LNA Design Project

Tao Cheng Dept. of Information Technology, UTU 5/29/2008

ETT_3047 RF ANALOG IC DESIGN PROJECT

CONTENT

1. PROJECT DESCRIPTION .......................................................................................................2 2. SPECIFICATIONS AND PROCESS PARAMETERS............................................................2 3. LNA PARAMETERS DESIGN..................................................................................................3

3.1 LNA Architecture ..............................................................................................................3 3.2 Short-Channel Effects For MOS Transistors .................................................................3

3.2.1 Mobility Degradation With Vertical Field................................................................3 3.2.2 Velocity Saturation ...................................................................................................4

3.3 Input/Output Impedance Matching ................................................................................4 3.4 Equivalent Transconductance of LNA ............................................................................5 3.5 Voltage Gain of LNA .........................................................................................................6 3.6 Noise Analysis ....................................................................................................................6

3.6.1 Calculation of output noise due to ing1......................................................................6 3.6.2 Calculation of output noise due to ind1......................................................................8 3.6.3 Noise Figure Calculation..........................................................................................8

3.7 Devices Size Selection........................................................................................................9 4. SIMULATION RESULTS ........................................................................................................11 5. REFERENCES..........................................................................................................................13 6. APPENDIX A: MATLAB CODE.............................................................................................14


1. PROJECT DESCRIPTION

This project is to design a classic Narrow Band Cascode Low Noise Amplifier (LNA) with Inductive Source Degeneration based on publication [5].

2. SPECIFICATIONS AND PROCESS PARAMETERS

Table 2.1 LNA Design Specifications

SPECS DESCRIPTION VALUES

f0 (GHz) Operation Frequency 2

Av (dB) Voltage Gain 20

S11 (dB) S11 -10

NF (dB) Noise Figure 4

IIP3 (dBm) Input 3rd Intercept Point -10

P1dB (dBm) Input 1-dB Compression Poin 0

Pdiss (mW) Power Dissipation < 10

Vdd (V) Power Supply 1.2

C2 (fF) Capacitive Loading 20

Technology 0.13um CMOS

Table 2.2 Process Parameters

PARAMETERS DESCRIPTIONS VALUES

Vthn Threshold voltage 0.36 (V)

μn Mobility of carrier 0.0311 (m2/v/s)

vsat Saturation velocity of carrier 1e5 (m/s)

tox Thickness of oxide 2.5e-9 (m)

θ mobility Degradation factor by vertical fields (θ≈10-7/tox) 40 (V-1)


3. LNA PARAMETERS DESIGN

3.1 LNA Architecture

Vo

L3

L2C1

Rs=50Ω

Vi

M2

M1

L1

R3C3

C2L4

Fig 3.1 LNA Architecture with Source Degenerative Inductor

Fig 3.1 shows the circuit of the designated LNA. For simplicity, bias circuit is not shown here. M1 and M2 in the figure form a cascode structure to reduce the output signal feed-through to the input due to gate-drain capacitance of M1.

1 1m gsg v

2 2m gsg v

2gsv

1gsv2 2mb gsg v

1Lv

1 1mb Lg v

Fig 3.2 Small Signal Equivalent Circuit of LNA

C1 is input coupling capacitors. C2 is capacitive loading. L1, L2 and Cgs1 form an input impedance matching network to realize maximum power delivery at resonance. Output type-π matching network consists of L3, C3 and L4. In practice, C3 may need to be tunable to compensate parasitic effects. A relatively complete small signal equivalent model of Fig 3.1 is provided by Fig 3.2. R2 is the total series parasitic resistance of L2 and M1 gate which is neglected in the following analysis.

3.2 Short-Channel Effects For MOS Transistors

There are two kinds of important short-channel effects which should be mentioned here in order to validate our later analysis: mobility degradation with vertical field and velocity saturation.

3.2.1 Mobility Degradation With Vertical Field

Small-geometry devices experience significant mobility degradation due to the high vertical electric field because large gate-source voltage confines the charge carriers to a narrow region below the oxide-silicon interface leading to more carriers scattering and hence lowering the mobility. An empirical equation modeling this effect is [1]:


( )

0

1effgs thV Vμ

μθ

=+ −

, ( 710 oxtθ −= ) (3.01)

In whichθ is a fitting parameter [2]. Thus, in linear region of MOS transistor, the drain-source current should be modified as:

( )

( ) ( )0 2121

oxds gs th ds ds

gs th

C W LI V V V V

V Vμ

θ⎡ ⎤= − −⎢ ⎥+ − ⎣ ⎦

(3.02)

The drain-source conductance at the point of Vds=0 is:

( )( )( )

00 0 1ds

ox gs thdsd V

ds gs th

C W L V VIg

V V V

μ

θ=

−= =

+ − (3.03)

3.2.2 Velocity Saturation

The mobility of carriers also will degrade when lateral electric field approaches a sufficiently high level because the velocity of carriers is going to saturate under this condition [1]. A compact and versatile equation developed to represent the saturation drain-source current considering the effects of large vertical and lateral electric fields is given by:

( )

( )

2

00

12

12

gs thds ox

gs thsat

V VWI CL

V Vv L

μμ

θ

−=

⎛ ⎞+ + −⎜ ⎟⎝ ⎠

(3.04)

Where vsat is the saturation velocity of carriers. The degradation of mobility with both lateral and vertical electric fields are represented by parametersθ and u0/(2vsatL).

3.3 Input/Output Impedance Matching

The circuit of input impedance calculation is shown in Fig 3.3(a) in which the total series parasitic resistance of L2 and M1 gate is neglected to simplify the analysis. According to KVL, we have:

( )1 2 1 2 1 1 11

1x gs L L x x m gs

gsv v v v i sL i g v sL

sC⎛ ⎞

= + + = ⋅ + + + ⋅⎜ ⎟⎜ ⎟⎝ ⎠

( ) 11 2 1

1 1

1x mi

x gs gs

v gZ s L L L

i sC C= = + + + (3.05)

In order to maximize the power transfer at resonant frequency, the real part of Zi must be equal to Rs and the imaginary part must be equal to zero, which gives:

( )

( ) ( ) ( )

11 1 1 1

1

20 1 2 0

0 1 1 2 1

Re

1 1Im 0

mi s m gs s

gs

igs gs

gZ L R g L C R

C

Z L LC L L C

ω ωω

⎧ = = → =⎪⎪⎨⎪ = + − = → =⎪ +⎩

(3.06)

The input quality factor Qi is:


( )0 1 2

01 10

1 12 2i

gs s smgs s

gs

L LQ

C R Rg LC RC

ωω

ω

+= = =

⎛ ⎞+⎜ ⎟⎜ ⎟

⎝ ⎠

(3.07)

1 1m gsg v

2 2m gsg v

2gsv1gsv

1 1m gsg v

2 2m gsg v

2gsv1gsv

(a) Zi Calculation (b) Gm Calculation

Fig 3.3 Equivalent Circuit for Input Impedance Zi and Transconductance Gm Calculation

At the output port, L3,C3 and L4 forms an output matching network when circuit is resonating, their sizes are calculated with the help of CAD tool RFSIM99 [7].

3.4 Equivalent Transconductance of LNA

The circuit of equivalent transconductance calculation is shown in Fig 3.3(b), to evaluate equivalent transconductance Gm, the following equation can be given:

( ) ( )

1 1

1 1 2 1 1 1 1 1 1

y m gs

i gs gs s gs m gs gs gs

i g v

v sC v R sL v sL g v sC v

=⎧⎪⎨

= ⋅ + + + +⎪⎩

( ) ( ) ( ) ( )1

21 1 1 1 1 21

y mm

i m s gs gs

i gG j j

v j g L R C C L Lω ω

ω ω= =

+ + − + (3.09)

Noting (3.06) and (3.07), Gm at resonant frequency is then got by plugging the two equations into the (3.09):

( ) 1,0 0 1

0 1 0 0 1

12 2 4

m Tm m m i

s gs s

g fG G j g Q

R C f R f Lω

ω π= = = ≈ = (3.10)

0.20.4

0.60.8

1 00.2

0.40.6

0.80

100

200

300

400

Vgs-Vth (V)

Cut-off Frequency .vs. Vgs-Vth

L (um)

fT (G

Hz)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

-0.05

0

0.05

0.1

0.15

0.2

Vgs-Vth (V)

Af=

f0/ft

Af .vs. Vgs-Vth

θ≠0θ=0

Fig 3.4 fT .vs. Vgs-Vth Determined By (3.11) Fig 3.5 αf .vs. Vgs-Vth


Where fT≈gm1/(2πCgs1) is the cut-off frequency of NMOS transistors. Since Cgs1≈(2/3)WLCox, gm1=unCox(W/L)(Vgs-Vth), so fT is given by (3.11) and its relation with L & Vgs-Vth is shown in Fig 3.4:

( ) ( )2

3440 (GHz)

4n gs th

T gs th

V Vf V V

L

μ

π

−≈ ≈ − (3.11)

3.5 Voltage Gain of LNA

The voltage gain is given by:

( ) ( ) 3 33 1 3

020 log 20log 20log 20log

2 2T

v m m is f s

f R RA G R g Q R

f R Rα

⎛ ⎞⎛ ⎞= = = = ⎜ ⎟⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

(3.12)

In which αf=f0/fT. The variation of αf with overdrive voltage is shown in Fig 3.5. Given the spec. of 20dB voltage gain, we have:

320 log 202v

f s

RA

Rα

⎛ ⎞= ≥⎜ ⎟⎜ ⎟

⎝ ⎠ 3 20 1000f s fR Rα α≥ = (3.13)

From Fig 3.5 we can see that minimum αf is about 0.06 and 0.01 at θ≠0 and θ=0 respectively, so minimum R3 should be larger than 60Ω and 10Ω.

3.6 Noise Analysis

Fig 3.6 shows the key noise sources [3][4] for the simplified small signal equivalent circuit given by Fig 3.2 in which ing1 is gate induced noise current, ind1 is channel noise current of M1 including thermal and flicker noise and ino,LNA is the total equivalent output noise current due to ing1 and ind1. The noise caused by cascode transistor M2 can be neglected [1].

1 1m gsg v1gsv

2nsv

21ngi

21ndi

1Lv

1 1m gsg v1gsv

2nsv

2,no LNAi

1Lv

Fig 3.6 Noise Model of LNA

The values of ing1 and ind1 are given by:

2 2

121

04 4

5gs

ng gd

Ci kT g kT

gω

δ δ= = , 21 04nd di kT gγ= (3.14)

Where typically δ=2γ=6. gd0, the drain-source resistance of M1 at Vds=0, is given by (3.03) and gm1, the transconductance of M1, is determined by the derivative of Ids with Vgs in (3.04). Fig 3.7 shows the relation between Vgs-Vth and gm1, gd0 and the ratio αg of gm1 and gd0 with and without consideration of θ.

3.6.1 Calculation of output noise due to ing1

In order to get ing1 induced output noise, we should firstly calculate Zgs1. The circuit for Zgs1 calculation is shown in Fig 3.8(a). We have:


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

2

4

6

8

10

12

14

16

Vgs-Vth (V)

gm1

(mS)

gm1 & gd0 .VS. Vgs-Vth (θ≠0)

gm1gd0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.5

0.6

0.7

0.8

0.9

1

1.1

1.2

Vgs-Vth (V)

αg=g

m1/

gd0

αg .VS. Vgs-Vth (θ≠0)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

100

200

300

400

500

600

Vgs-Vth (V)

gd0

& g

m1

(mS)

gm1 & gd0 .VS. Vgs-Vth (θ=0)

gm1gd0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Vgs-Vth (V)

αg=g

m1/

gd0

αg .VS. Vgs-Vth (θ=0)

Fig 3.7 Vgs-Vth .vs. gm1, gd0 and Vgs-Vth .vs. αg (W=200um, L=0.13um, )

1 1 1

1 11

2 1

x L gs x m x

x L Lm x

s

i v sC v g v

v v vg v

sL R sL

+ = +⎧⎪

+⎨ + =⎪ +⎩

( ) ( )( ) ( )

1 22

1 2 1 1 1 11sx

x gs m s gs

R j L Lvj

i L L C j g L R Cω

ωω ω

+ +=

− + + + (3.15)

At resonant frequency point, plug the result of (3.06) and (3.07) into the above equation:

( ) ( )1 0 2xgs s i i

x

vZ j R Q Q j

iω= = − 2

1 1 4gs s i iZ R Q Q= + (3.16)

Then:

, 1 1 1 1 1 1no g m gs ng g ngi g Z i iη= ⋅ = ⋅ (3.17)

In which

1 1 1g m gsg Zη = 21 1 1 1 1 4g m gs m s i ig Z g R Q Qη = = + (3.18)

Cgs1

L1

1 1m gsg v1gsvL2

Rs=50Ω

Zgs1

1Lv

Vx

Ix

Cgs1

L1

1 1m gsg v1gsvL2

Rs=50Ω

1Lv

21ndi

2, 1no di

Fig 3.8 ino,tot Calculation (a) Circuit for Zgs1 Calculation (b) Circuit for ino,d1 Calculation


3.6.2 Calculation of output noise due to ind1

The circuit for ino,d1 Calculation is shown in Fig 3.8(b). We have:

( )( ) ( )

( )

11 1

1 , 1 1 2 1 12 1

, 1 1 1 1

|| gsgs no d s gs

s gs

no d m gs nd

sCv i sL R sL sC

R sL sC

i g v i

−−

−

⎧⎡ ⎤⎪ = − ⋅ + + ⋅⎪ ⎢ ⎥⎣ ⎦⎨ + +

⎪= +⎪⎩

( ) ( )( ) ( )

21 2 1 1, 1

21 1 2 1 1 1 1

1

1gs s gsno d

nd gs m s gs

L L C j R Cij

i L L C j g L R C

ω ωω

ω ω

− + +=

− + + + (3.19)

At resonant frequency point, plug the result of (3.06) and (3.07) to the above equation and we can get:

( ) 1, 11 0

1 1 1 1

12

s gsno dd

nd m s gs

R Cij

i g L R Cη ω= = =

+ 1

12dη = (3.20)

Then the expression of ino,tot is:

2 * * * * 2 2 2 2 * *, 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12Reno LNA g ng d nd g ng d nd g ng d nd ng nd d gi i i i i i i i iη η η η η η η η⎡ ⎤⎡ ⎤= + ⋅ + = + + ⋅⎣ ⎦ ⎢ ⎥⎣ ⎦

2 2

1 12 2 2 2 2 2 * 2 2 21 1 1 1 1 1 1 1 1 1 1 1 12 2

1 1

2 Re 2 Reng ngg ng d nd ng nd g d nd d g d g

nd nd

i ii i c i i i c

i iη η η η η η η η

⎛ ⎞⎧ ⎫⎪ ⎪⎜ ⎟= + + ⋅ = + + ⋅⎨ ⎬⎜ ⎟

⎜ ⎟⎪ ⎪⎩ ⎭⎝ ⎠

( )2 2 2 20 1 0 12 2 2 2 2 2

1 1 1 1 1 12 20 0

1 4 2Re5 5

gs gsnd d m s i i d m gs

d d

C Ci g R Q Q j c g Z

g g

δω δωη η

γ γ

⎛ ⎞⎛ ⎞⎜ ⎟⎜ ⎟= + + ⋅ + − ⋅ ⋅ ⋅⎜ ⎟⎜ ⎟

⎝ ⎠⎝ ⎠

( )2 2

2 2 1 11 1 1 0 12

00

1 42 Re 1 2

5 4 5m i m

nd d d gs s i idd

g Q gi C R Q c j Q

ggδ δη η ωγ γ

⎛ ⎞⎧ ⎫+ ⎪ ⎪= + ⋅ − ⋅ ⋅ ⋅ +⎜ ⎟⎨ ⎬⎜ ⎟⎪ ⎪⎩ ⎭⎝ ⎠

( )2 2 2 21 1 1

1 1 44nd d i di Q cη χ η χ⎛ ⎞= + + −⎜ ⎟

⎝ ⎠ (3.21)

In which

*

1 1

2 21 1

12

ng nd

ng nd

i ic j

i i

⋅= ≈

⋅,

222 1

20 5 5

gm

d

gg

α δδχγ γ

= ⋅ = (3.22)

3.6.3 Noise Figure Calculation

The output noise due to input source is:

2 2 2 2 2, 1 4no src m ns m i si G v g Q kTR= = ⋅ (3.23)

The noise factor of the designated LNA is:

( )2 2 2

2 1 1 0,

2 221,

1 1 4 441 1

4

d i d dno LNA

m i sno src

Q c kT giF

g Q kTRi

η χ η χ γ⎛ ⎞+ + − ⋅⎜ ⎟⎝ ⎠= + = +

⋅

( )2 2 201 1

1 1

1 11 1 44

dd i d

m i s i m

gQ c

g Q R Q gγ

η χ η χ⎛ ⎞= + ⋅ ⋅ + + −⎜ ⎟⎝ ⎠


( )2 2 21 1

,0

11 1 44d i d

m s g iQ c

G R Qγ η χ η χα

⎛ ⎞= + ⋅ + + −⎜ ⎟⎝ ⎠

( )2 2 201 1

11 1 44d i d

g i T

fQ c

Q fδ η χ η χ

α⎛ ⎞= + ⋅ + + −⎜ ⎟⎝ ⎠

( )2 2 211 0.5 1 4 0.54

fi

g iQ c

Qα δ

χ χα

⎛ ⎞= + ⋅ + + − ⋅⎜ ⎟⎝ ⎠

( )2 21 1 2 1 44

fi

g ic Q

Qα δ

χ χα

⎡ ⎤= + ⋅ − + +⎣ ⎦ (3.24)

In which αf=f0/fT. For short-channel devices, typically γ is equal to 2~3 depending on bias condition [6] and δ=2γ. In this design, we set γ=3, δ=6, so (3.19) changes to:

( )2 261 1 2 0.4 0.5 0.4 1 4

4f

g g ig i

F QQ

αα α

α⎡ ⎤= + ⋅ − ⋅ + +⎣ ⎦

( )2 21 1.5 1 0.4 0.4 1 4fg g i

g iQ

Qα

α αα

⎡ ⎤= + ⋅ − + +⎣ ⎦ (3.25)

Fig 3.9 and Fig 3.10 shows the relation of power dissipation and noise figure and overdrive voltage.

0 0.05 0.1 0.15 0.2 0.25 0.30

5

10

15

20

25

30

Vgs-Vth (V)

Pdis

s (m

W)

Pdiss .vs. Vgs-Vth

W=50umW=100umW=150umW=200um

0 0.05 0.1 0.15 0.2 0.25 0.3

0

1

2

3

4

5

6

Vgs-Vth (V)

NF

(dB)

NF .vs. Vgs-Vth

W=50umW=100umW=150umW=200um

Fig 3.9 Pdiss .vs. Vgs-Vth Fig 3.10 NF .vs. Vgs-Vth

3.7 Devices Size Selection

According to the specifications and the above analysis, we can calculate the detailed devices parameters. First, we select (W1/L1)=(W2/L2)=200μm/0.13μm (channel width can not be too small, otherwise the L2 in input matching network might be too large to be integrated), (Vgs-Vth)=0.1V, so gm1≈55mS, Cgs1≈240fF.

From (3.06), L1=RsCgs1/gm1≈0.22nH, L2=[(2πf0)2·Cgs1]-1-L1≈26.2nH. From Fig (3.5), αf≈0.01, so R3 must be larger than 10Ω according to (3.13). Here we set R3=180Ω. As for L3, C3 and L4, using RFSIM99, the calculated results are L3=2.87nH, C3=1.53pF and L4=1.6nH under the bandwidth of 400MHz. The following Table 3.1 summaries the result of our design parameters.


Table 3.1 Design Parameters

W1/L1 200 μm/0.13 μm Vgs-Vth 100 mV

W2/L2 200 μm/0.13 μm Ibias 0.13 mA

L1 0.22 nH C1 10 pF

L2 26.2 nH C2 20 fF

L3 2.87 nH C3 1.5 pF

L4 1.60 nH R3 180 Ω


4. SIMULATION RESULTS

This section gives the complete schematic and simulated results of designated LNA under typical corner. Table 4.1 and 4.2 summarize the final simulated device sizes and performance.

Fig 4.1 Schematic of Source Degenerated LNA


Fig 4.2 Waveform of S-parameters, Voltage Gain, Noise Figure IP3 and P1dB

Fig 4.3 Transient Waveform of LNA


Table 4.1 Device Sizes

W1/L1 25*8 μm/0.13 μm W0/L0 8 μm/0.13 μm

W2/L2 25*8 μm/0.13 μm W4/L4 8 μm/0.13 μm

Vgs-Vth 90 mV Ibias 0.24 mA

L1 0.30 nH C1 10 pF

L2 16.9 nH C2 20 fF

L3 2.40 nH C3 1.53 pF

L4 1.60 nH R3 180 Ω

Table 4.2 Simulated Performace

S11/S22/S21/S12 -22/-22/23/-35 dB Gain 28 dB

IIP3/OIP3 -13.2/9.9 dBm NF 0.12 dB

Input/Output P1dB -26.38/-4.34 dBm Pdiss <9.5 mW

5. REFERENCES

[1] B. Razavi, “Design of Analog CMOS Integrated Circuits”, Singapore: McGraw Hill, 2001. [2] C. G. Sodini, P. K. Ko and J. L. Moll, “The Effect of High Fields on MOS Device and Circuit

Performance”, IEEE Tran. On Electron Devices, Vol.31, pp.1386-1393, Oct.1984. [3] J. S. Goo, “High Frequency Noise in CMOS Low Noise Amplifiers”, PhD Thesis, Stanford

University, Aug.2001. [4] T. Sepke, “Investigation of Noise Sources in Scaled CMOS Field-Effect Transistors”, MS Thesis,

MIT, Jun.2002. [5] D. K. Shaeffer, T. H. Lee, “A 1.5-V, 1.5-Ghz CMOS Low Noise Amplifier”, IEEE JSSC, Vol.32,

No.5, May 1997. [6] A. A. Abidi, “High-Frequency Noise Measurements on FET’s with Small Dimensions”, IEEE

Transactions on Electron Devices, Vol.ED-33, No.11, Nov. 1986. [7] RFSIM99, http://www.rfglobalnet.com/


6. APPENDIX A: MATLAB CODE

%function ett3047_prj

%-----------------------------------------------------------------------------

%[DESCRIPTION]

% This program implements the following main functions:

% 1)Plot the gm1,gd0 and gm0/gd0 .vs. (vgs-vth)

% 2)Plot f0/ft .vs. (vgs-vth)

% 3)Plot NF .vs. (vgs-vth)

% 4)Plot Pdiss .vs. (vgs-vth)

%

%[USAGE]

% ett3047_prj

%

%[AUTHOR]

% Tao Cheng

%[DATE]

% 2008.05.30

%-----------------------------------------------------------------------------

%clear all;

%clc;

% Channel Width & Length of NMOS Transistor

W=200e-6;

L=0.13e-6;

% Threshold Voltage of NMOS Transistor

Vth=0.36;

% Supply Voltage

Vdd=1.2;

% Mobility of Long-Channel NMOS Transistor

U0=0.0311;

% Gate-Oxide Thickness

Tox=2.5e-9;

% Gate-Oxide Capacitance

Cox=3.9*8.85e-12/Tox; % Cox=0.0138F/(m*m)

% Gate-Source and Gate-Drain Capacitance for Saturated NMOS Transistor

Cgs=(2/3)*W*L*Cox; % Cgs=240fF

% Impedance of Input Voltage Source

Rs=50;

% Load Impedance

R3=75;

% Operation Frequency of LNA

f0=2e9;

% A Fitting Parameter For Degradation of Mobility By Vertical Fields

Thita=1e-7/Tox;


% Saturation Velocity of Carriers For Degradation of Mobility By Lateral Fields

Vsat=1e5;

% Effects of Combination "Thita" & "Vsat"

Thita0=Thita+U0/(2*Vsat*L); % "Thita" is considered

Thita1=U0/(2*Vsat*L); % "Thita" is not considered

% Setup the Range of Gate-Source Voltage

Vgs=[Vth:0.01:Vdd];

% The Drain-Source Current Considering Mobility Degradation Effects (mA)

Id0=inline('1e3*0.5*U0*Cox*(W/L)*(Vgs-Vth).^2./(1+Thita0*(Vgs-Vth))','Vgs','Vth','U0',

'Cox','W','L','Thita0');

Id1=inline('1e3*0.5*U0*Cox*(W/L)*(Vgs-Vth).^2./(1+Thita1*(Vgs-Vth))','Vgs','Vth','U0',

'Cox','W','L','Thita1');

% Transconductance of NMOS Transistor

gm0=diff(Id0([Vgs,1.21],Vth,U0,Cox,W,L,Thita0))/0.01;

gm1=diff(Id1([Vgs,1.21],Vth,U0,Cox,W,L,Thita1))/0.01;

% Drain-Source Conductance at Vds=0

gd0=1e3*U0*Cox*(W/L)*(Vgs-Vth)./(1+Thita0*(Vgs-Vth)); % "Thita" is considered

gd1=1e3*U0*Cox*(W/L)*(Vgs-Vth); % "Thita" is not considered

% Ratio of "gm0" and "gd0"

Ag0=gm0./gd0; % "Thita" is considered

Ag1=gm1./gd1; % "Thita" is not considered

% Cut-off Frequency of NMOS Transistor

ft0=1e-3*gm0/Cgs; % "Thita" is considered

ft1=1e-3*gm1/Cgs; % "Thita" is not considered

% Ratio of "f0" and "ft"

Af0=f0./ft0; % "Thita" is considered

Af1=f0./ft1; % "Thita" is not considered

% Input Quality Factor of LNA

Qi=1/(4*pi*f0*Cgs*Rs);

% Input Quality Factor of LNA .vs. W

W1=1e-6*[30:10:200];

Cgs1=(2/3)*W1*L*Cox;

Qi1=1./(4*pi*f0*Cgs1*Rs);

% Equivalent Transconductance Gm of LNA

Gm0=gm0*Qi; % "Thita" is considered

Gm1=gm1*Qi; % "Thita" is not considered

% Voltage Gain Av

Av0=20*log10(Gm0*R3/1e3); % "Thita" is considered

Av1=20*log10(Gm1*R3/1e3); % "Thita" is not considered


% Noise Factor and Noise Figure of LNA

F0=1+1.5*Af0./(Ag0.*Qi).*(1-sqrt(0.4).*Ag0+0.4*Ag0.^2.*(1+4*Qi.^2)); % "Thita" is

considered

F1=1+1.5*Af1./(Ag1.*Qi).*(1-sqrt(0.4).*Ag1+0.4*Ag1.^2.*(1+4*Qi.^2)); % "Thita" is not

considered

NF0=10*log10(F0); % "Thita" is considered

NF1=10*log10(F1); % "Thita" is not considered

% Power Dissipasion

Pdiss0=Vdd*Id0(Vgs,Vth,U0,Cox,W,L,Thita0); % "Thita" is considered

Pdiss1=Vdd*Id1(Vgs,Vth,U0,Cox,W,L,Thita1); % "Thita" is not considered

% Plot Curves

%--------------------------------------------------------------------------

% Plot gm0,gd0,Ag0;gm1,gd1,Ag1;

%figure(1);

%subplot(2,2,1);

%plot(Vgs-Vth,gm0,'r',Vgs-Vth,gd0,'b');grid on;

%xlim([0 0.8]);%ylim([-50 300]);

%xlabel('Vgs-Vth (V)');ylabel('gm1 (mS)');

%subplot(2,2,2);

%plot(Vgs-Vth,Ag0,'b');grid on;

%xlim([0 0.8]);%ylim([0.4 1.1]);

%xlabel('Vgs-Vth (V)');ylabel('Ag');

%subplot(2,2,3);


%xlim([0 0.8]);%ylim([-50 300]);


%subplot(2,2,4);



%xlim([0 0.8]);%ylim([-50 300]);

%figure(1);


%xlim([0 0.8]);%ylim([-50 300]);


%title('gm1 & gd0 .VS. Vgs-Vth (θ≠0)');

%figure(2);


%xlim([0 0.8]);%ylim([0.4 1.1]);


%title('Ag0 .VS. Vgs-Vth (θ≠0)');

%figure(3);



%xlim([0 0.8]);%ylim([-50 300]);


%title('gm1 & gd0 .VS. Vgs-Vth (θ=0)');

%figure(4);



%xlim([0 0.8]);%ylim([-50 300]);

%title('Ag0 .VS. Vgs-Vth (θ=0)');

%--------------------------------------------------------------------------

% Plot Af;

%figure(2);

%plot(Vgs-Vth,Af0,'b',Vgs-Vth,Af1,'r');grid on;xlim([0 0.8]);ylim([-0.05 0.2]);

%xlabel('Vgs-Vth (V)');ylabel('Af=f0/ft');

%title('Af .vs. Vgs-Vth');

%figure(2);

%plot(Vgs-Vth,Af0,'b');grid on;xlim([0 0.8]);%ylim([0.04 0.2]);


%title('Af .vs. Vgs-Vth (θ=0)');

%figure(3);

%plot(Vgs-Vth,Af1,'b');grid on;xlim([0 0.8]);%ylim([0.04 0.2]);


%title('Af .vs. Vgs-Vth (θ≠0)');

%--------------------------------------------------------------------------

% Plot ft;

%figure(3);

%[L2,Vgs2]=meshgrid(1e-6*[0.13:0.05:1],[Vth:0.05:Vdd]);

%Cgs2=(2/3)*W*L2*Cox;

%gm2=U0*Cox*(W./L2).*(Vgs2-Vth);

%ft2=gm2./(2*pi*Cgs2);

%surf(L2*1e6,Vgs2-Vth,ft2/1e9);xlim([0.1 1]);ylim([0 0.8]);

%--------------------------------------------------------------------------

% Plot Qi;

%figure(4);

%plot(W1*1e6,Qi1,'b');hold off;grid on;

%xlabel('W (um)');ylabel('Qi');xlim([30 200]);

%title('Qi .vs. W');

%--------------------------------------------------------------------------

% Plot Av;

%figure(5);

%plot(Vgs-Vth,Av1,'b');hold on;grid on;

%xlabel('Vgs-Vth (V)');ylabel('Av (dB)');xlim([0 0.8]);

%title('Av .vs. Vgs-Vth');

%--------------------------------------------------------------------------


% Plot Pdiss;

%figure(6);

%plot(Vgs-Vth,Pdiss1,'r');hold on;grid on;xlim([0 0.3]);%ylim([0 8]);

%xlabel('Vgs-Vth (V)');ylabel('Pdiss (mW)');

%title('Pdiss .vs. Vgs-Vth');

%--------------------------------------------------------------------------

% Plot NF;

%figure(7);

%plot(Vgs-Vth,NF1,'r');hold on;grid on;xlim([0 0.3]);%ylim([1 7]);

%xlabel('Vgs-Vth (V)');ylabel('NF (dB)');

%title('NF .vs. Vgs-Vth');

Documents

LNA Design Project