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Electronic DevicesKEEE 2224

Lecture 8Complementary Metal-Oxide-

Semiconductor (CMOS)

Dr. Ghafour Amouzad Mahdiraji

November 2012

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n-Channel MOSFETs

Depletion-type MOSFET:The device is ON at zero gate voltage.

Enhancement-type MOSFET:The device is OFF at zero gate voltage.

A +tive gate voltage induces the electroninversion layer, which then connects then-type source to drain regions.

Electron inversion layer exist at 0 V andcan be off with -tive voltage.

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p-Channel MOSFET

p-channel depletion mode MOSFET. p-channel enhancement mode MOSFET

A -tive gate voltage must be applied tocreate an inversion layer of holes thatwill connect the p-type source to drainregions.

Electron inversion layer exist at 0 V andcan be off with +tive voltage.

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Complementary MOS (or CMOS) Devices

We have discussed both n-channel and p-channel enhancement MOSFETs.When both devices are used in a circuit, they form a Complementary MOS(or CMOS).

CMOS inverter is one of the basis of CMOS digital logic circuits. The dc power dissipation in a digital circuit can be reduced to very low

levels by using a complementary p-channel and n-channel pair. Usually, such devices fabricated in one cheep using integrated circuit. It is

necessary to form electrically isolated p- and n-substrate regions in anintegrated circuit to accommodate the n- and p-channel transistors.

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p- and n-Channel MOSFETs in Enhancement Modebefore applying +ve & -ve gate voltage

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p- and n-Channel MOSFETs in Enhancement Modeafter applying +ve & -ve gate voltage

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InputOutput

GND

V DD

G a

t e

S

u b s

t r a

t e

n

n

S

D

p

G a

t e

S u

b s

t r a

t e

D

S

n

Input=

LowOutput = High

GND

V DD

+ + + +

+ + + + +

p

p

G a

t e

S

u b s

t r a

t e

S

D

p

G a

t e

S u

b s

t r a

t e

D

S

n

Input=

HighOutput = Low

GND

V DD

p

p

- - - - - - - - - - - - -

n

n

- - - - - - - - -

p- & n-Channel MOSFET: Complementary MOS Inverter

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CMOS Inverter

For small values of the input voltage, V IN, the nMOS transistor is switched off,whereas the pMOS transistor is switched on and connects the output mode to V DD.

For large values of the input voltage, V IN, the pMOS transistor is switched off,whereas the nMOS transistor is switched on and connects the output mode to GND= 0V.

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CMOS Inverter Circuits

V DD

S

S

D

D

OutputInput

p channel

n channel

GNDEnhancement mode

V DD

S

S

D

D

OutputInput

p channel

n channel

GND

Depletion mode

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Note that when the input voltage increase from 0V to 5V the output voltage decreasesfrom 5V to 0V.

In region 1 VOUT = V DD and I D = 0. In region 3 VOUT = 0V and I D = 0.

In region 2 the transistor remains onlyfor a short period of time, when theinput voltage switches between V Land V H.In this region there is non-zero currentflowing between V DD and GND, andsome power dissipation, which isconverted into heat.

The fact that in regions 1 and 3 NOcurrent flows between V DD and GND,is very attractive because there is no

power dissipation at this stages. Thisvery fact is the reason that all digitalcircuitry is now build in the CMOStechnology.

Note that the same current flowsthrough the pMOS and nMOStransistors, that is, I Dp = I Dn .

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Example of CMOS Structures