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EEC 116 Lecture #4:CMOS Inverter AC
Characteristics
Rajeevan AmirtharajahUniversity of California, Davis
Jeff ParkhurstIntel Corporation
Amirtharajah/Parkhurst, EEC 116 Fall 2011 2
Acknowledgments
• Slides due to Rajit Manohar from ECE 547 Advanced VLSI Design at Cornell University
Amirtharajah/Parkhurst, EEC 116 Fall 2011 3
Announcements
• Lab 2 this week, report due next week
• Quiz 1 on Monday!
Amirtharajah/Parkhurst, EEC 116 Fall 2011 4
Outline
• Review: CMOS Inverter Transfer Characteristics
• Finish Lecture 3 slides
• CMOS Inverters: Rabaey 5.4-5.5 (Kang & Leblebici, 6.1-6.4, 6.7)
Amirtharajah/Parkhurst, EEC 116 Fall 2011 5
CMOS Inverter VTC: Device Operation
P linearN cutoff
P linearN sat P sat
N sat
P satN linear
P cutoffN linear
Amirtharajah/Parkhurst, EEC 116 Fall 2011 6
Logic Circuit Delay
• For CMOS (or almost all logic circuit families), only one fundamental equation necessary to determine delay:
• Consider the discretized version:
• Rewrite to solve for delay:
• Only three ways to make faster logic: C, ΔV, I
dtdVCI =
tVCIΔΔ
=
IVCt Δ
=Δ
Amirtharajah/Parkhurst, EEC 116 Fall 2011 7
CMOS Inverter Capacitances
Vin
Vdd
Gnd
Cgd,p
Cgs,p
Cdb,p
Csb,p
Cgd,n
Cgs,n Csb,n
Cdb,n CintCg
f
• Assume input transition is fixed, then delay determined by output
Capacitance on node f (output):
• Junction capCdb,p and Cdb,n
• Gate capacitanceCgd,p and Cgd,n
• Interconnect cap• Receiver gate cap
Amirtharajah/Parkhurst, EEC 116 Fall 2011 8
CMOS Inverter Junction Capacitances• Junction capacitances Cdb,p and Cdb,n:
– Equation for junction cap:
– Non-linear, depends on voltage across junction
– Use Keq factor to get equivalent capacitance for a voltage transition
( )m
da
dajm
jj NN
NNqCV
ACVC ⎟⎟
⎠
⎞⎜⎜⎝
⎛+
=
⎟⎟⎠
⎞⎜⎜⎝
⎛−
=0
0
0
0 12
,
1φ
ε
φ
jsweqswjeqdb CPKCAKC +=
Amirtharajah/Parkhurst, EEC 116 Fall 2011 9
CMOS Inverter Gate Capacitances
• Gate capacitances CGD,p and CGD,n:
– Just after the input switches(t = 0+), what regions are transistors in?
– One is in cutoff: CGD = Overlap Cap
– One is in Saturation: CGD = Overlap Cap
– Therefore, gate-to-drain capacitance is due to overlap capacitance :
Doxngdpgd WLCCC == ,,
However, also need to consider Miller effect ...
Amirtharajah/Parkhurst, EEC 116 Fall 2011 10
CMOS Inverter Capacitances: Miller Effect
• When input rises by ΔV, output falls by ΔV
– Change in stored charge: ΔQ = Cgd1ΔV – (-Cgd1ΔV)
– Effective voltage change across Cgd1 is 2ΔV
– Effective capacitance to ground is twice Cgd1
• Including Miller effect:
Vin
VoutCgd1
Vin
Vout
2Cgd1
Doxngdpgd WLCCC 2,, == (For transistor in Cutoff)
Amirtharajah/Parkhurst, EEC 116 Fall 2011 11
CMOS Inverter Capacitances: Receiver
• Receiver gate capacitance
– Includes all capacitances of gate(s) connected to output node
– Unknown region of operation for receiver transistor: total gate cap varies from (2/3)WLCox to WLCox
– Ignore Miller effect (taken into account on output)
– Assume worst-case value, include overlap
oxDoxeffg CWLCWLC 2+=
Cg = WL Cox
Amirtharajah/Parkhurst, EEC 116 Fall 2011 12
Inverter Capacitances: Analysis
• Simplify the circuit: combine all capacitances at output into one lumped linear capacitance:
Cload = 2*Cgd,n + 2*Cgd,p + Cdb,n + Cdb,p + Cint+ Cg
• Csb,n = Csb,p = 0
• Cgs,n and Cgs,p are not connected to the load. These are part of the gate capacitance Cg
Miller effect
Amirtharajah/Parkhurst, EEC 116 Fall 2011 13
First-Order Inverter Delay
• Suppose ideal voltage step at input
• Assume: Current charging or discharging capacitance Cload is nearly constant Iavg
• tPHL = Cload (Vdd - Vdd/2) / Iavg
• tPLH = Cload (Vdd/2 - Vss) / Iavg
VinVout
Cload
Amirtharajah/Parkhurst, EEC 116 Fall 2011 14
ID.n
Inverter Delay: Falling
• Assume PMOS fully off (ideal step input, ID,p = 0)
CloadVin
dtdVCI
dtdVCI
outloadnD =
=
, Need to determine ID,n
Amirtharajah/Parkhurst, EEC 116 Fall 2011 15
Inverter Delay: Falling
• From t0 to t1: NMOS in saturation
• From t1 to t2: NMOS in linear region
• Find ID in each region
VddVdd - Vtn
Vdd/2
t0 t1 t2
NMOS in saturation
NMOS in linear region
Amirtharajah/Parkhurst, EEC 116 Fall 2011 16
Inverter Delay: Falling t1-t0• Assumption: Input fast enough to go through
transition before output voltage changes
• Vout drops from VOH to VDD-VTN (NMOS saturated)
2,0
,001
2,0
2,0
2,0
)(2
)(2
2/)(2/)(,01
0
nTOHn
nTL
VV
Vout
nTOHn
Lt
t
nTOHnnTinnDS
VVkVC
tt
dVVVk
Cdt
VVkVVkInTOH
OH
−=−
−−
=
−=−=
∫∫−
Amirtharajah/Parkhurst, EEC 116 Fall 2011 17
Inverter Delay: Falling t2-t1
• Vout drops from (VOH-VT0,n) to VDD/2• NMOS in linear region
[ ]
[ ]
⎥⎦
⎤⎢⎣
⎡+
+−−−
=−
−−−=−
−−=
∫+
−
2/)(2/)()(2
ln)(
)(
)(
,0
,012
2/)(
221
,012
221
,0
,0
OLOH
OLOHnTOH
nTOHn
L
VV
VV outoutnTOHn
outL
outoutnTOHnDS
VVVVVV
VVkCtt
VVVVkdVCtt
VVVVkIOLOH
nTOH
Amirtharajah/Parkhurst, EEC 116 Fall 2011 18
Inverter Delay: Falling, Total
• Total fall delay = (t1-t0) + (t2-t1)
⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛−
+−
+−−
= 1)(4
ln2
)(,0
,0
,0
,0 OLOH
nTOH
nTOH
nT
nTOHn
LPHL VV
VVVV
VVVk
Ct
Amirtharajah/Parkhurst, EEC 116 Fall 2011 19
Inverter Delay: Rising
• Similar calculation as for falling delay
• Separate into regions where PMOS is in linear, saturation
• Note: to balance rise and fall delays (assuming VOH = VDD, VOL = 0V, and VT0,n=VT0,p) requires
5.2≈=⎟⎠⎞
⎜⎝⎛
⎟⎠⎞
⎜⎝⎛
p
n
n
p
LWLW
μμ
⎥⎥⎦
⎤
⎢⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛−
+
−−+
−−−−= 1
)(4ln
2)(
,0
,0
,0
,0 OLOH
pTOLOH
pTOLOH
pT
pTOLOHp
LPLH VV
VVVVVV
VVVVk
Ct
1=n
p
kk
Amirtharajah/Parkhurst, EEC 116 Fall 2011 20
Inverter Rise, Fall Times• Summary -- Exact method: separate into two regions
– t1• Vout drops from 0.9VDD to VDD-VT,n (NMOS in
saturation)• Vout rises from 0.1VDD to |VT,p| (PMOS in saturation)
– t2• Vout drops from VDD-VT,n to 0.1VDD (NMOS in linear
region)• Vout rises from |VT,p| to 0.9 VDD (PMOS in linear
region)– tf,r = t1 + t2
Amirtharajah/Parkhurst, EEC 116 Fall 2011 21
CMOS Inverter Delay• Review of approximate
method
– Assume a constant average current for the transition
– Iavg = average of drain current at beginning and end of transition
( )
( )SSDDavg
loadPLH
DDDDavg
loadPHL
VVICt
VVICt
−=
−=
21
21
V1=Vdd
V2=½Vdd
t1 t2
I1
I2
Iavg = ½(I1+I2)
Amirtharajah/Parkhurst, EEC 116 Fall 2011 22
CMOS Inverter Delay: 2nd Approximation• Another approximate
method:– Again assume constant Iavg
– Iavg = current I1 at start of transition
– Why is this a good approximation (esp. for deep submicron)?
( )
( )2
2
TPDDp
DDloadPLH
TnDDn
DDloadPHL
VVkVCt
VVkVCt
−=
−=
V1=Vdd
V2=½Vdd
t1 t2
I1
Iavg = I1
Amirtharajah/Parkhurst, EEC 116 Fall 2011 23
CMOS Inverter Delay: Finite Input Transitions• What if input has finite rise/fall time?
– Both transistors are on for some amount of time
– Capacitor charge/discharge current is reduced
22
2)()( ⎟
⎠⎞
⎜⎝⎛+= r
phlphltsteptactualt
22
2)()( ⎟⎟
⎠
⎞⎜⎜⎝
⎛+= f
plhplh
tsteptactualt
Empirical equations:
trise(ns)
t pHL(
ns)
Amirtharajah/Parkhurst, EEC 116 Fall 2011 24
How to Improve Delay?
• Minimize load capacitances
– Small interconnect capacitance
– Small Cg of next stage
• Raise supply voltage
– Increases current faster than increased swing ΔV
• Increase transistor gain factor
– Increase transistor drive current for charging/discharging output capacitance
• Use low threshold voltage devices
– More subthreshold leakage power dissipation
Amirtharajah/Parkhurst, EEC 116 Fall 2011 25
Inverter Power Consumption
• Static power consumption (ideal) = 0
– Actually DIBL (Drain-Induced Barrier Lowering), gate leakage, junction leakage are still present
• Dynamic power consumption
fVCVCT
P DDloadDDloadavg221
==
( ) ⎥⎦
⎤⎢⎣
⎡⎟⎠⎞
⎜⎝⎛−+⎟
⎠⎞
⎜⎝⎛−= ∫ ∫
2/
0 2/
1 T T
T
outloadoutDD
outloadoutavg dt
dtdVCVVdt
dtdVCV
TP
⎥⎥
⎦
⎤
⎢⎢
⎣
⎡⎟⎠⎞
⎜⎝⎛ −+⎟⎟
⎠
⎞⎜⎜⎝
⎛−=
T
ToutloadloadoutDD
T
outloadavg VCCVVVC
TP
2/
2
2/
0
2
21
21
( ) ( )∫=T
avg dttitvT
P0
1
Amirtharajah/Parkhurst, EEC 116 Fall 2011 26
Next Time: Combinational Logic and Layout
• Combinational MOS Logic
– DC Characteristics, Equivalent Inverter method
– AC Characteristics, Switch Model
• Combinational Logic Layout