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Lecture 6. CMOS Device (cont). ECE 407/507. Notice. Reading Assignment : chapter 1, chapter 3 (finish reading) Both hw1 and lab1 are on the website hw1 due in one week (next Thurs.) Lab1 due in two week (the Thurs. after next ). The Transistor as a Switch. The Transistor as a Switch. - PowerPoint PPT Presentation
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EE1411
© Digital Integrated Circuits2nd Devices
Lecture 6. CMOS Device (cont)Lecture 6. CMOS Device (cont)
ECE 407/507
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NoticeNotice
Reading Assignment : chapter 1, chapter 3 (finish reading)
Both hw1 and lab1 are on the website hw1 due in one week (next Thurs.) Lab1 due in two week (the Thurs. after
next )
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The Transistor as a SwitchThe Transistor as a Switch
VGS VT
RonS D
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
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The Transistor as a SwitchThe Transistor as a Switch
0.5 1 1.5 2 2.50
1
2
3
4
5
6
7x 10
5
VDD
(V)
Req
(O
hm)
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The Transistor as a SwitchThe Transistor as a Switch
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C GCB_1 C GCS C GCD
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The Sub-Micron MOS TransistorThe Sub-Micron MOS Transistor
Threshold Variations Subthreshold Conduction Parasitic Resistances
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Threshold VariationsThreshold Variations
VT
L
Long-channel threshold Low VDS threshold
Threshold as a function of the length (for low VDS)
Drain-induced barrier lowering (for low L)
VDS
VT
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Sub-Threshold ConductionSub-Threshold Conduction
0 0.5 1 1.5 2 2.510
-12
10-10
10-8
10-6
10-4
10-2
VGS (V)
I D (
A)
VT
Linear
Exponential
Quadratic
Typical values for S:60 .. 100 mV/decade
The Slope Factor
ox
DnkT
qV
D C
CneII
GS
1 ,~ 0
S is VGS for ID2/ID1 =10
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Sub-Threshold Sub-Threshold IIDD vs vs VVGSGS
VDS from 0 to 0.5V
kT
qV
nkT
qV
D
DSGS
eeII 10
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Sub-Threshold Sub-Threshold IIDD vs vs VVDSDS
DSkT
qV
nkT
qV
D VeeIIDSGS
110
VGS from 0 to 0.3V
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Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions
Strong Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS VDSAT
Weak Inversion (Sub-Threshold) VGS VT
Exponential in VGS with linear VDS dependence
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Parasitic ResistancesParasitic Resistances
W
LD
Drain
Draincontact
Polysilicon gate
DS
G
RS RD
VGS,eff
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Future PerspectivesFuture Perspectives
25 nm FINFET MOS transistor
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New Tech: Silicon On Insulator (SOI)New Tech: Silicon On Insulator (SOI)
Silicon wafers are highly perfect : critically important for achieving high device yield.
But a more radical change may be needed in the material structure, processing method, or device design in order to enhance the circuit performance.
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Why use SOIWhy use SOI
Extend the life of traditional silicon technology
Boost speed Reduce power consumption Solve some scaling difficulties
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Transistor crosssectionTransistor crosssection
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SOI material structure SOI material structure
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Benefits of SOI -performanceBenefits of SOI -performance
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Benefits of SOI -- powerBenefits of SOI -- power
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Benefits of SOI – timing Benefits of SOI – timing
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SiGe: Silicon Germanium SiGe: Silicon Germanium
Used to be inefficient in chip production Extremely high frequencies: 60Ghz Very little power usage 70% faster, 35% less power
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Why SiGeWhy SiGe
The layer of latticed silicon and germanium added to the chips silicon layer increases the distance between
silicon atoms
Less force between atoms, easy for electrons to pass by with less resistance
IBM suggests combining SiGe and SOIIBM suggests combining SiGe and SOI
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Thermal problem with SiGeThermal problem with SiGe
The diagram above shows the effect of localized self-heating in the emitters(30C for 40mv)