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Lecture 19
OUTLINE• Common‐gate stageg g• Source follower
Reading: Chapter 7.3‐7.4
EE105 Fall 2007 Lecture 19, Slide 1 Prof. Liu, UC Berkeley
Diode‐Connected MOSFETsDiode-connected NMOSFET Diode-connected PMOSFET
11
1o
mX r
gR = 2
2
1o
mY r
gR =
Small-signal analysis circuit Small-signal analysis circuit
N t th t th ll i l d l f PMOSFET i id ti l t
EE105 Fall 2007 Lecture 19, Slide 2 Prof. Liu, UC Berkeley
• Note that the small‐signal model of a PMOSFET is identical to that of an NMOSFET
Common‐Gate Amplifier Stage• An increase in Vin decreases VGS and hence decreases ID.
The voltage drop across RD decreases V t increasesThe voltage drop across RD decreases Vout increasesThe small‐signal voltage gain (Av) is positive.
Dmv RgA =
EE105 Fall 2007 Lecture 19, Slide 3 Prof. Liu, UC Berkeley
Operation in Saturation Region• For M1 to operate in saturation, Vout cannot fall below Vb‐VTH.
Trade‐off between headroom and voltage gainTrade off between headroom and voltage gain.
EE105 Fall 2007 Lecture 19, Slide 4 Prof. Liu, UC Berkeley
I/O Impedances of CG Stage (λ = 0)Small-signal analysis circuit for
determining output resistance, Rout
Small-signal analysis circuit fordetermining input resistance, Rin
Dout RR =in gR 1
=
EE105 Fall 2007 Lecture 19, Slide 5 Prof. Liu, UC Berkeley
mg
CG Stage with Source Resistance
mg1
Small-signal equivalent circuit seen at input
in
mS
mX v
gR
gv 1+
=
R1For λ = 0:
S
Dv
Rg
RA+
= 111
+⋅=⋅=
SmDm
in
X
X
out
in
out
RgRg
vv
vv
vv
EE105 Fall 2007 Lecture 19, Slide 6 Prof. Liu, UC Berkeley
mg
• The output impedance of a CG stage with source resistance is identical to that of CS stage with degeneration.g g
Small-signal analysis circuit fordetermining output resistance, Rout
( ) ( ) rRrgRRgrR ++=++= 11
EE105 Fall 2007 Lecture 19, Slide 7 Prof. Liu, UC Berkeley
( ) ( ) OSOmSSmOout rRrgRRgrR ++=++= 11
CG Stage with Biasing• R1 and R2 establish the gate bias voltage.
• R3 provides a path for the bias current of M1 to flow.R3 provides a path for the bias current of M1 to flow.
( )R /1||( )( ) Dm
Sm
m
in
out RgRgR
gRvv
⋅+
=/1||
/1||
3
3
EE105 Fall 2007 Lecture 19, Slide 8 Prof. Liu, UC Berkeley
CG Stage with Gate Resistance• For low signal frequencies, the gate conducts no current.
Gate resistance does not affect the gain or I/O impedancesGate resistance does not affect the gain or I/O impedances.
EE105 Fall 2007 Lecture 19, Slide 9 Prof. Liu, UC Berkeley
CG Stage ExampleSmall-signal equivalent
circuit seen at inputSmall-signal equivalent
circuit seen at output
( ) inSmm
in
S
mmX v
Rggv
R
ggv
21
21
11
11
11
++=
+=
12
1111
Om
SOmout rg
RrgR +⎟⎟⎠
⎞⎜⎜⎝
⎛≈
Smm
Rgg 21
+
DOSOmout RrRrgR ||||1111 ⎥⎦
⎤⎢⎣
⎡+⎟
⎠
⎞⎜⎜⎝
⎛≈( )
DmXoutv R
RgvvA 1
1 ++=⋅=
EE105 Fall 2007 Lecture 19, Slide 10 Prof. Liu, UC Berkeley
OSm
Omout g 2⎥⎦
⎢⎣ ⎠
⎜⎝( ) SmminX Rggvv 211 ++
Source Follower Stage
1||<LOout RrvA 1
||1||
<+
=≡LO
m
LO
in
outv
Rrg
vA
Small-signal analysis circuit fordetermining voltage gain, Av
mg
Equivalent circuitg g g , v Equivalent circuit
( )( )( )
Lomout Rrvgv = 1outin vvv += 1
EE105 Fall 2007 Lecture 19, Slide 11 Prof. Liu, UC Berkeley
( )( )Looutinm Rrvvg −=outin 1
Source Follower Example• In this example, M2 acts as a current source.
||
21
21
||1||
OO
OOv
rr
rrA+
=
EE105 Fall 2007 Lecture 19, Slide 12 Prof. Liu, UC Berkeley
211
|| OOmg
Rout of Source Follower• The output impedance of a source follower is relatively low,
whereas the input impedance is infinite (at low frequencies); p p ( q );thus, it is useful as a voltage buffer.
Small-signal analysis circuit fordetermining o tp t resistance Rdetermining output resistance, Rout
Lm
LOm
out Rg
Rrg
R ||1||||1≈=
EE105 Fall 2007 Lecture 19, Slide 13 Prof. Liu, UC Berkeley
Source Follower with Biasing• RG sets the gate voltage to VDD; RS sets the drain current.
(Solve the quadratic equation to obtain the value of I )(Solve the quadratic equation to obtain the value of ID.)
Assuming λ = 0:
( )2
21
THSDDDoxnD VRIVLWCI −−= µ
EE105 Fall 2007 Lecture 19, Slide 14 Prof. Liu, UC Berkeley
Supply‐Independent Biasing• If Rs is replaced by a current source, the drain current ID
becomes independent of the supply voltage VDDbecomes independent of the supply voltage VDD.
EE105 Fall 2007 Lecture 19, Slide 15 Prof. Liu, UC Berkeley
