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Lecture 13ANNOUNCEMENTS
• Midterm #1 (Thursday 10/11, 3:30PM‐5:00PM) location:Midterm #1 (Thursday 10/11, 3:30PM 5:00PM) location:• 106 Stanley Hall: Students with last names starting with A‐L• 306 Soda Hall: Students with last names starting with M‐Z
• EECS Dept policy re: academic dishonesty will be strictly followed!
OUTLINE
EECS Dept. policy re: academic dishonesty will be strictly followed!• HW#7 is posted online.
• Cascode Stage: final comments• Frequency Response
– General considerations– General considerations– High‐frequency BJT model– Miller’s Theorem– Frequency response of CE stage
EE105 Fall 2007 Lecture 13, Slide 1 Prof. Liu, UC Berkeley
q y p g
Reading: Chapter 11.1‐11.3
Cascoding Cascode?• Recall that the output impedance seen looking into the
collector of a BJT can be boosted by as much as a factor of β, by using a BJT for emitter degeneration.
||)]||(1[ rrrrrgR ++=( ) 11211
121121
||||)]||(1[
ooomout
ooomout
rrrrgRrrrrrgR
βπ
ππ
≤≈++=
• If an extra BJT is used in the cascode configuration, the maximum output impedance remains βro1.
1111max,
121121 ||)]||(1[
oomout
ooomout
rrrgRrrrrrgR
βββ
π
ππ
=≈++≤
EE105 Fall 2007 Lecture 13, Slide 2 Prof. Liu, UC Berkeley
Cascode Amplifier• Recall that voltage gain of a cascode amplifier is high,
because Rout is high.because Rout is high.
( )21211 πrrgrgA omomv −≈
• If the input is applied to the base of Q2 rather than the p pp 2base of Q1, however, the voltage gain is not as high.– The resulting circuit is a CE amplifier with emitter degeneration,
which has lower Gwhich has lower Gm.
( )212
2
1m
i
om rrg
gviG
+=≡
EE105 Fall 2007 Lecture 13, Slide 3 Prof. Liu, UC Berkeley
( )2121 oomin rrgv +
Review: Sinusoidal Analysis• Any voltage or current in a linear circuit with a sinusoidal source is a sinusoid of the same frequency (ω)source is a sinusoid of the same frequency (ω).– We only need to keep track of the amplitude and phase, when
determining the response of a linear circuit to a sinusoidal source.
• Any time‐varying signal can be expressed as a sum of sinusoids of various frequencies (and phases).
Applying the principle of superposition:– The current or voltage response in a linear circuit due to a time‐varying input signal can be calculated as the sum of the sinusoidal responses for each sinusoidal component of the
EE105 Fall 2007 Lecture 13, Slide 4 Prof. Liu, UC Berkeley
sinusoidal responses for each sinusoidal component of the input signal.
High Frequency “Roll‐Off” in Av
• Typically, an amplifier is designed to work over a limited range of frequencies.limited range of frequencies.– At “high” frequencies, the gain of an amplifier decreases.
EE105 Fall 2007 Lecture 13, Slide 5 Prof. Liu, UC Berkeley
Av Roll‐Off due to CL • A capacitive load (CL) causes the gain to decrease at high frequencieshigh frequencies.– The impedance of CL decreases at high frequencies, so that it shunts some of the output current to ground.
⎞⎜⎜⎛RA 1||
⎠⎜⎜⎝
−=L
Cmv CjRgA
ω||
EE105 Fall 2007 Lecture 13, Slide 6 Prof. Liu, UC Berkeley
Frequency Response of the CE Stage• At low frequency, the capacitor is effectively an open circuit and A vs ω is flat At high frequencies thecircuit, and Av vs. ω is flat. At high frequencies, the impedance of the capacitor decreases and hence the gain decreases. The “breakpoint” frequency is 1/(RCCL).C
1222 +=
ωLC
Cmv
CRRgA
LC
EE105 Fall 2007 Lecture 13, Slide 7 Prof. Liu, UC Berkeley
Amplifier Figure of Merit (FOM)• The gain‐bandwidth product is commonly used to benchmark amplifiers. p– We wish to maximize both the gain and the bandwidth.
• Power consumption is also an important attribute.– We wish to minimize the power consumption.
( )CmRg 1 ⎞⎜⎜⎛( )
CCC
LCCm
VICR
g
1nConsumptioPower
BandwidthGain ⎠⎜⎜⎝=
×
LCCT CVV1 =
EE105 Fall 2007 Lecture 13, Slide 8 Prof. Liu, UC Berkeley
Operation at low T, low VCC, and with small CL superior FOM
Bode Plot• The transfer function of a circuit can be written in the general formgeneral form
L⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛+
= 21
11)( zz
jj
AjHωω
ωω
ωA0 is the low-frequency gainωzj are “zero” frequencies
L⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟
⎟⎠
⎞⎜⎜⎝
⎛+
=
21
0
11)(
pp
jjAjH
ωω
ωω
ω ωzj are zero frequenciesωpj are “pole” frequencies
• Rules for generating a Bode magnitude vs. frequency plot:As ω passes each zero frequency the slope of |H(jω)| increases– As ω passes each zero frequency, the slope of |H(jω)| increasesby 20dB/dec.
– As ω passes each pole frequency, the slope of |H(jω)| decreases
EE105 Fall 2007 Lecture 13, Slide 9 Prof. Liu, UC Berkeley
by 20dB/dec.
Bode Plot Example• This circuit has only one pole at ωp1=1/(RCCL); the slope of |Av|decreases from 0 to ‐20dB/dec at ωp1. | v| / p1
1=ω
LCp CR1 =ω
• In general, if node j in the signal path has a small‐signal resistance of Rj to ground and a capacitance Cj to ground then it contributes a pole at frequency (R C )‐1
EE105 Fall 2007 Lecture 13, Slide 10 Prof. Liu, UC Berkeley
ground, then it contributes a pole at frequency (RjCj) 1
Pole Identification Example
1 1
inSp CR
11 =ω
LCp CR
12 =ω
EE105 Fall 2007 Lecture 13, Slide 11 Prof. Liu, UC Berkeley
High‐Frequency BJT Model• The BJT inherently has junction capacitances which affect its performance at high frequencies.affect its performance at high frequencies.Collector junction: depletion capacitance, CµEmitter junction: depletion capacitance, Cje, and also j
diffusion capacitance, Cb.
b CCC +≡
EE105 Fall 2007 Lecture 13, Slide 12 Prof. Liu, UC Berkeley
jeb CCC +≡π
BJT High‐Frequency Model (cont’d)• In an integrated circuit, the BJTs are fabricated in the surface region of a Si wafer substrate; anothersurface region of a Si wafer substrate; another junction exists between the collector and substrate, resulting in substrate junction capacitance, CCS.g j p CS
BJT cross-section BJT small-signal model
EE105 Fall 2007 Lecture 13, Slide 13 Prof. Liu, UC Berkeley
Example: BJT Capacitances• The various junction capacitances within each BJT are explicitly shown in the circuit diagram on the right.p y g g
EE105 Fall 2007 Lecture 13, Slide 14 Prof. Liu, UC Berkeley
Transit Frequency, fT• The “transit” or “cut‐off” frequency, fT, is a measure of the intrinsic speed of a transistor and is defined asof the intrinsic speed of a transistor, and is defined as the frequency where the current gain falls to 1.
C t l t t fConceptual set-up to measure fT
inmout VgI =inT
minmin
out
CjgZg
II
=⎟⎟⎠
⎞⎜⎜⎝
⎛==
ω11
in
inin Z
VI =
in
mT
inTin
Cg
j
=⇒
⎠⎝
ω
πCgf m
T =2
EE105 Fall 2007 Lecture 13, Slide 15 Prof. Liu, UC Berkeley
πC
Dealing with a Floating Capacitance• Recall that a pole is computed by finding the resistance and capacitance between a node and GROUNDand capacitance between a node and GROUND.
• It is not straightforward to compute the pole due to Cµ1in the circuit below, because neither of its terminals isin the circuit below, because neither of its terminals is grounded.
EE105 Fall 2007 Lecture 13, Slide 16 Prof. Liu, UC Berkeley
Miller’s Theorem • If Av is the voltage gain from node 1 to 2, then a floating impedance ZF can be converted to twofloating impedance ZF can be converted to two grounded impedances Z1 and Z2:
ZVZZVVV⇒
− 11121
vFF
F AZ
VVZZ
ZZ −=
−=⇒=
1
21
11
1
121
FF ZVZZVVV 122
221 =−=⇒−=−
EE105 Fall 2007 Lecture 13, Slide 17 Prof. Liu, UC Berkeleyv
FFF A
ZVV
ZZZZ 11
21
22 −−
⇒
Miller Multiplication• Applying Miller’s theorem, we can convert a floating capacitance between the input and output nodes of p p pan amplifier into two grounded capacitances.
• The capacitance at the input node is larger than the l floriginal floating capacitance.
vAA −≡0 FF CjZZ⎞⎛
===21
1
1
1ω
FvCAjAA ⎟⎠⎞⎜
⎝⎛ ++−
00
2111111 ω
FF CjZZ 11ω
EE105 Fall 2007 Lecture 13, Slide 18 Prof. Liu, UC Berkeley
( ) F
F
v
F
CAjACj
AZZ
001 1
111 +
=+
=−
=ω
ω
Application of Miller’s Theorem
( ) FCmSinp CRgR +=
11
,ω
outp
CR⎞
⎜⎜⎛+
=11
1,ω
EE105 Fall 2007 Lecture 13, Slide 19 Prof. Liu, UC Berkeley
FCm
C CRg
R⎠
⎜⎜⎝+1
Small‐Signal Model for CE Stage
EE105 Fall 2007 Lecture 13, Slide 20 Prof. Liu, UC Berkeley
… Applying Miller’s Theorem
( )( )ωCRgCRinp ++
=11
, ( )( )µCRgCR CminThev ++ 1
⎞⎛ ⎞⎛=ω outp
1,
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛++ µC
RgCR
CmoutC
p11
,
EE105 Fall 2007 Lecture 13, Slide 21 Prof. Liu, UC Berkeley
Note that ωp,out > ωp,in
Direct Analysis of CE Stage
• Direct analysis yields slightly different pole locations and an extra zero:and an extra zero:
mg=ω
XYz C=
1ω
ω
( ) ( )( ) ( )outXYCinThevThevXYCm
outXYCinThevThevXYCmp
CCRCRRCRgCCRCRRCRg
++++++++
=
111ω
( ) ( )( )outinXYoutXYinCThev
outXYCinThevThevXYCmp CCCCCCRR
CCCCg++
=2ω
EE105 Fall 2007 Lecture 13, Slide 22 Prof. Liu, UC Berkeley
Input Impedance of CE Stage
rZ ||1( )[ ] π
µπωr
CRgCjZ
Cmin ||
1++≈
EE105 Fall 2007 Lecture 13, Slide 23 Prof. Liu, UC Berkeley