Integrated Radiation-tolerant Imaging Systemmicroelectronics.esa.int/presentation/IRIS.pdf · GSTP/ASCMSA/Integrated Radiation tolerant Imaging System ... GSTP/ASCMSA/Integrated Radiation

GSTP/ASCMSA/Integrated Radiation tolerant Imaging System – Final Presentation – ESTEC, 7 March 2001 1

GSTP – ASCMSAAnalog Silicon Compiler for Mixed Signal ASICs

Group 4 – Development of Microcamera

Integrated Radiation-tolerant Imaging System

Werner OgiersFillFactory NV

Schalienhoevedreef 20BB-2800 Mechelen

www.FillFactory.com


Contractors

• 1997 – 2000• Originally IMEC Image Sensor Group• Since 12/1999 partly by FillFactory

– IMEC spin-off for CMOS imagers– transfer of all people/patents to new company– based in Mechelen, Belgium– activities

• custom and off-the-shelf CMOS camera chips• studio digital photography• high-speed imaging• industrial vision• aerospace


Overview

• Objective: one-chip camera

• Challenges, choices• Specifications, architecture

• Prototype• Evaluation

• Final implementation• Evaluation

• Conclusions and future plans


Objective, SOW

… to design, develop, fabricate and test a novel microcamera chip, to be used as a monitoring camera for space applications with as few components as possible.

… based on CMOS technology … allows for easy co-integration of … control logic … ADC … interfaces, and on

the long term image compression circuitry

�IRISIntegrated Radiation tolerant Imaging System


• Target: low-end– Visual SC monitoring

– Landers and rovers this contract– Robotics

• Feasible:– Optical navigation TRP:ASCoSS(12227/96/NL/SB)

Space Applications for CMOS APS


Overview

• Statement of work: one-chip camera






IRIS Challenges

• Integrated: CMOS APS + logic– CMOS imagers immature– no mixed-signal experience

• Radiation tolerant: CMOS reputation– zero knowledge– trust technology

• Imaging System– choice of two CMOS APS styles

• direct readout• integrating


Technology? Direct readout

• Direct readout CMOS Active Pixel Sensor• IMEC’s FUGA15 used on Teamsat• Photo-current though resistor => V(t)• Non-linear R => wide dynamic range• No blooming• Static offsets => correct with LUT• No single-chip solution

raw image

LUT processed image

V=R.I(t)

I(t)

R


Technology? Integrating

• Integrating CMOS APS• ~ CCD, ~film• Exposure: photocurrent on C• Readout: C to V• (Correlated) Double Sampling• Cosmetically ‘perfect’• Little experience

– IBIS1 sensor (1997)

raw image

V=∑I(t)

I(t)


• Integrating CMOS APS– IBIS1 architecture– Larger area: 640 x 480 14µm pixels– ADC– Logic

• Radiation hardening?– None– Applying known rules would explode chip area

• Chip integration?– Sensor core unknown– First two-chip prototype

=> Conservative approach: 2 stages

Choices


Phase 1 flow

Two-chip solution: IRIS1 imager with control FPGA

Flight demonstration: VMC/IRIS1 on XMM, Cluster-II, …

System and chip specification


Phase 2 flow

IRIS2 single-chip camera

IRIS2 electro-optical and radiation characterisation

Demonstration microcamera


Overview







Camera Specifications

NoYesOn-chip linedrivers

NoYesPower-save

Slightly less (ASCoSS: Mv=5)Mv=5 starsSensitivity

CCSDS packets

Various parallel and serial IFs

SCcompatible

Interfaces

Windowing, subsampling, …Windowing,subsampling,…

Readout

???TolerantRadiation

8 bit> 8 bitADC

9Hz25Hz (video)Frame rate

640x480> 512x512Resolution

IRIS proposal (technical limits in 1997)Desired


IRIS Functionality

3 analogue input channelsRemote signal sensing

8 programmable output linesRemote control

Manual (TC needed); limited automatic control loopExposure control

Start up and take stream of imagesAutonomous operation

YesCommanded operation

RS-485-style ..12.5Mb/sSync serial ..12.5Mb/sSync parallel ..3.125MB/s

Data interfaces

RS-485-style ..3.125Mb/sSync serialSync parallel (bus)

Command interfaces

ESA-style CCSDSTC/TM protocol

Full frame ~9HzWindowed pro rata e.g. 320 x 240 x 36Hz

Frame rate

Full frame, One window of interest, Y-subsampled 1,2,4,8,X-subsampled 1,2,4,8, X-binned 1,2,4,8, Y-interleaved 1,2,4,8

Readout


Not Included/Missing

• Image memory– over 300 kB needed

• Support for external memory– pin limited

• Synchronous ‘snap shot’ shutter– requires larger pixel– result: ‘rolling blade’ electronic shutter

=> Imaging rate = output data rate


IRIS Chip Architecture

640 x 480 pixel array anddouble sampling column amplifiers

Control logic:•Image sequencer•I/O interfaces•CCSDS packetiser

Analogue path:•Multiplexer•Amplifier•ADC


IRIS Pixel Architecture

• Patented ‘well pixel’ uses bulk of silicon to trap photo-electrons– Near-100% fill-factor: only metal-covered area is blind– Increased sensitivity

– Increased NIR sensitivity: use filter– Risk for inter-pixel crosstalk

– Risk for local blooming-like effects


Typical Application

Packet TelecommandDecoder

IRIS Camera-on-a-Chip

Data Acquisition System withMemory

Thermistor

Lighting

Pan and Tilt Motor

Sync Serial IF

Sync Parallel IF

Remote Control Bus

Telesense Inputs


Overview







IRIS1 Implementation

• Alcatel Microelectronics (Mietec) 0.7µ A/D CMOSprocess

• Custom focal plane array• Existing ADC block


IRIS1 + FPGA Architecture

IRIS1 analogue ASIC•Black & white•RGB colour (IMEC funded)

FPGA


Overview







IRIS1 Characterisation Results

FewBlemishes anddefects

-Operatingtemperature

-Latch up

-Radiation

-ADC missing codes

Low sharpness0.24/0.3MTF

80mAPower

0.62%Uniformity

-Dark signal at 65°C

31mV/sDark signal

~40dB post ADC67dBSNR

remarksIRIS1 (analogue)


IRIS1 Flights (outside contract)

• Visual Monitoring Camera– Unsollicited IMEC/OIP proposal

• System– IRIS1 or FUGA15 sensors– Colour or B&W– Actel 1280 FPGA– TTC-B-01 or RS-422 interfaces– Storage for 1 image

• Flights– XMM– Cluster II– Proba– Mars Express


IRIS1 Flights (XMM)

Interactive exposure settingIRIS1

Direct readout sensor,No exposure setting


IRIS1 Flights (Cluster II)

Pre-calculated exposure settingbased on solar simulator experiments


IRIS1 Evaluation

• Performance matched expectations, except

• Low MTF (picture sharpness)– expected

– not to be avoided• Unless thinner wafer material• Inter-pixel shielding

– Larger pixels– Less sensitivity

• Limited dynamic range <-> space scenes

– exact pre-calculation of exposure time


Overview







IRIS2 Implementation

• Alcatel Microelectronics 0.7µ AD CMOS

• Custom– FPA (IRIS1 with better output amp)

– ADC (same)• Standard cells

– logic core (subset of library for RT)– I/O pads


IRIS2 Chip Overview

640 x 480 pixel array

8 bit flash ADC

20 kgates core logic

double sampling column amplifiers

digital I/O

analogue I/O


IRIS2 Board Specifics

• 84 pin ceramic J-lead package• Seven 5V power supplies

– can be combined without ill effect

• Requires– 16 configuration straps– 12 resistors– 13 capacitors– 12.0/12.5MHz clock generator– interface drivers/receivers


Overview







IRIS1/2 Characterisation Results

FewFewBlemishes anddefects

0 .. 65°C-Operatingtemperature

yes-Latch up

~10 krad-Radiation

~11-ADC missing codes

-0.24/0.3MTF

74mA80mAPower

0.52%0.62%Uniformity

2780mV/s-Dark signal at 65°C

20mV/s31mV/sDark signal

68dB67dBSNR

IRIS2 (mixed signal)IRIS1 (analogue)


Environmental effects

• Temperature

– increased dark signal• Radiation

– increased dark signal�Limits of operation:

� 10 krad� 65 °C

10krad, 2 sec exposure

pre-rad


IRIS2 Microcamera

• IMEC made demo microcamera

– Not flight standard– Demonstrates most of IRIS2 functionality

– Configuration switches inside– Can be extended

• Bus-like backbone• Tube-like housing

• 8 cameras + 1 ‘station’


IRIS2 Microcamera Images

Raw imager output



Gamma,Sharpened



IRIS2 raw data, f/4, 700µs exposure

ISO100 film, f/4, 1000µs exposure



IRIS2 FF APS 2001 IRIS2 FILM



IRIS2



ISO 100 FILM


Overview







Project Evaluation

• Project defined in 1997• CMOS immature technology

– Low image quality– Radiation issues

=> IRIS2 outdated device in 2001

• FillFactory got experienced in noise-free co-integration ofimage sensors with logic

• In-flight experience with IRIS1 drives new developments• Requests from industry for monitoring chips or cameras=> Next generation will be better / already is better


Continuation

ASCMSA/IRIS (and ASCoSS) follow-up in STARS3framework, Work Order 3

• WP1300 Rad-hard imager development (IMEC,FF)• > 1 MRad attained

• WP2000 Image Compression Camera – IRIS3• Rad-hard IRIS3 1024x768 chip with integrated control for SDRAM and link

to data compression chip

• Optical InterSatellite Link (beam/star tracker)• Rad-hard sensor + 10b ADC for beam/star tracking• 512x512 silicon available now• 1024x1024 soon


Conclusions

• Successfully developed single-chip CMOS camera forspace use

• IRIS1 demonstrated in space• Good electro-optical performance

• Needs better– MTF/sharpness

– Dynamic range– Radiation behaviour

• Solutions in on-going follow-up work

Documents

Integrated Radiation-tolerant Imaging Systemmicroelectronics.esa.int/presentation/IRIS.pdf · GSTP/ASCMSA/Integrated Radiation tolerant Imaging System ... GSTP/ASCMSA/Integrated Radiation