Reconfigurable Devices for Error- DetectiodCorrection Applications

T. Donneuy, K. Jackson and J. Moreno* School of Electrical, Electronic & Communications Engineering

University of Plymouth Plymouth, Devon.

*Escuela Universitaria Politecnica Universidad De Cordoba, Cordoba, Spain.

Abstract Most digital, recording systems employ error-correction codedtechniques to correct spurious errors. A fixed error-correction strategy is normally employed the power of which is based on the worst-case error characteristics of the system The redundancy inherent in the codewords must be stored on the recording medium and this displaces recording capacity which could, in an error-free system, be occupied by information. If the error-correction strategy were varied according to the prevailing error conditions a reduced redundancy overhead would be incurred thus affording an increase in recording capacity. The difference in the electronic circuits for error-correction schemes of varying power is largely one of extent and thus, such an adaptive error- correction scheme is possible through the use of reconfigurable electronics. There are a number of techniques which can be applied but these are a trade off between effective device utilisation and the fist reconfiguration time required. Use of the Xilinx X4000E series in this application is limited because it cannot be selectively reconiigured. The more advanced 6000 series does offer this feature but the device is more difficult to use and development tools do not seem to be well developed.

Adaptive Error Correction In a fixed error-correction system the error code(s) employed are chosen to cope with worst-case error conditions. Consequently, the error-correction "overhead" is carried whether or not those worst-case conditions are encountered and the 111 power of the code never fully utilised.

With adaptive error-correction the power of the code employed is tailored to the prevailing error conditions [l]. If errors are light, a code with modest power, and therefore lower redundancy, is used. As errors increase, the power of the code is increased. If error conditions are less than continuous worst case the overall redundancy of an adaptive system will be less than a fixed system thus giving a saving.

Typical Circuitry Typical encoding/decoding circuitry for error detectiodcorrection applications is made up from logic elements and s M registers which combine to perform the functions of finite-field division, addition and multiplication. An example of a tirite-field multiplifier is shown in figure 1.

71 1

P i

Data in c

Figure 1. Example of me-field multiplier (1 + a).

FPGA b Data out

FPGA Reconfiguration The task of adaptive error correction requires fkst processing logic and rapid reconiiguration of the correction algorithm. A microprocessor does not provide sufEcient speed to implement the algorithm directly. However, an FPGA can be used to implement the algorithm with adaptive control undertalcen by a microprocessor, figure 2.

Figure 2. Adaptive control with microprocessor and FPGA

As conditions change the FPGA must be re-contigured dynamically. Ideally, low cost devices, such as the xilinx 4000 series would be chosen but there are recontigumtion issues concerning circuit size, the chosen algorithm and time to reconfigure. One option is to switch between pre-configured algorithms within the FPGA, figure 3.

Data in

I Processor control

7 I

Algorithm 1

- Algorithm2 0

b

lr Algorithm 3

Data out

I P G A 1 Figure 3. Switching between pre-configured options within the FPGA

This is quick but inefficient in terms of device utilisation. A more efficient technique is to totally reconfigure the whole device each time the algorithm changes. This would suit the 4000 series which does not permit partial reconfiguration. The X4000E series can accommodate a bit rate of up to 10 Mbits per second of reconfiguration data in serial or 8-bit parallel mode. For a typical mid-range device, such as the 4006, there are around 12OKbits of data which, if loaded in parallel mode takes around 1.5 ms. However, if loaded fiom a processor this speed may not be achievable.

Selectively reconfigurable devices, such as the Xilinx 6000 series offer a solution. Some work has been done using a Plessey ERA selectively programmable device [2] but cell-utilisation was poor and the device is no longer produced. The Xilinx 6000 could provide a promising solution but these are more diflicult to use and development tools do not seem to be well developed.

Conclusions Two desireable features of an FPGA for this application are high speed of reconfiguration and selective-reconfiguration capability. Although, which of these features is necessary would depend on the chosen algorithm. The Xilinx X4000E devices are straightforward to apply but limit the choice of algorithms since they are not selectively reconfigurable. The 6000 series offers higher performance in this respect but is diEcult to apply.

Appendix. Basic Theory of Error Correction Message information is encoded such that a code-generating polynomial, G(x), is a fhctor of each codeword. Decoding is accomplished by detecting the hctor, G(x), in each codeword.

The encoding process is as follows. Let information to be encoded be represented by the polynomial M(x).

Dividing M(x) by G(x): M(x) = Q(x) 8 R(xl G(x) G(x)

From this, M(x) @ R(x) = Q(x) G(x) mod. 2.

Where Q(x) is the quotient and R(x) is the remainder. M(x)G R(x) is the codeword. The remainder is the parity component of the codeword which endows error detectiodcorrection capability.

In practice, M(x) is effectively shifted by the number of symbols in R(x), n-k, to place the codeword in systematic form. Hence,

Systematic codeword = X'"" M(x) 8 R(x).

The encoding process includes multiplication (X'""' M(x)) and division (M(x)/G(x)). Both are serial processes and the electronic circuitry employed is made up of a combination of shift registers and modulo 2 adders.

Reed Solomon (RS) code The Reed Solomon code [3] is used extensively in data recording and digital communications systems. Codewords are made up from symbols each of a fixed number of bits. Codewords comprise data symbols and parity symbols. For a single error-correcting RS code any combination of bit errors within a single symbol is correctable. Decoding, therefore, involves identifling the symbol within the codeword which is in error plus each erroneous bit within the symbol.

The basic theory and hardware requirements, outlined above, are applicable to RS codes. However, since Galois fields are employed to represent codeword symbols, and also in the encoding/decoding process, circuitry to execute Galois field arithmetic (addition and multiplication) is also required. These arithmetic operations can be implemented using combinatiod logic.

Interleaving This process increases the error-correcting capability of a code. Rather than processing (recording or traasmittjng) codewords sequentially, interleaving involves processing bits (symbols) from each of n codewords sequentially. If an error burst of m consecutive bits are now corrupted during processing, only one bit (symbol) in n codewords is affected rather than m bits in one codeword for the non-interleaved case. This means that a single error-correcting code can be utilised on a channel subject to burst-type errors.

References [ 11 Donnelly, T et al, "The Use of a FPGA in adaptive Error Correction for a Digital recording System", presented at IEE Colloquium: Field Programmable Gate-Array Technology and Applications, London, Feb., 1993.

[2] Troup, T.P., Donnelly. T., Mapps, D.J. "Adaptive Data Interleaving Using a Microprocessor Controlled Reconfigurable Gate Array", Microprocessing and Microprogramming, 36, pp43-48, North Holland, 1992/93.

31 Reed, I. S., Solomon, G., "Polynomial Codes over Certain Finite Fields". J. Soc. Ind. Appl.Math., 8, pp 300-304. 1960.

c8 1999 The Instiition of Electrical Engineers. Printed and published by the IEE. Savoy Place. London WCSR OSL UK.

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