HVDC models in EMTP-RV

Sébastien Dennetière, EDF R&D, April 30th 2009

EMTP-RV user group meeting, Dubrovnik

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière2

Presentation layout

Why do we develop HVDC models ?

Description of a detailed HVDC model in EMTP-RV

Simulation results

Description of an average HVDC-VSC model in EMTP-RV

Simulation results

Next developments

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière3

Why do we develop HVDC models ?

Growing interest in HVDC links in transmission system

Avoid overhead lines construction

Flexibility

HVDC links models are required :

Determination of the best HVDC solution in a specific case

Training of power system engineers

4 Models :

Detailed models for transient studies: generic & specific

Average models for system studies : generic & specific

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière4

Detailed HVDC model

Main characteristics :

Generic standard HVDC (Bipolar 12 pulses)

Rated power : 1200 MVA

DC voltage : +/- 500 kV

DC cable 1400 mm², 70 km

AC Filters : 11th, 15th, 23rd/25th ; DC Filters : 6th & 12th

Reactive power compensation : filters + capacitor bank

Smoothing reactor : 370 mH

AC Short Circuit Power : 6000 MVA

Control system :

Current controller on rectifier side

Gamma controller or current controller on rectifier side

Developed by : University of Ontario Institute of Technology ,Ecole Polytechnique de Montreal and EDF R&D

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière5

Detailed HVDC model

AC network :

SCP = 6000 MVA

+

?v400kVRMSLL /_50

+

85mH

L2

+

1.5

R1

AC filters:

Each filter and capacitor bank generate ¼ of reactive power consumed by converters

Filters parameters are calculated from analytical expressions included into scripts

Capacitor bankharmonic 11th harmonic 13th HP filter

+

#

R_

13

#,#

L_

13

#,#

C_

13

#

+

#C_24p#

+

#

R_

24

p# +

#L

_2

4p

#

ligne

+

#C_bank#

+

#

R_

11

#,#

L_

11

#,#

C_

11

#

PQ

PQ

_ca

pa

_b

an

k

PQ

PQ

_1

1

PQ

PQ

_1

3

PQ

PQ

_H

P

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière6

Detailed HVDC model

Rectifier

3-phase+

-gates

6-pulse bridge

aux

B6P_1

3-phase+

-gates

6-pulse bridge

aux

B6P_3

3-phase+

-gates

6-pulse bridge

aux

B6P_4

3-phase+

-gates

6-pulse bridge

aux

B6P_5

1 2

YY9

368/205.45

1 2

YY1

368/205.45

1 2

368/205.45

YgD_2

1 2

368/205.45

YgD_1

firing_rec_delta

firing_rec_delta

firing_rec_star

firing_rec_star

gamma_min_star_bd

gamma_min_delta_bd

gamma_min_delta_minus_bd

gamma_min_star_minus_bd

ratio_rec_D

ratio_rec_D

ratio_rec_Y

ratio_rec_Y

Converters transformers :

Sn = 300 MVA / transformer

Tap changer

Xlf = 12.5%

Converters :

12 pulses

RC snubbers

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière7

Detailed HVDC model

DC Cables :

Paper insulated +/- 500 kV, 1400 mm²

CP model

DC filters : RLC branches ( 6th et 12th )

Smoothing reactance : 370 mH

DC filter

600 Hz

+

0.139,370mH

RL3

+

0.139,370mH

RL4

DC filter

300 Hz

500 kv 1400 mm² Cu

cable_plus

DC filter

600 Hz

DC filter

300 Hz

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière8

Detailed HVDC model

Rectifier / inverter control system

3PH AC Line voltages at Rectifier

Star/Deltatransformation

Pulse generators

Synchronising System

0.0002

1

2

3

4

5

6

f(u)

1

2

3

4

5

6

1

2

3

4

5

6

1

2

3

4

5

6

f(u)1

2

Fm8

f(u)1

2

Fm9

f(u)1

2

Fm10

v_pri_c

v_pri_av_pri_b

delta_freq

V_sync_aV_sync_bV_sync_c

V.K.SoodDQO_PLL_50Hz

DEV6

6-pulse bridgesingle firing of

a

b

c

delay

width

blocking

g1

g2

g3

g4

g5

g6

VKSood

DEV12

6-pulse bridgesingle firing of

a

b

c

delay

width

blocking

g1

g2

g3

g4

g5

g6

VKSood

DEV7

5.3e-6

5.3e-6

5.3e-6

scope

v_rec_a

scope

v_rec_b

scope

v_rec_c

v_pri_c

v_pri_av_pri_b

delta_freq

V_sync_aV_sync_bV_sync_c

V.K.SoodDQO_PLL_50Hz

DEV9

f(u)

1

2

3

Fm11

f(u)

1

2

3

Fm12

f(u)

1

2

3

Fm13

dpspdnsnidcio

out

iref

Rectifier_inverter_control

v1v2

ratio_Dratio_Y

tap_changer_rec

c

C9

205.45

cC10

365

v_pri_c

v_pri_av_pri_b

delta_freq

V_sync_aV_sync_bV_sync_c

V.K.SoodDQO_PLL_50Hz

DEV10

firing_rec_star

firing_rec_delta

v_pri_rec_a

v_pri_rec_b

v_pri_rec_c

gamma_min_delta_bd

gamma_min_star_bd

gamma_min_delta_minus_bd

gamma_min_star_minus_bd

id_rec

iref1iref2

ratio_rec_D

ratio_rec_Y

Regulation

Synchronization

Transformer tap changer

Pulse generation

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière9

Detailed HVDC model

Rectifier control system

from page 1

Alpha rectifier limits:alpha_min=5 degs =0.0278alpha_max=145 degs=0.81111

Step change in Iorderamplitude -0.1 puwidth 200 mstime shift 501 ms

Ramp Initialisationamplitude 1puwidth 150 mstime shift 50 ms

CurrentScaling

Step Initialisationamplitude 1puwidth 4000mstime shift 200 ms

alpha_delay in secondsdivide by 120 elec. degs

Kp=1.65Ki=2.75

Current order to be sent to inverter (page 3) via telecoms

step

sg3

ramp

sg9

step

sg10

1

Div1

1000f(s)

1

120+-

+

++

+

sum12

SUM1

2

lim7

1

0.0278

0.81111

180

Gain15

++

+ !h

sum13

0.7

Gain16

10

Gain17rc rv

0.8111

!h

0.0278

Int4

lim8

1

0.2

1.2

iref

scope

Iref

scope

err_idrec

idc

step_change_Io

deg_pu_delay_lim

iref

iref

deg_pu_delay

PI current

controller

Initialization

Step change in

Iorder

beta_delay in secondsdivide by 120 electrical degsinv gamma

inv current

simulates telecoms delay for margin setting

Gamma ref1 V = 180 degs0.1 = 18 degs

current scaling

Step Io test at recamplitude 0.1 puwidth 270 mstime shift 470 ms

margin 0.1 pu

Users may select at the inverter either1. Inverter Gamma control, or2. Inverter Current control. This is normally biased off with the current margin setting

Alpha inverter limits:alpha-min-inv =110 degs = 0.611 pualpha-max-inv =170 degs = 0.944 pu

Kp=4.0Ki=12.0

Kp=0.75Ki=35.0

Step Gamma testamplitude 0.05width 300 mstime shift 1400 ms

scope

alpha_inv_degsc

C12

0.10

step

sg4

scope

gamma_ref

180

Gain1

1

Div2

120

scope

gamma_min

+-

+ !hsum3

f(s)!h

MIN

1

2

3

4

Fm5

!h

1

Div3

1000

f(s)!h

++

- !h

sum1

++

-

sum6

step

sg6

scope

Io_inv++

-

sum8

c

C9

0.1

++

+ !h

sum4

scope

inv_gamma_controller

scope

inv_current_controller++

+ !h

sum2

1.8

Gain3

14

Gain4 0.925

0.711

1

lim1

MIN1

2

MIN_SELECT

!h

++

+ !h

sum5

0.2

Gain5

10

Gain6 0.944

0.711

1

lim4

rc rv

0.95

!h

0.611

Int3

rc rv

0.944

!h

0.711

Int1

0.95

0.1

1

lim3

0.2

0.05

1

lim6

dp

sp

dn

sn

idc

io

gamma_step

idc

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière10

Detailed HVDC model

Inverter control system

PI current

controller

Step change in

Gamma order

PI Gamma

controller

Detailed HVDC model

Rectifier

Rectifier AC Filters

Rectifier AC system

Inverter ACsystem

+ Pole

- Pole

400 kV AC system400 kV AC system

Inverter AC Filters

scope id_rec

v(t)

v(t)p3

scope V_pri_rec_a

scope

V_pri_inv_a

v(t) i(t)p1

scopevd_rec

3-phase+

-gates

6-pulse bridge

aux

B6P_1

3-phase

+

-

gates

6-pulse bridge

aux

B6P_2

3-phase+

-gates

6-pulse bridge

aux

B6P_3

3-phase+

-gates

6-pulse bridge

aux

B6P_4

3-phase+

-gates

6-pulse bridge

aux

B6P_5

3-phase

+

-

gates

6-pulse bridge

aux

B6P_6

3-phase

+

-

gates

6-pulse bridge

aux

B6P_7

3-phase

+

-

gates

6-pulse bridge

aux

B6P_8

+

R19

10M

+

R11

10M

DC filter

600 Hz

+

RL1

0.139,370mH

+

RL2

0.139,370mH

+

RL3

0.139,370mH

+

RL4

0.139,370mH

DC filter

600 Hz

DC filter

300 Hz

DC filter

300 Hz

12

410/205.45

YY4

12

410/205.45

YY2

1 2

368/205.45

YY9

1 2

368/205.45

YY1

1 2

YgD_2

368/205.45

1 2

YgD_1

368/205.45

12

YgD_4

420/205.45

12

YgD_3

420/205.45

f(s)

scope vd_rec_filtered

PQ

PQ_AC_rec

PQ

PQ_filter_rec

PQ

PQ_pole1_rec

PQ

PQ_AC_inv

PQ

PQ_filter_inv

PQ

PQ_pole2_rec

PQ

PQ_pole1_inv

PQ

PQ_pole2_inv

500 kv 1400 mm² Cu

cable_plus

500 kv 1400 mm² Cu

cable_minus

DC filter

600 Hz

DC filter

300 Hz

DC filter

600 Hz

DC filter

300 Hz

Filters sizing

AC filtersharmonics11, 13, 24+

and

Capacitor bank

filters_rec

AC filtersharmonics11, 13, 24+

and

Capacitor bank

filters_inv

Filters sizing

VM+vd_inv

?v

+

400kVRMSLL /_50?v

+L2

85mH

+R1

1.5 +L1

85mH

+ R2

1.5

+400kVRMSLL /_0

?v

firing_rec_delta

firing_rec_delta

firing_rec_star

firing_rec_star

firing_inv_delta

firing_inv_delta

firing_inv_star

firing_inv_star

vd_rec id_rec

gamma_min_star

v_pri_rec_c

v_pri_rec_a

v_pri_rec_b

v_pri_inv_c

v_pri_inv_a

v_pri_inv_b

gamma_min_star_minus

gamma_min_delta

gamma_min_delta_minus

gamma_min_star_bd

gamma_min_delta_bd

gamma_min_delta_minus_bd

gamma_min_star_minus_bd

ratio_rec_D

ratio_rec_D

ratio_rec_Y

ratio_rec_Y

ratio_inv_D

ratio_inv_D

ratio_inv_Y

ratio_inv_Y

vd_rec_filtered

EMTP-RV design

11 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière

Detailed HVDC model

Step change in Iorder

time (s)

y

PLOT

time (s)

y

PLOT

Step change in Gamma order

12 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière

Simulation results

Simulation options : Δt = 25µs, tmax = 2s, CPU time = 30s

time (s)

y

PLOT

time (s)

y

PLOT

Detailed HVDC modelVoltage sag

AC voltage rectifier side

time (s)

y

PLOTAC voltage inverter side

time (s)

y

PLOT

DC Current DC Voltage

13 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière14

Detailed HVDC model, next developments

Available on demand

Implementation of the Voltage Dependent Current Limit Unit :

Static characteristic adapts Iref as a function of DC voltage

Dynamic characteristic adapts Iref as a function of DC voltage according to the fast down time and slow up time

Modeling of protection systems (overvoltage, overcurrent, commutation failures)

Implementation of start up algorithm

Integration of control systems designed by manufacturers (DLL connection) to obtain specific HVDC models

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière15

Average HVDC VSC model

Main Characteristics :

Rated power : 1200 MVA

DC voltage : +/- 320 kV

DC cable 2500 mm² XLPE insulation, 70 km

Converters transformers

AC & DC filters

Capacitor bank : 20 µF

AC short circuit power : 6000 MVA

Control system :

Active power regulation

DC voltage regulation

Reactive power regulation

Developed by EDF R&D

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière16

Average HVDC VSC model

3-phase fault during 200 ms

1 2

YY1

400/450

12

400/450

YY2

F fault

DC link

HVDC_VSC_Link

+

LF + TD

AC_network2

+

LF + TD

AC_network1

+ +

GNDGND GNDGND

Q P

powerMeter1

sc

op

e

Q1

_m

es

sc

op

e

P1

_m

es

+

V1

Load-flowInitialization

+

0.50/100 cI2

V_mag

+

Load-flowInitialization

QP

powerMeter2

sc

op

eQ

2_

me

s

sc

op

e

P2

_m

es

V_mag

+

-V

+

0.50/100

cI1

+

-V

k_HVDCm_HVDC

CP+

XLPE_cable_1

7.00000E+01+

60uF!v

+

60uF!v

+

60uF!v

+

60uF!v

CP+

XLPE_cable_2

7.00000E+01

V1_magV2_mag

Idc1_mes

Q2_mes

phase_1phase_2

Idc2_mes

P1_mesP2_mes

Vdc2_mes

Q1_mes

Vdc1_mes

time (s)

y

PLOT

time (s)

y

PLOT

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière17

Average HVDC VSC model

Active power step change DC voltage step change

Simulation options : Δt = 50µs, tmax = 3s, CPU time = 4.2s

April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière18

HVDC VSC model – Next developments

Reactive power controller has to be improved

Contribution to CIGRE WG B4.38 (Simulation of HVDC and FACTS)

Implementation of manufacturer controllers models using DLL connection to obtain specific HVDC models

Available on demand