Sebastian Hoyoshttp://ece.tamu.edu/~hoyos/

Several of these slides were provided by

Dr. Jose Silva-Martinez and Dr. Jun Zhou

Fundamentals of Data Conversion: Part I.1

• Fundamentals of Analog-to-Digital Converters

• Introduction

• Sampling and Quantization

• Quantization noise and distortion

• INL and DNL

• Technological related issues

• Sample and Hold

• Switching issues

• S/H Accuracy

• Active S/H

• Switch around S/H

Outline

The Smartphone market

• Global smartphone market projected to growAnticipated global unit sales to approach 400 millions in 2013

(market research report from Forward Concepts Co)Projected revenue in 2012: $32.2 billion

(source: In-Stat Group)

GSM

WCDMA

FM

WiMax & 802.20

GPS

Bluetooth

WiFi

Multi-standard Wireless Systems• Multiple services

• Reuse circuits as much as possible• Power• Area• Competitiveness

• Smaller Cell phone,stronger function,longer battery duration

• Use of digital (analog unfriendly) nanometric tecnologies

Exponential growth in mobile computing and broadband wireless Major need for high dynamic range, wide-bandwidth, low power ADCs.

Multi-standard Wireless Systems

Bandwidth requirements for higher connectivity

Bluetooth, 802.11band 802.11g

Frequency (GHz)

Spec

turm

802.11a

5.42.4

UMTS

2

DECT

1.91.0

GSM

IS-95

DTV

0.05 0.8

> 45 dB

Higher flexibility on operational frequency and bandwidth, higher blocker rejection, higher dynamic range

Receiver Architectures:

Super-heterodyne, Low-IF, Direct Conversion, High-IF, Digital Radio

What is an Analog-to-Digital Converter (ADC)?Analog

Continuous with no apparent discontinuities

The way we interpret our surroundings: sound, light, temperature … etc

Digital01001011001010010101010101010100101001010010100101010010010010010110011001010100100101001001010

Discrete with limited range; based on binary numbers with limited number of bits.

The way we mathematically represent and process our world using electronic “brain” power

ADC

R. Walden, 1999

x(t)

Sampling

δ(t-nTS)

x(nTS)

Quantization

x(nTS)+q(nTS)

Decoding111110101

010001000

765

210

N bits

How does an ADC work?Analog Digital

Continuous with no apparent discontinuities

The way we interpret our surroundings: sound, light, temperature … etc

10010100101001010010011001011001010

01001011001010010101010101010100101001010010100101010010010010010110011001010100100101001001010

ADC Discrete with limited range; based on binary numbers with limited number of bits.

The way we mathematically represent and process our world using electronic “brain” power

How does an ADC work?

x(t)

Sampling

δ(t-nTS)

x(nTS)

Quantization

x(nTS)+q(nTS)

Decoding111110101

010001000

765

210

N bits

x(t)

t

x(n)

nTS

Analog Digital

10010100101001010010011001011001010

ADC

δ(n)

nTS

x(n)

nTS

2N Levels separated by 1LSB, 1LSB = VFS

* / 2N

* VFS = full scale range, Vmax-Vmin

Quantization noise

ADCs are indispensable, but now need to handle smaller signals at higher speeds with similar or higher resolutions.

ADCs: Yesterday vs. TodayExample: Digital photography (8-12b ADCs)

2000

CCD/CMOS Image Array

Balance Control

DSP(black level

compensation , encoding ...etc)

AMP ADC

0.5-0.8µm CMOS with 5V supply (moderate gate density and speed in DSPs)

2M pixel CCD sensor (low pixel scanning speed) Some pre-ADC analog conditioning ~ 2.5mV / LSB

2009

DSP(balance control, black level

compensation, image stabilization, exposure levels, noise reduction, lens shading

correction, encoding...etc)

AMP

CCD/CMOS Image Array

ADC

90nm-180nm CMOS with 1.2-1.8V supplies (high gate density and speed in DSPs)

12M pixel CCD sensor (high pixel scanning speed) Minimal pre-ADC analog conditioning ~ 0.5mV / LSB

Faster DSPs capable of performing numerous complex functions are developed thanks to advanced CMOS technologies

ADCs are becoming the bottleneck for advancement, and new design techniques need to be developed.

ADCs: Tomorrow?ADC IEEE literature survey: 2006-2008

Pipeline ADC is currently most published architecture Pipeline ADC is breaking the trend set by Sigma-Delta and Flash ADCs

Pipeline ADC is expected to be a key ADC architecture in future applications

2468

101214161820

0.1 1 10 100 1000 10000Signal Bandwidth (MHz)

Res

olut

ion

(bits

)

0.01

Sigma-DeltaPipelinedFlash

The development of new design techniques for high speed, low voltage and low power Pipeline ADCs is crucial to stay on the future applications roadmap

15M?20M?

From 1080P to 4K (2160P)?

4G?HDTV?

Tomorrow

Pipeline ADC ApplicationsToday

Pipeline ADC is breaking the trend set by Sigma-Delta and Flash ADCs, and driven by consumer electronics

Design Challenges of Pipeline ADCs in Advanced CMOS Technologies (Summary)

High Speed Low Voltage Low Power

DSP(balance control, black level

compensation, image stabilization, exposure levels, noise reduction, lens shading

correction, encoding...etc)

AMP

CCD/CMOS Image Array

ADC

With the added speed of new generations of DSPs, the ADC is becoming the bottleneck for overall system speed

in addition to increased speed, the DSP ability to perform more complex tasks will require higher ADC resolutions

Reduction of Device size allows for denser integration, but device reliability dictate lower supply voltages

Reduced supplies means reduced signal range, which requires a higher ADC accuracy for the same number of bits

Many applications are portable and operated from a battery

As a potentially power hungry component, the ADC power needs to be reduced to help prolong battery life

Digital Camera Example

Super-heterodyne Receiver

BPF LNA BPFVGA

LO2LO1

Digital Output

RF(0.45-5 GHz)

High IF(100-200 MHz)

Antenna

LPF Baseband ADC

Baseband(< 20 MHz)

Invented by Armstrong in 1918 Hardware specific radio architectureExtensive filtering to relax ADC specsSuitable for narrow-band applications

Design issues for multi-standard solutions

Excessive power at the front-end (Linearity issues)Extensive down conversions: LO and mixers increase both

noise and power consumptionExtensive filtering: Area, Power and Noise issuesNot fully compatible for the Telecoms roadmap

Limited by flicker noise

Not flexible

Hardware intensiveBPF LNA BPFVGA

LO2LO1

Digital Output

RF(0.45-5 GHz)

High IF(100-200 MHz)

Antenna

LPF Baseband ADC

Baseband(< 20 MHz)

Current Multi-standard designs

BPF LNA BPFVGA

LO2LO1

RF(1-2 GHz)

IF(100-200 MHz)

Antenna

RFSwitch

Receiver for standard 1

BPF LNA BPFVGA

LO2LO1

RF(1-2 GHz)

IF(100-200 MHz)

Receiver for standard 2

Minimum sharing of blocks

Area and powerconsumption overhead

Not Flexible at all

Limited number of standards can be accommodated

Introduction to Analog-to-Digital Converters

• Analog-to-Digital Converters (ADC) are necessary to convert real world signals (which are analog in nature) to their digital equivalents for easy processing.

• Common applications for ADCs are communication systems, TV receivers, Digital Oscilloscopes, Audio applications..

Analog

Efficient radio transceiver: Direct Conversion

Direct conversion + broadband ADC (1 receiver per service) Lowpass filter is required (~ 50-100 mW) 13-14 bits 80 MHz Lowpass ADC (500 mW from ADI) Bank of receivers, filters and ADCs

Antenna

RFsignal

Software Platform

DSP

or

FPGAs

LNA & VGA

16-Channel Multiband Digital Receiver

RF Filter 1 ADC 1IF Filter 180 MHz

4-channel digital

receiver

4-channel digital

receiver

ADC 2IF Filter 24-

channel digital

receiver

4-channel digital

receiver

Antenna

RFsignal

LNA & VGARF Filter 2

Optional

Mixer

Mixer

Frequency Synthesizer

Recent Approaches to Broadband Receivers Sample rate, downsampling and filteringR. Crochiere and L. Rabiner, Multirate Digital Signal Processing. Englewood Cliffs, NJ: Prentice Hall,

1983.

Sampling with built-in anti-aliasing Y. S. Poberezhskiy et.al. “Sampling and signal reconstruction circuits performing internal

antialiasing filtering and their influence on the design of digital receivers and transmitters,” TCASI, Jan. 2004.

A discrete-time RF sampling receiverR. B. Staszewski, et. al. “All-digital TX frequency synthesizer and discrete-time receiver for

Bluetooth radio in 130-nm CMOS,” IEEE J. Solid-State Circuits, Dec. 2004.

SDR receiverAbidi, “The path to software-defined radio receiver”, IEEE JSSC, May 2007

Frequency-domain-sampling receiversS. Hoyos and B. M. Sadler, “Ultra-wideband analog to digital conversion via signal expansion,” IEEE

Transactions on Vehicular Technology, Sept. 2006.

A. Abidi, “The path to software-defined radio receiver”, IEEE JSSC, May 2007

Direct conversion with tunable LO in the freq. range 800 MHz to 6 GHz.

Cascade of sincN filters followed by decimation to achieve the initializing needed.

Good for narrowband signals as a single ADC can handle the bandwidth. But SDR should also be good for wideband and ultra-wideband signals. Need parallel ADC to sample at a fraction of Nyquist rate. Parallelization of the front-end will be needed if want to keep the ADC sampling rate down.

UCLA SDR receiver

x A/D

A/Dx

jj( 1m+

∫( 1m+

∫1

Tc

0R

Frequency-Domain ADC Based on Fourier Coefficients

Mixers and integrators. Lower frequency sample and

hold requirements.

No signal reconstruction. Parallel digital processing.

Optimal bit allocation minimizes quantization error. Some samples may

not be quantized at all.

F0 F1 FN-1F2

1R2R

1NR −

S. Hoyos and B. M. Sadler, “Ultra-wideband analog to digital conversion via signal expansion,” IEEE Transactions on Vehicular Technology, Sept. 2006.

Dout

Antenna

LNA & VGARF Filter BP-Σ∆-ADC RF

signalVin

Software radio transceiver: Design Issues

Makes it sense to have a multi-standard solution based on this architecture?

Bandwidth required? Dynamic range required? DTV SNRsignal=25 dB; Blockers > 45 dB; Crest factor > 20 dB LNA+VGA+ADC Dynamic Range over 90 dB (practical ?) Can you use tracking filters? (back to the past)

Ultimate goal: Reality or Dream

Antenna

RF signalDSP

Filter+

LNA

T/R switch

Linear RF Power

amplifierDAC

Reconfigurableprograms

ADC

Concept introduced in 1991Modulation/demodulation waveforms in software Flexible multi-standard software architecture

1

2

3

LNA

RF Filter

RF

Anti-Aliasing

Filter

A/D

SCF, GmCOP-RC

Anti-Aliasing

Filter

A/D

Dig. Filter

DSP

DSPRF

RF Filter

RF Filter

A/D

Dig. Filter

DSPG

Dig. Mod.RF

IF or BB

DR

DR

BB

How much RF processing should be done before the ADC? The front-end must be scalable and configurable to fit multiple standards

Roadmap for high-resolution Receivers

The single-chip Transceiver Paradigm25

Critical Analog components must be minimized

• Modern technologies:“Digital intensive” System-on-Chip (SOC) environmentScaling of transistor dimensions in digital CMOS

technologiesIncreased intra-die variability from device scalingDefect densities increase in newer technologiesYields decrease as SOC chip sizes increaseYield impact on analog specifications leads to

process corner-based overdesignto allow for analog parameter variations Increased test cost

M. Onabajo, 2011

Fast CMOS ADC’s: State of the art

Freq (GHz)

Spec

turm

5.42.421.91.00.05 0.8

16

14

12

10

8

6

4

10 MS/s 100MS/s 1GS/s 10GS/s 100GS/s

Flash

Pipeline Interleaved

Sampling rate

Resolution

Trends:Extensive use of parallelism

Time interleavedReduced supply voltages make analog

more challengingHeadroom for amplifiersLittle room for cascodingPoor devices if VDS is further reduced

Use techniques that take advantage of digital trendsDigital circuitry is “cheap and fast”Tendency is Digitally Assisted Analog

Circuits

Research Goal

Pipeline

Calibrated Pipeline

BP Sigma-delta

R. Walden, 1999

LTE

Where we were in 99? Where we are?

A Little bit of History

A Little bit of History

Jitter and noise limitations on ENOB

Classic FoM to compare ADCs

Recent Σ∆ modulators

Bandwidth (Nyquist) vs. SNDR

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

10 20 30 40 50 60 70 80 90 100 110 120

BW

[Hz]

SNDR [dB]

ISSCC 1997-2009VLSI 1997-2009ISSCC 2009Jitter=1psrmsJitter=100fsrms

B. Murmann, "ADC Performance Survey 1997-2010, http://www.stanford.edu/~murmann/adcsurvey.html.

Energy per conversion at Nyquist rate

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

10 20 30 40 50 60 70 80 90 100 110 120

P/f s

[pJ]

SNDR [dB]

ISSCC 2010ISSCC 1997-2009VLSI 1997-2009FOM=100fJ/conv-stepFOM=10fJ/conv-step

B. Murmann, "ADC Performance Survey 1997-2010, http://www.stanford.edu/~murmann/adcsurvey.html.

The quantized signal presents a finite number of output values that are associated with digital codes

Data Converters: The main issue

What the problem is?

The quantized signal presents a finite number of output values that are associated with digital codes

Issues: Sampling, Holding and conversion

Properties of the Fourier Series

Properties of the Fourier Series

Modulation properties

Convolution in time

Relevant properties of the Fourier Series

Product in time

Relevant properties of the Fourier Series

Additional properties of the Fourier Series

Define the problem: Sampling Operation

Sampling Operation: Nyquist Rate

According to the sampling theorem: If no alias issues, then

Ideal sampling does not add distortion but replicas of the original spectrum

Signal Sampling Theorem

Time domain sampling

Frequency Spectrum

Signal Sampling employing a train of pulsesTime domain sampling with pulses

Spectrum

Alias issue if undersampling

Under-sampling of a broadband signal

The sampling and Held operations generate alias frequency components and (sinc) signal distortion, respectively

Error is an odd function (no even harmonic distortions, why?)

Quantization generates harmonic distortioncomponents when sinusoidal input signals are used

S/H and Quantization errors

Freq Freq

Error signal

Quantized signal

( ) ( ) ( )tErrortStS qin +=

Distortion due to quantization errors

ADC metrics: Quantization error• Signal is sampled at given instants• Signal is encoded to a limited number of codes resulting in quantization noise

(random signals) and distortion (periodic signals)

What the fundamental problem is?Mapping an infinite resolution analog signal into a digital but finite resolution representation

Quantization noise for Random (Ramp) input signal

( ) dB.N./

/P

/APP

SQNRN

noisenoise

signalideal 761026

12222

2

22

+=∆⋅∆

===

The maximum Signal-to-Quantization Noise ratio (SQNR) for an N-bit ADC:

02.676.1)dB(SNDRENOB −

=

• For an ADC with a measured SNDR, the effective number of bits is defined as:

ADC metrics: SQNR

The dynamic range of a system is equal to the signal to noise ratio measured over a bandwidth equal to half of the sampling (Nyquist) frequency

Then,

Is the total while the quantization noise density (quantization noise measured in a bandwidth of 1 Hz)

s

2

s

2

22

f6q

f2densityNoise

12q

==

=

σ

σ

Quantization noise density

fs/2-fs/2

Incommensurate fs and fin Sampling frequency fs is fixed.

Input frequency fin is chosen to satisfy (a) integernumber of cycles C and (b) N / C = fs / fin isincommensurate. An easy way is to make N a power of 2 and C a prime number. Additionally to guarantee thatthe input frequency falls on a DFT freq. bin use fin = fs/2-kfs/N, where k is an integer. Then checkinconmesurate requirement.

Windowing lifts the need to have an integer numberof cycles. Good for measurements.

Pick N depending on noise floor requirements: TheDFT noise floor is 10*log10(N/2) below the noise floor. Then DFT noise floor = -SNR_0dFS -10*log10(N/2).

Practical Limitations

Digital to Analog Converters

Practical Definitions

Practical Limitations

Practical Limitations

Quite critical issue! Usually not a major issue

Practical Limitations: Offset error

Practical Limitations

Usually not a major issue Quite critical issue!

Practical Limitations: Gain error

Practical Limitations: Differential Error

Practical Limitations

Practical Limitations: Integral error

Practical Limitations

Practical Limitations: Absolute Accuracy

Analog to Digital Converters

Usually the effects of

the systematic offsets

can be minimized

through calibration or

accounted in digital

domain

Digital to Analog Converters

Practical Limitations

Practical Limitations

Practical Limitations

DNL must be smaller or equal to 1 LSB

Practical Limitations

Offset Voltages

Practical Limitations