Little Devil Presentation

EE435 Final Project: 9-Bit SAR ADCCurtis Mayberry, Kyle Slinger, Yuan Ji()9-Bit SAR ADCRequirements9 bits of resolutionINL 1 LSBDNL 1 LSBSpeed > 0.2 MSPSPower < 20 mWArea < 1 mm^2

System DesignSAR ADC system level design

System Level DesignCharge Redistribution DAC Design

Charge Redistribution (Q=CV and Q is conserved)2 cycles samplingEstimate bit by bit9-bit SAR ADCFinal Schematic

9-bit SAR ADCSwitch Device SizingTransmission Gate Style Switch Used for Vin TrackingSingle Transistor Switches Used for Vdd and VssSmallest switch nmos=1.5um wide by 600nm longSmallest switch pmos=4.5um wide by 600nm longSizes increase proportionally to capacitor sizes4 sizes used. Largest can drive largest capacitor full range in 50ns.9-bit SAR ADCSwitches

9-bit SAR ADCSwitch TestingSwitching with the largest switch and largest load capacitorApproximately 50 ns required for maximum rise and fall time.This corresponds to 20 MSPS9-bit SAR ADCSwitch Testing

9-bit SAR ADCSwitch Testing

9-bit SAR ADCCapacitor Array

9-bit SAR ADCComparator

9-bit SAR ADCComparator PerformanceDC Gain: 79.91 dBResolution: 0.5 mV3 dB Bandwidth: 26.87 MHzPropagation Delay(1 LSB step): 6.5 nsHysteresis Voltage: +- 1.815 mV Power Consumption: 2 mW

9-bit SAR ADCComparator Design Strategy

9-bit SAR ADCComparator 1st Stage

9-bit SAR ADCComparator 2nd Stage

9-bit SAR ADCComparator Hysteresis

9-bit SAR ADCComparator 3rd Stage

9-bit SAR ADCPropagation Delay(1 LSB step)

9-bit SAR ADCPropagation Delay vs. Overdrive Amplitude

Digital SAR LogicHDL designHDL simulation in ModelsimElaboration ResultsSynthesis ResultsInitial Verification Test BenchFinal Implementation

FSM Diagram

HDL simulation Testbench Scenario 1

HDL simulation Testbench Scenario 2

HDL simulation Results

Elaboration

Synthesized Digital Control

Final Digital Schematic

Spectral and Static PerformanceSpectral analysis, INL, and DNLINL, DNL, and Spectral Testing Test Bench

Spectrum Analysis of the ADCSignal Frequency : 312.5 KHzSampling Frequency: 946.745 KhzM=512K=169

DNL: First fifth of code

Ran for 100us of a 543us rampDecreased run time0.99 DNL over this rangeINL over 100us from 0 to FS code6.4 LSB INL11 LSB offset

INL and DNL over 543us, covering FS

INL = 15.3 LSB INL index: 4.692 *10^-4DNL = 1.99 LSB DNL time: 1.122 *10^-4