Enabling SPACE applications in advanced CMOS nodes

Enabling SPACE applications in advanced CMOS nodes:Challenges and Opportunities

STMicroelectronics, CrollesV.Huard, Member of Technical Staff

March 1st-3rd, 2016

2/26/2016Presentation Title

Intel 4004IBM 1620 Power Mac G4Intel 286 Core i7 Extreme Edition

1 2.300 134.000 32 Million 1.3 Billion

1960 1970 1980 1990 2000 2010 2016

Music Hall capacity Large stadium capacity Population of Tokyo Population of China

Vostok 11st spaceflight

Voskhod 21st spacewalk

Appolo 111st moonwalk

Pioneer 11Saturn’s flyby

MIR1st space station

Voyager 2Neptun’s flyby

Sojourner1st Mars rover

ISSLargest space station

Hubble Hayabusa1st asteroid sampling

Rosetta1st comet landing

Space exploration and CMOS scaling50+ years of common history

# transistors

On-board processors performance scaling trend

1

10

100

1000

1980 1990 2000 2010 2020

Nor

mal

ized

per

form

ance

MA31750 (1.5um)

ERC32 (0.8um)

ERC32 (0.5um)

AT697 (0.18um)

NGFP (65nm)

NGMP (65nm)

ERC32– 90W

AT697– 40W

SCOC3– 15W

Source : L. Hili, P. Roche, F. Malou, ESCCON, 2016

NGMP LEON4

Long missions in varying & harsh environments

Interplanetary30+ years missions

LEO orbits: 7+ yearsGEO orbits: 20+ years

• Scaling and Reliability Challenges• Electromigration• BTI degradation• HCI degradation• TID degradation

• Device Reliability Modelling• Physic-of-Failure (PoF) approach supported by ST-specific C code• Industrial, automated extraction flow• Generic simulations outputs

• Digital Hardening Flow• Design For Reliability flow for digital IPs• Predictive EMG checker • Predictive TID modeling

• Analog Hardening Modelling• Design For Reliability flow for analog IPs• Reliability-enabled design framework• Automated flow for hardening

• Conclusions and Perspectives

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Outline


• Device Reliability Modelling• Physic-of-Failure (PoF) supported by ST-specific C code• Industrial, automated extraction flow• Generic simulations outputs




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Outline

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Scaling and Reliability challenges

Degradation Mechanisms

e-→→

= jZkT

eDcJ flow ρ*

Electromigration

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Interconnect scaling

55nm 28nm

Source : ITRS, 2001/2013.

Increased current density

Decreased EMG lifetime

Source : T. Oates et al., IRPS , 2012

Electromigration

EMG and Interconnect scaling

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e-→→

= jZkT

eDcJ flow ρ*

Electromigration

BTIHCI



1

10

100

1000

10000

100000

1000000

13

0n

m

90

nm

65

nm

45

nm

28

nm

28

FD

16

FF

14

FD

Re

lati

ve

lif

eti

me

• BTI mean degradation• Universal behavior

• Scaling model for mean degradation

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Device Reliability

BTI Degradation

Source : Mahapatra et al., IRPS, 2014

Source : Ramey et al., IRPS, 2015

Oxide Field Time Temperature Lifetime

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Device Reliability

BTI Recovery• BTI recovery modelling is a must-have feature

• BTI degradation is modulated by activity duty cycle

Source : Subirats et al., IRPS ,2014

10-6 10-4 10-2 100 10210-6 10-4 10-2 100 102

=>DF=50%

RC Model

AVGP : 1000101110.. ..0111000110

∆∆ ∆∆Vt (

A.U

)Total Time (s)

tBit

= 1µs 10µs 100µs

=>DF=25%

AVGP : 0010011000.. ..0000100100

Total Time (s)

0.0 0.5 1.0 1.5 2.00

1

Time (ms)

Vg(

%)

‘0’‘0’

‘1’

‘0’

‘1’

‘0’ ‘0’ ‘0’‘0’ ‘0’‘0’ ‘0’

‘1’ ‘1’ ‘1’‘1’ ‘1’‘1’‘1’ ‘1’

0 5 10 15 20

∆∆ ∆∆Vt (

u.a)

Bit Number

Pattern code: 00 101010001001101111

Bit sequence independence Duty cycle dependence• PRBS technique:• Fast measurement (1us)• Random bit sequence

• BTI induces additional variability

• Scaling model for BTI-induced mismatch

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Device Reliability

BTI-induced mismatch

BTI-induced mismatch Defect Centric model Scaling model

−∆Γ−=∆ ∑

∞

=

−

)!1(

/,(1

!

.)(

1 m

Vm

m

NeVCDF th

m

tN

th

t η

Poisson distribution of the average

number N t of defects

Exponential distribution of ∆Vth steps due to a

single defect

0

2

4

6

8

10

12

14

16

0 2 4 6 8 10 12 14 16

Nor

m. E

TA p

aram

eter

Oxide thickness (nm)

Poly SiON/PlanarMG HiK/PlanarMG HiK/UTBB FDSOIMG HiK/FinFet

�� =2∆��

∆��2

�� =∆��2

2∆��=

�

2. �. �0.��

��

Average impact/defect

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08

No

rma

l S

tan

da

rd d

ev

iati

on

Threshold Voltage shift (V)

Defect-centric distribution

Normal distribution

1M+ transistors

Source : Huard et al., IRPS ,2015Source : Angot et al., IEDM ,2013

• HCI mean degradation• Predictable behavior

• Scaling model for mean degradation

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Device Reliability

HCI Degradation

1

10

100

1000

10000

100000

1000000

13

0n

m

90

nm

65

nm

45

nm

28

nm

28

FD

16

FF

14

FD

Re

lati

ve

lif

eti

me

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

13

0n

m

90

nm

65

nm

45

nm

28

nm

28

FD

16

FF

14

FD

Tim

e e

xp

on

en

t

0

2

4

6

8

10

12

14

16

13

0n

m

90

nm

65

nm

45

nm

28

nm

28

FD

16

FF

14

FD

Vd

po

we

r e

xp

on

en

t

Voltage Time Lifetime

Source : Cacho et al., IIRW, 2014 and references therein

100806040200

40

30

20

10

0

Vth shift (mV)

Id

lin

dri

ft (

%)

0.40.30.20.10.0

0.10

0.08

0.06

0.04

0.02

0.00

ETA parameter Vth shift (mV)

ET

A p

ara

me

ter

Id

lin

dri

ft (

%)

Low energy mode

Low energy mode

High energy mode

Idli

nd

rift

(%

)

Vth shift (mV)

ETA for Vth shift (mV)

ETA

fo

r Id

lin

dri

ft (

%)

50403020100

99.9

99

95

90

80

7060504030

20

10

5

1

0.1

Vth shift (mV)

No

rma

l D

istr

ibu

tio

n P

erc

en

t (%

) Vgs>Vds

Vgs<Vds

Vgs=Vds

NBTI

• HCI induces additional variability

• Scaling model similar to BTI degradation• Amplitude depends on energy mode

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Device Reliability

HCI-induced mismatch

Energy mode dependence Comparison to BTI

Source : Huard et al., IEDM, 2015

nMOS pMOS

• Foundry qualification: BTI and HCI independent mechanisms

• BTI/HCI competition for the same defect creation sites

• Additive degradation exhibits pessimistic results

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Device Reliability

BTI/HCI degradation coupling

Source : Cacho et al., IRPS , 2014

PMOS NMOS

0

1

2

3

4

5

6

7

β=0.9

α=0.9

β=0.1α=0

NBTIHCINBTI

DIdsat Low to No Interaction High to full Interaction

DId

sat (

%)

Stress time0

1

2

3

4

5

6

7

8

9

10

11β=0.1

β=0.9

α=0.9

PBTIHCIPBTI

DIdsat Low to No Interaction High to full Interaction

DId

sat (

%)

Stress time

α=0

Defect sitescompetition

BTIHCI

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e-→→

= jZkT

eDcJ flow ρ*

Electromigration

BTIHCI



TID

Total Ionizing Dose

• FDSOI transistors more sensitive to TID than bulk one due to buried oxide layer

• Positive charge build-up in buried oxide layer may lead to:• Threshold voltage shift due to electrical coupling with front gate � observed• Formation of back-channel leakage path � not observed due to high quality interface

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Device Reliability

TID degradation

Threshold Voltage shiftsTID and space environment

1000 10000

Source: Space Environment Analysis, Experience and Trends

Orbit Altitude (km)

LEO GEO

100

Ann

ual d

ose

(kra

d)

1

1000

100

10

0.1

0.01

0.001

10 100 1000V

th s

hif

t (m

V)

TID dose (krad)

pMOS

nMOS

degradation

improvement

Both nMOS and pMOS Vth shifts in same direction- pMOS degradation- nMOS improvementAmplitude vary between nMOS and pMOS






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Outline

• Defect Generation Rate:• Physics-Of-Failure (PoF) approach• Model all reliability modes all over the Vgs/Vds/Vbs space• Stress renormalization using AGE rate function

∆�

�= ��

�� ! "�#, �� = � �%&, �'& , �(&, � )��,��

• ST-specific compiled C code:

• compatible with major CAD vendors for Spice and FastSpice simulations through API usage

• ST-specific equations for improved accuracy

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Opportunities

Device Reliability modelling

Framework strategy

Capability

Application Programming

Interface(UDRM, MOSRA, RelXpert)

Wrapper style flow

(TSMC Modeling Interface)

(TMI2)

External wrapper

program

(VerilogA module)

Built-in simulator

(equation written in

simulator language)

End-Of-Life Models

(aged SPICE corner)

Separation ageing

flow from SPICE flowYes No Yes No No

Integration effortNo

external .lib for ageing

parameter and C code

Additional integration TMI2 dedicated options are

written in .model

Additional scripting for files postprocessing

Additional integration

stepsNo

Ease at use Yes YesNo

additional postprocessingYes Yes

Deployment in

industrial flowYes Yes

Limited due to additional

postprocessing scripting

Yes Yes

Equation

implementation

capability

Complex functioncapability to implement

recovery contribution

Complex function capability

to implement recovery

contribution

Complex function capability to implement

recovery contribution

Limitedby CAD-vendor functions

No

Run timeFast

compiled c-code

Fast

compiled c-code

Mediumcompiled c-code + Perl script

Slowinterpreted function

Fast

Simulation capabilityVery High

1M+ Xtor (SPICE-FastSPICE)

High Up to 100K Xtor (SPICE)

Low (memory limitations

due to postprocessing)

High Up to 100K Xtor (SPICE)

Very High 1M+ Xtor (SPICE-FastSPICE)

Confidentiality of

ageing equationYes

compiled c-code

Yescompiled c-code

Yescompiled c-code

NoEquations in netlist

NoEquations in models

Source : Reliability subgroup in Compact Modeling Council

• Robust optimization• Automated reporting

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Extraction Flow

Reliability models Flow

2/26/2016

Various stress conditions

Various device parameters (Vth, Idlin, gmmax, Idon and Id (arbitrary Vds Vgs Vbs))

• Selection data• Filtering• Plot and sweep

hierarchy• Data to plot• Selection graph for fit

Stress 1 Stress 2

Interaction between modes

• Inputs:• Dedicated switches for degradation mechanisms’ selection (BTI/HCI/TDDB) for stimuli analysis• Fully scalable model in time with widened validity range (>WLR)• Dedicated TID switch with scalable dose model including recovery feature

• Outputs:• All informations stored in AGED_REPORT.log file:

• Drift informations for all devices• TDDB failure rate informations (also available in the terminal in prompt)

• TDDB model implemented in addition with BTI/HCI to address:• Transient and static violation of Vgs/Vds, time to breakdown determination• Failure rate of the circuit (FIT and ppm calculation) assuming a scaling factor

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Reliability simulations

Reliability simulations inputs and outputs

Defect Generation Rate

Stimuli Analysis






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Outline

• Aged corners in library:• Another process corner characterized using reliability models• Copes with intercell degradation sensitivity and duty cycle dependence

• Good Model-to-Hardware correlation

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Digital Design Hardening

Library characterization

Library characterization

1

16

31

46

61

76

91

10

6

12

1

13

6

15

1

16

6

18

1

19

6

21

1

22

6

24

1

25

6

27

1

28

6

30

1

31

6

33

1

34

6

36

1

37

6

39

1

40

6

42

1

43

6

45

1

46

6

48

1

49

6

51

1

52

6

54

1

55

6

57

1

58

6

60

1

61

6

63

1

64

6

66

1

67

6

69

1

70

6

72

1

73

6

75

1

76

6

78

1

79

6

Silicon driftsReference partsCAD drifts

800 Ring Oscillators – 1000hrs HTOL

Reference parts

BTI

HCI

Fre

quen

cydr

iftR

elat

ive

stre

ngth

s

Model-to-Hardware Correlation


• Digital design hardening flow:• Aging-aware selective gate replacement• DFR approach to optimize reliability/area/power trade-offs

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Digital Design for Reliability Flow


Place and Route

RTL2GATE

Timing Analysis

Nominal Aging-aware

Increasing size

Delay

Spec

MissionProfile

Aged Corners only

Fresh & Aged Corners

Fresh & Aged Corners

Worst-case slow corner



Fixed margin

2- 4%

8- 12% Time

• DFR flow enables:• Predictive degradation at System-level for concurrent engineering • Getting rid of full reliability trials on all components for System Failure Rate predictions

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Predictive DFR flow

0

1

2

3

A9_48h A9_168h A9_500h A9_1000h

AR

M A

9 f

req

ue

ncy

de

gra

dat

ion

(%

) Silicon measurements

CAD values

ARM 2xA9ARM 2xA9

45nm SiON ARM 2xA9 processor

0

5

10

15

20

48h 168h 500h 1000h 1500h

AR

M A

9 V

min

incr

ea

se (

mV

) Silicon measurements

CAD values

ARM 2xA9 processor

ARM 2xA9ARM 2xA9

28nm HiK

0

5

10

15

20

V1_14h V1_168h V2_48h V2_500h

AR

M A

9 V

min

in

cre

ase

(m

V)

Silicon measurementsCAD values

ARM 2xA9 processor

ARM 2xA9ARM 2xA9

28nm FD

Si-CAD validation at component level through technology scaling

• EMG checker flow:• SOC-level CAD solutions with wide ecosystem• Accurate design rules to allow MHC on complex blocks

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Predictive EMG checker flow

10.01.00.1

99

95

90

80

70

60

50

40

30

20

10

5

1

WLR projections

EMG block

Failu

re r

ate

Failure time

Layout view EM violations mapAccurate MHC

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EMG redundancy/robustness methods

Redundancy/Robustness methods

Source : B. Ouattara, ITC, 2013Source : B. Ouattara, Microelectronics Reliability, 2014

• Redundancy current paths

– Mitigate EMG and increase TTF

• Dynamic Halo on CT cells

EMG violations and redundancy effects

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Predictive TID modeling impact• DFR flow enables:

• Predictive degradation at both circuit (Path Replica) and System-level for concurrent engineering • Getting rid of full reliability trials on all components for System Failure Rate predictions

-16

-14

-12

-10

-8

-6

-4

-2

0

2

4

0 50 100 150 200 250

Fre

qu

en

cy c

ha

ng

e (

%)

Recovery time (hrs)

Experimental measurementsTID modeling

-16

-14

-12

-10

-8

-6

-4

-2

0

2

4

10 100 1000 10000

Fre

qu

en

cy c

hn

ag

e (

%)

TID dose (krad)

Critical Path Replica

Commercial MCU

TID modeling

Total dose impact on digital timing TID recovery fol lowing anneals

degradation

improvement

TID dose






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Outline

• Reliability insurance:• Analog IPs reliability guaranteed on worst-case mission profile by good design practices

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Analog Design Hardening

Industrial good design practices

Block Level Reliability

Simulations

Top Level Reliability

Simulations

Design analysis

and workaround

Good Design

Practices

Design under

standard operating conditions

Design under

aggressive operating conditions

Are devices within

standard operating

conditions?

Yes

No

OK

KO

Check with reliability team for

clearance?

Design impact analysis

• Enhanced design environment to support design good practices:• Reference design environment with reliability-enhanced features enabled by reliability models

• Degraded MOS highlight• Device Degradation Pareto• Device Degradation Histogram

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Industrial design for reliability framework

Device Degradation Pareto

Device Degradation Histo

• Enhanced design tool for automated transistors’ sizing for reliability:• Few optimization loops needed for optimal design• Average 10x gain in design time

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Automated sizing for reliability hardening

Source : Huard et al., IRPS ,2015

• Silicon-proven efficiency in advanced CMOS nodes to achieve:• More than 2x area savings compared to WLR rules• Similar reliability observed

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Automated sizing for reliability hardening

Source : Huard et al., IRPS ,2015

28nm UTBB FDSOI






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Outline

• 50 years of scaling rise reliability challenges• New device architectures

• Large range of interacting physical mechanisms

• Opportunities: Reliability-aware design flow• Known scaling rules for degradation modes

• Production CAD ecosystem to push knowledge upwards into design flow

• Entering Golden Age of design hardening flow

• Perspectives:• Lots of R&D efforts towards Resilient digital designs

• Key enabler to cope with High-Reliability markets

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Conclusions

SPACE products in advanced CMOS nodes

• European initiative towards resilient digital designs• Dynamic Wearout Management inc. in-situ monitors and regulation

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Perspectives

Resilient digital designs

Digital IP

IS2M Flags

OR tree MacroFlag

DWM ControlReset Flag

AVS/ABB regulationVoltageRegulator

IS2M

Aging-aware SW

• All these works have been made possible throughout the years by:• Emmanuel Vincent• Florian Cacho• Xavier Federspiel• David Ney• David Roy• Chittoor Parthasarathy• Etienne Maurin• Lise Doyen• Paras Garg• Anuj Gupta• Philippe Roche• Ahmed Benhassain• Souhir Mhira• Cheikh Ndiaye• Ajith Sivadasan• Damien Nouguier• All former PhD students

• Special thanks for TID experimental results provided by:• Gilles Gasiot• Dimitri Soussan

• The underlying research and development has been supported in part by• DGA, DGE, CATRENE

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Conclusions

Acknowledgments

38

Documents

Enabling SPACE applications in advanced CMOS nodes