Interface control process for metal/germanium Schottky ...However, continuous shrinking CMOS device into 16 and 11 nm technology nodes is facing tremendous difficulties, including

2015 Master Thesis

Interface control process for

metal/germanium Schottky contact

Masaaki Motoki

13M36377

Department of Electrical and Electronic Engineering

Tokyo Institute of Technology

Supervisor

Associate Professor: Kuniyuki Kakushima

Professor: Hiroshi Iwai

Abstract

February, 2015 Abstract of Master Thesis

Interface control process for metal/germanium Schottky contact

Supervisor: Associate Prof. Kuniyuki Kakushima

Supervisor: Prof. Hiroshi Iwai

Tokyo Institute of Technology

Department of Electrical and Electronic Engineering

13M36377 Masaaki Motoki

Germanium (Ge) channels have attracted lots of interests as alternatives to further improve

the performance of complementary metal-oxide-semiconductors (CMOS) owing to its high

intrinsic mobility. One of the concerns is the presence of Fermi-level pinning (FLP) near the

valence band which leads large Schottky barrier height (SBH) for electrons, which eventually

increases the contact resistance for n-type Ge channel. Un-pinned metal contact processes

including thin oxide insertion between metal and Ge substrate, and formation of thin

amorphous Ge layer at the interface have been proposed so far. Due to insertion thickness

sensitivity and small process window, a stable un-pinned process is required. On the one hand,

atomically controlled interfaces process has been reported as offer promising prospects.

Because SBH has been alleviated by formed atomically smooth interfaces without insertion

layers.

In this thesis, a novel interface control process to modify the energy barrier is presented.

Abstract

Firstly, characteristics of thermally stable metals are presented and secondly an original little

interface reaction process using interface impurity incorporation is described.

Thermally stable nickel germanide (NiGe) films, which are formed by cyclic deposition of

nickel (Ni) and Ge layers, are used as a contact metals. A stable sheet resistance in the

temperature range from 300 to nearly 500 degree C is obtained, and nearly ideal Schottky

diode characteristics are achieved, owing to little interface reaction. The x-ray diffraction

spectrum of NiGe on Ge substrates, analyzed by in-plane x-ray diffraction, is revealed the

formation of NiGe when annealed at 400 degree C.

Next, effect of incorporated phosphorous (P) atoms between NiGe and n-Ge substrate is

performed by changing the first Ni layer to Ni3P layer. An effective energy barrier height

modification is confirmed by diode characterization, however, Ohmic contacts is not observed

at all annealing temperature range. With impurities incorporation of both silicon (Si) and P

atoms at the interface between NiGe and n-Ge substrate, extracted SBH is modified more

effectively than those with incorporation of P atoms at an annealing temperature of 400 degree

C. Especially, Ohmic characteristics are observed and a contact resistance is obtained of 10-3

cm2 at 400 degree C. This results attribute alleviation in FLP and modulation in SBH for

electrons. Presumably, the main reasons are band bending due to increased doping

concentration by effective P atoms incorporation and alleviation of FLP due to reduced

interface states by thin Si layer insertion.

This finding may give strong insight into contact resistance reduction and FLP alleviation

for Ge nFET with low temperature process.

Abstract


I

Contents

1 Introduction

1.1 Introduction of CMOS scaling...................................................2-4

1.2 Introduction of high mobility channel material..........................4-5

1.3 Introduction of metal Schottky source/drain.........................5-6

1.4 Issues of metal/germanium Schottky junction.......................6-7

1.5 Reports on un-pinned metal/germanium process......................7-10

1.6 Purpose of this study......................................................................10

1.7 Outline of this thesis...................................................................11-12

1.8 Metal selection..................................................................................12

References

2 Experimental Setup

2.1 Device fabrication

2.1.1 Radio frequency magnetron sputtering.......................................17

2.1.2 Lift-off process............................................................................18

2.1.3 Rapid thermal annealing..............................................................18

2.1.4 Vacuum evaporation..............................................................18-19

2.2 Four-point method...........................................................................19

2.3 Transmission electron microscopy..................................................20

2.4 J-V characteristics


II

2.4.1 Thermionic emission theory....................................................21

2.4.2 Image-force-induced barrier lowering.....................................22

2.5 X-ray reflectivity..............................................................................22

2.6 X-ray diffraction.........................................................................23-24

2.7 Circular transmission line method............................................24-26

References

3 Composition and morphology of Ni-germanide films

3.1 Introduction.....................................................................................29

3.2 Cyclically stacked process..........................................................29-30

3.3 Measurement of Ge film density.....................................................30

3.4 Process of Ni-germanide..................................................................31

3.5 Measurement of sheet resistance...............................................31-32

3.6 XRD analysis of stacked germanide film..................................32-33

3.7 J-V characteristics of stacked germanide diode.......................33-35

3.8 Conclusions.......................................................................................36

References

4 Schottky Barrier Height Lowering with Dopant

Incorporation

4.1 Effect of P atoms incorporation.................................................39-42

4.2 Extraction of contact resistance on Ni3P/n-Ge diode....................42

4.3 Extraction of Schottky barrier height on Ni3P/n-Ge diode.....43-44

4.4 Incorporation P atoms for NiGe/n-Ge diode..................................45


III

4.5 Measurement of J-V characteristics...............................................45

4.6 Observation of cross-sectional surface...........................................47

4.7 Discussion and Conclusions.......................................................48-49

References

5 Thin Film Insertion into Metal/n-Ge Interface

5.1 Si film insertion................................................................................52

5.2 Measurement of J-V characteristics.........................................52-54

5.3 Dependence of Si thickness........................................................54-56

5.4 Extraction of contact resistance................................................56-57

5.5 Extraction of Schottky barrier height......................................57-59

5.6 Discussions..................................................................................60-62

5.7 Conclusions.......................................................................................63

References

6 Conclusions.............................................................................65-66

Presentations...................................................................................68

Acknowledgements......................................................................69


IV

Chapter 1. Introduction

1

Chapter 1

Introduction

1 Introduction

1.1 Introduction of CMOS scaling...................................................2-4

1.2 Introduction of high mobility channel material..........................4-5

1.3 Introduction of metal Schottky source/drain.........................5-6

1.4 Issues of metal/germanium Schottky junction.......................6-7

1.5 Reports on un-pinned metal/germanium process......................7-10

1.6 Purpose of this study......................................................................10

1.7 Outline of this thesis...................................................................11-12

1.8 Metal selection..................................................................................12

References


2

1.1 Introduction of CMOS scaling

Very Large Scale Integration (VLSI) technology has been considered

essential to modern information society. VLSI circuits have been constructed by

Complementally Metal-Oxide-Semiconductor (CMOS) Field-Effect-Transistor (FET).

It is necessary for development of Information Technology (IT) that CMOSFET with

high speed, low power consumption is achieved. The key to the advancement of VLSI

technology is the device scaling which means scaling down the size of MOSFETs.

Table 1.1 and Fig. 1.1 show the scaling rules for various device and circuit parameters.

Scaling rules show speed up of circuit and reduction of power consumption are

obtained with the scaling of the device dimensions [1.1]. Therefore, scaling leads to

improvement of convenience for people and saving energy.

Table 1.1 Constant-field scaling of MOSFET device and circuit parameters.

The scaling remains electrical field unchanged.

1Electric field (E)

1/kJunction depth (xj)

kDoping concentration (N)

1/kDepletion layer width (Wd)

1/k2Device area (A)

1/kCircuit delay time (t)

1/k2Power consumption (P)

1/kGate oxide thickness (tox)

1/kChannel width (W)

1/kChannel length (L)

Multiplicative factorParameters

1Electric field (E)

1/kJunction depth (xj)

kDoping concentration (N)

1/kDepletion layer width (Wd)

1/k2Device area (A)

1/kCircuit delay time (t)

1/k2Power consumption (P)

1/kGate oxide thickness (tox)

1/kChannel width (W)

1/kChannel length (L)

Multiplicative factorParameters


3

Fig. 1.1 Schematic illustration of scaling MOSFET.

However, continuous shrinking CMOS device into 16 and 11 nm technology nodes is

facing tremendous difficulties, including severe short channel effects, degraded

driving current, dopant penetrations and poly-silicon depletion, high-field effects,

direct gate tunneling current and high series resistance [1.2]. Thus, the introduction of

new materials such as high-k gate insulators (to replace SiO2 gate insulators), strained

silicon, Ge and III-V substrates (to replace Si substrates), metal gates (to replace

polysilicon gates) and metal source/drains (S/Ds) (to replace doped silicon S/Ds), and

structures such as silicon on insulator (SOI), Fin and silicon nanowires (SiNWs), have

been investigated as shown in Table 1.2 and Fig. 1.2 [1.3].

Table 1.2 The building-block materials of conventional and new material MOSFETs.

Strained-Si, Ge, III-VSiSubstrate

Metal (silicide)DopedS/D

MetalPolysiliconGate electrode

high-kSiO2Gate insulator

New materialConventional

Strained-Si, Ge, III-VSiSubstrate

Metal (silicide)DopedS/D

MetalPolysiliconGate electrode

high-kSiO2Gate insulator

New materialConventional


4

Fig. 1.2 Schematic illustration of MOSFET with new structures.

1.2 Introduction of high mobility channel material

The scaling of advanced MOS devices is approaching its technological and

fundamental limits. Further performance enhancements of MOSFETs require

exploitation of more efficient materials and architectures. An important factor defining

the transistor speed is the carrier injection velocity into the channel region which is

proportional to the carrier mobility. Therefore, germanium has been receiving

attention as an alternative channel material [1.4] due to its high intrinsic mobility.

Table 1.2 show properties of semiconductors [1.5], germanium has two times higher

for electrons and four times higher for holes as compared to those in silicon. Thus,

both n- and p-Ge are expected using as channel material of CMOS due to the highest


5

harmonic average between electron and hole mobility in the table. However, Ge is

enormously affected by short channel effect because Ge permittivity is higher than Si

one. We prevent the short channel effect by metal Schottky source/drain as we shall

discuss later.

Table 1.2 Mobility and band gap for Si, Ge, GaAs, InAs and InSb.

1.3 Introduction of metal Schottky source/drain

For short channel MOSFETs, there are some issues which are decrease of

threshold voltage, drain induced barrier lowering (DIBL) and so on. Thus, it is one of

the key for suppression of short channel effects to achieve abrupt and shallow junction

at source/drain(S/D) [1.6]. An approach to realize the abrupt and shallow junction is

using Schottky barrier S/D, which is typically formed by silicide. Schottky barrier S/D

has some advantages which is atomically abrupt and shallow junctions and low

parasitic resistance [1.7]. In addition to these advantages, a low temperature process


6

capability is another advantage of Schottky barrier S/D [1.8]. Therefore, Schottky

barrier S/D is the key technology to realize suppression of short channel effects as

shown in Fig. 1.3.

Fig. 1.3 (a) 3D-FETs with conventional pn junctions suffer from short channel effects

with channel length scaling due to the dopant diffusions which lower the abruptness.

(b) Metal (silicide) Schottky junction is one of the solutions to suppress short channel

effects because of abrupt junctions [1.9].

1.4 Issues in metal/germanium Schottky junction

Reduction of parasitic resistance of metallic contact on Ge substrate is one

of the issues for Ge FETs, and low contact resistance of NiGe with Ge substrate has

been studied as metallic contact on Ge substrate [1.10]. However, agglomeration of

NiGe roughens metal/Ge interface thereby increasing the sheet resistance at the

interface [1.11]. Moreover, as shown in Fig. 1.4 [1.12], a strong Fermi-level pinning

near the valence band of Ge results in large Schottky barrier height for electrons (Bn),

which eventually leads to high contact resistance for n-type Ge channel [1.13].

Hard

mask

Gate

SourceDrain

SourceDrain

Gate

Lphy

Do

pa

ntC

on

c.

y position

Gate

(a) Conventional doping S/D

Gate

MetalMetal

MetalMetal

Gate

Me

tal C

on

c.

y position

Gate

Lphy = Leff

(b) Schottky barrier S/D


7

Fig. 1.4 Barrier height for electrons vs metal work function of Ge.

1.5 Reports on un-pinned metal/germanium process

Fermi level pinning at the metal/Ge Schottky junction is released and

Schottky barrier height comes to be modulated by tuning metal work function. Fermi

level position is then determined by the insulator, and theoretically any insulator (SiN

[1.14],Ge3N4 [1.15], or Al2O3 [1.16], etc.) which has larger band gap and smaller

dielectric constant can release Fermi level pinning more effectively as shown in Fig.1.5

[1.17]. However, there has a problem which is the sensitivity of insulator thickness and

the trade-off relation between insulator thickness and contact resistance as shown in

Fig. 1.6. The inserted interlayer would need to be kept a thickness of more than 1 nm,

which would limit the suppression of contact resistance for metal/n-Ge.


8

Fig. 1.5 The schematic band diagram at the metal/Ge Schottky junction

(a) without thin insulator and (b) with thin insulator.

Without insulator, the Fermi level of the metal is pinned close to a charge

neutrality level (ECNL), which is located near the Ge valence band.

With insulator, Fermi level pinning is released and effective Schottky barrier

height becomes small.

Fig. 1.6 J-V characteristics of Al/SiN/n-Ge shottky diodes.


9

Another solving Fermi level pinning has proposed TiN/n-Ge, with an approximately

1-nm-thick interlayer formed at a TiN/Ge interface, by direct sputter deposition from

a TiN target and subsequent post-metalization annealing at 350oC as show in Fig.1.7

[1.18]. However, there has a problem which is sensitivity and limit of annealing

temperature.

Fig. 1.7 J-V characteristics and HAADF-STEM image

of TiN/n-Ge Schottky diodes at 350 oC annealing.

And so atomically controlled interfaces process is offer promising prospects. The

Fe3Si/n-Ge(111) and Fe3Si/n-Ge(100) contacts by low-temperature molecular beam

epitaxy(LTMBE) have been demonstrated as shown in Fig. 1.8 [1.19]. The Schottky

barrier height of atomically controlled interfaces for Fe3Si/n-Ge(111) becomes lower

than the Schottky barrier height of Fe3Si/n-Ge(100) as shown in Fig.1.9 [1.19].


10

Fig.1.8 Cross-sectional TEM images of

(a)Fe3Si/n-Ge(100) and (b)Fe3Si/n-Ge(111) interfaces grown by LTMBE [1.19].

Fig.1.9 (Color online) SHB (b) vs metal work function (m)

for metal/n-Ge junction [1.19]

1.6 Purpose of this study

It is necessary for futures n-Ge MOSFET to lower contact resistance, control

junction position and apply low temperature process. The purpose of this thesis is to

present a novel interface control process in order to modification of the energy barrier

on metal/germanium for low contact resistance with compatible gate formation

processes.


11

1.7 Outline of this thesis

Fig. 1.10 Contents of this thesis

The contents of this thesis is shown in Fig.1.10. This thesis is consisted of 6

parts.

In chapter 1, the introduction of this thesis is stated.

In chapter 2, the fabrication of devices and detail of measurement are explained.

In chapter 3, characteristics of NiGe are examined. A stable characteristics can be

achieved by using cyclically stacked germanidation process. Moreover, different

electrical characteristics of Schottky diodes between formed by cyclically deposition

and by Ni-single layer deposition are investigated.


12

In chapter 4, electrical characteristics of Ni3P/n-Ge diode have been investigated in

order to confirm effect of P atoms incorporation. And Schottky barrier height

modulation with impurity incorporated NiGe/n-Ge diode is examined. Then a problem

is discussed in order to achieve Ohmic characteristic.

In chapter 5, Schottky barrier height modulation by P atoms and Si film insertion is

researched. It was fond that dependence of inserted Si layer thickness can be important

to achieve Ohmic characteristic. Moreover, the cause of Ohmic contact and a way to

de-pin Fermi-level are considered.

Finally, chapter 6 summarizes this study.

1.8 Metal selection

In this study, Nickle germanide (NiGe) which is used for metal source/drain

is selected due to low temperature formation at minimum 250oC [1.20] and very low

specific resistance [1.21]. Therefore, properties of NiGe/Ge contact is investigated in

this thesis afterward.


13

References

[1.1] Y. Taur, and T. H. Ning, “Fundamentals of MODERN VLSI DEVICES,” p.204-

p.206, Cambridge University Press (1998).

[1.2] Y. Song, H. Zhou, and Q. Xu: “Source/drain technologies for the scaling of

nanoscale CMOS device’’, Solid State Sciences, 13, p.294-p.305 (2011)

[1.3] T. Skotnicki, James A. Hutchby, Tsu-Jae King, H.-S. Philip Wong and Frederic

Boeuf, “The end of CMOS scaling: toward the introduction of new materials and

structural changes to improve MOSFET performance,” IEEE Circuits and Devices

Magazine, 21, p.16-p.26 (2005).

[1.4] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L.

Kwong, and D. A. Antoniadis, “Epitaxial Strained Germanium p-MOSFETs with HfO2

Gate Dielectric and TaN Gate Electrode,” Technical Digest - International Electron

Devices Meeting, p.433-p.436 (2003).

[1.5] D. Schroder, “Semiconductor Material and Device Characterization,” third

edition, WILEY-INTERSCIENCE (2006).

[1.6] K. Tanaka, K. Takeuchi and M. Hane, “Practical FinFET Design considering

GIDL for LSTP (Low Standby Power) Devices,” Technical Digest - International

Electron Devices Meeting, p.980-p.983 (2005).

[1.7] J. M. Larson and J. P. Snyder, “Overview and Status of Metal S/D Schottky-

Barrier MOSFET Technology,” IEEE Transactions on Electron Devices, 53, p.1048-

p.1058 (2006).

[1.8] W. Mizubayashi, S. Migita, Y. Morita, and H. Ota, “Exact Control of Junction

Position and Schottky Barrier Height in Dopant-Segregated Epitaxial NiSi2 for High


14

Performance Metal Source/Drain MOSFETs,” Digest of Technical Papers -

Symposium on VLSI Technology, p.88-p.89 (2011).

[1.9] A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I.

Mizushima, K. Okano, H. Kawasaki,T. Izumida, T. Kanemura, N. Aoki, A. Kinoshita,

J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi,

Y.tsunashima, “High-Performance FinFET with Dopant-Segregated Schottky

Source/Drain,” Technical Digest - International Electron Devices Meeting, p.1-p.4

(2006).

[1.10] X. V. Li, M. K. Husain, M. Kiziroglou, and C.H. de Groot, “Inhomogeneous

Ni/Ge Schottky barriers due to variation in Fermi-level pinning” Microelectronic

Engineering, 86, p.1599-p.1602 (2009).

[1.11] Q. Zhang, N. Wu, T. Osipowicz, L. K. Bera, and C. Zhu, “Formation and

Thermal Stability of Nickel Germanide on Germanium Substrate,” Japanese Journal

of Applied Physics, 44, L1389-L1391 (2005).

[1.12] A. Dimoulas, P. Tsipas, and A. Sotiropoulos, “Fermi-level pinning and charge

neutrality level in germanium,” Applied Physics Letters, 89, 252110 (2006).

[1.13] L. Lin, Y. Guo and J. Robertson, “Metal silicide Schottky barriers on Si and Ge

show weaker Fermi level pinning” Applied Physics Letters, 101, 052110 (2012).

[1.14] M. Kobayashi, A. Kinoshita, K. Saraswat, H.S.P. Wong and Y. Nishi, “Fermi

level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-

semiconductor field-effect-transistor application” Journal of Applied Physics, 105,

023702 (2009).

[1.15] R. R. Lieten, S. Degroote, M. Kuijk, and G. Borghs, “Ohmic contact formation

on n-type Ge,” Applied Physics Letters, 92, 022106 (2008).


15

[1.16] N. Tomonori, K. Koji and T. Akira, “A Significant Shift of Schottky Barrier

Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin

Insulating Film,” Applied Physics Express, 1, 051406 (2008).

[1.17] D. Connelly, C. Faulkner, D. E. Grupp and J. S. Harris, “A New Route to Zero-

Barrier Metal Source/Drain MOSFETs,” IEEE Transactions on Nanotechnology, 3,

p.98-p.104 (2004).

[1.18] M. Iyota, Y. Yamamoto, D. Wang, H. Yang and H.Nakashima, “Ohmic contact

formation on n-type Ge by direct deposition of TiN,” Applied Physics Letters, 98,

192108 (2011).

[1.19] K. Yamane, K. Hamaya, Y. Ando, Y. Enomoto, K. Yamamoto, T. Sadoh, and M.

Miyao, “Effect of atomically controlled interfaces on Fermi-level pinning at metal/Ge

interfaces,” Applied Physics Letters 96, 162104 (2010)

[1.20] T.Sadoh, H.Kamuzuru, A.Kenjo, and M.Miyao, “Low temperature

formation(500oC) of poly-Ge thin-film transistor with NiGe Schottky source/drain,”

Applied Physics Letters 89, 192114 (2006)

[1.21] S.Zhu and A.Nakajima, “Annealing Temperature Dependence on Nickle-

Germanium Solid-State Reaction,” Japanese Journal of Applied Physics vol, 44 No,

24 pp. L753-L755, 192114 (2006)

Chapter 2. Experimental Setup

16

Chapter 2

Experiment Setup

2 Experimental Setup


2.1.1 Radio frequency magnetron sputtering.......................................17

2.1.2 Lift-off process............................................................................18

2.1.3 Rapid thermal annealing..............................................................18

2.1.4 Vacuum evaporation..............................................................18-19

2.2 Four-point method...........................................................................19

2.3 Transmission electron microscopy..................................................20


2.4.1 Thermionic emission theory....................................................21

2.4.2 Image-force-induced barrier lowering.....................................22

2.5 X-ray reflectivity..............................................................................22

2.6 X-ray diffraction..............................................................................23

2.7 Circular transmission line method............................................24-26

References


17


2.1.1 Radio frequency magnetron sputtering

Thin films are the subject of matter for many applications and have got

significant importance in physical sciences and engineering. Sputtering is one

important technique used for thin film deposition. Radio frequency (RF) magnetron

sputtering is an enhanced sputter method which enables a higher deposition rate at low

operating pressure together with the possibility to obtain high quality films at low as

well as high substrate temperatures. In this study, the surface contact metals were

deposited by RF magnetron sputtering using the argon (Ar) gas. In the chamber filled

with the Ar gas, the high voltage is applied in high frequency between the target side

and the sample side. The surface atoms of target material are removed and deposited

on a substrate by bombarding the target with the ionized Ar atoms. The magnet, located

behind the target, enhances ionization and effectively directs the sputtered atoms

towards the substrate, and the samples are not damaged by the plasma. Schematic

diagram of this method is shown in Fig. 2.1.

Fig. 2.1 Schematic diagram of RF magnetron sputtering.

target

sample

ArAr

magnet

Ar

ion sheath

capacitive

coupling


18

2.1.2 Lift-off process

Lift-off is the process which selectively removes deposited films. Following

photolithography and deposition, resists and deposited films which exist on excess

area are left by ultrasonic cleaning with acetone.

2.1.3 Rapid thermal annealing

Rapid thermal annealing (RTA) was used for produce of Ni-germanide. The

heat chamber was vacuated and filled in nitrogen gas, so that the effect of prevention

oxidation of the sample. The samples were annealed by infrared ray for 1 minute.

2.1.4 Vacuum evaporation

Al was used for backside contact of Schottky diodes. Al was deposited by

vacuum evaporation method which is suitable for deposition of metallic thin films onto

cool surface. A suitable material (the source), in this study using Al, is placed inside

the vacuum chamber with a heater. When the temperature reaches the evaporation

temperature of the source, atoms or molecules start to leave the surface of the source

and travel in a more or less straight path until they reach another surface (substrate,

chamber wall, instrumentation). Since these surfaces are at much lower temperatures,

the molecules will transfer their energy to the substrate, lower their temperature and

condense. The schematic diagram of this method is shown in Fig. 2.2.


19

Fig. 2.2 Schematic diagram of vacuum evaporation.

2.2 Four-point method

In a planar IC technology, it is useful to define a quantity, called the sheet

resistivity (sh). That is because the thickness of conducting regions is uniform and

normally much less than both the length and width of the regions. sh of the sample

was measured by four-point method. In this method, put four probes on the sample in

a straight line, and the resistance is obtained by measuring difference of potential

between the two inner probes when a small current is passed through the two outer

probes as shown Fig. 2.3.

Fig. 2.3 Schematic illustration of four-point method.

sampleAl source

VI

I

sample

substrate

thickness


20

2.3 Transmission electron microscopy

Transmission electron microscopy (TEM) is one of the electron microscopes.

In this study, observations of germanide cross section surface were using TEM. By

irradiating electrons to the thin sample, some electrons are scattered and others are

transmitted. Because the amount of transmitted electrons depends on the structure or

component of each portion, the image is generated by the interference of the

transmitted electrons. In TEM, the specimen shape and surface structure in addition to

information of the internal material which is the degree of cohesion, crystalline

patterns, presence of lattice defect, and such as orientation directions of the crystal can

be known by observing the internal structure of the sample. Typically a TEM consists

of three stages of lensing as shown Fig. 2.4. The stages are the condenser lenses, the

objective lenses, and the projection lenses. The condenser lenses are responsible for

primary beam formation, whilst the objective lenses focus the beam that comes

through the sample itself. The projection lenses are used to expand the beam onto the

fluorescent screen or other imaging device, such as film.

Fig. 2.4 Organizational illustration of the TEM.

illumination

source

condenser

lens

specimen

objective

lens

projection

lens

image

plane

fluorescent

screen


21


2.4.1 Thermionic emission theory

Current characteristics of Schottky diodes (J-V) were measured by

semiconductor parameter analyzer. In this study, the method of analyzing J-V data used

thermionic emission (TE) theory and Thermionic-field emission (TFE). Generation

current from depletion is not considered, as this effect is negligible in the prepared

samples in this study. From the TE theory [2.1],

1exp2

nkT

qV

kT

qTAJ

appBn, (2.1)

can be obtained where A* is the effective Richardson constant, T is the absolute

temperature, q is the electronic charge, Bn is the Schottky barrier height, k is the

Boltzmann’s constant, Vapp is the applied voltage, and n is the ideality factor (n-factor)

which is related to the slope. Bn and n-factor can be obtained by fitting of J-V

characteristics. A* is 133A/cm2/K2 in this study. If the Schottky diode is applied values

of reverse voltage greater than 3kT/q, eq. (2.1) can be reduced to eq. (2.2).

kT

qTAJ Bn

exp2*

(2.2)


22

2.4.2 Image-force-induced barrier lowering

Image-force is the interaction due to the polarization of the conducting

electrodes by the charged atoms of the sample. The image-force effect cause the energy

barrier for electron transport across a metal-silicon interface to be lowered by

Ge

Bn

qE

4 (2.3)

where E is the electric field and Ge is the permittivity of Ge. The actual energy barrier

for electron transport in a Schottky barrier diode is (qBn-qBn) [2.2].

2.5 X-ray reflectivity

X-ray reflectivity (XRR) is meant for determining the thickness and density

of a sample. Incident x-ray at very shallow angles is reflected off the thin film surface

and interface at film/substrate respectively, therefore interference wave occurs when

two waves meet while traveling along the same medium (as shown in Fig. 2.5). Also,

reflectance ratio is changed continuously according to angle of incidence, and specific

vibronic structure shows up in response to intrinsic thickness, density, and interface

roughness. The thickness, density, and roughness are evaluated according to analyze

specific vibronic structure.

Fig. 2.5 Diagram of x-ray specular reflection


23

2.6 X-ray diffraction

In-plane x-ray diffraction (XRD) techniques with a grazing incident x-ray

beam has been used successfully to enhance the thin-film intensities and to minimize

the substrate in the analysis a thin-film [2.3]. Three-dimensional thin-film structure,

such as preferred orientation, orientational relationship and lattice distortion between

an epitaxial film and its substrate, crystallite-size anisotropy, etc, can be obtained from

in-plane XRD measurements. The geometrical layouts of in-plane XRD measurements

are shown in Fig. 2.6.

Fig. 2.6 Geometry of in-plane XRD measurement

The penetration of an incident x-ray beam into a sample is deep when the incident

angle is large, whereas the penetration depth can be extremely shallow for a very small

incident angle (as shown in Fig. 2.7). Therefore, the in-plane XRD technique using a

number of different incident angles can be used for an effective and non-destructive

structure-depth analysis of a thin films.


24

Fig. 2.7 Schematic drawing of diffraction intensities from a thin film deposited

on a substrate with different incident angles.

2.8 Circular transmission line method

Transmission line method (TLM) is often used to determine the specific

contact resistance(c) of Ohmic contact systems in semiconductor devise [2.4, 2.5].

Test pattern of either rectangular or circular geometry is commonly used [2.6], as

depicted in Fig. 2.8 and Fig. 2.9. In rectangular contacts, the current flow at contact

edge can significantly affect the results of contact resistance measurement unless mesa

structures current flow patterns. In circular test patterns this complication can be totally

avoided without making mesa structures.


25

Fig. 2.8 Test pattern for Ohmic contact characterization: Rectangular pattern

where W is the width of the pads, l is the length of the pads

and d is the contact pad separation.

Fig. 2.9 Test pattern for Ohmic contact characterization and using this study:

Circular pattern, where a1 is the radii of the inner circular contact; a2 is

the radii of the outer region; and d is the difference between a1 and a2.

For equal sheet resistances(sh) under the metal and in gap, and for circular TLM

(CTML), the total resistance between the internal and external contacts is [2.7]

1

2

21

20

211

10

1

ln2 a

a

LaK

LaK

a

L

LaI

LaI

a

LR

T

TT

T

TTshT

(2.5)

where I and K denote the modified Bessel function of the first order, and LT is transfer

length. LT is related to c of the metal/semiconductor contact and sh of the

semiconductor, as given by

W

l d


26

sh

cTL

(2.6)

For a2 ≫ 4LT, the Bessel function ratios 10 II and 10 KK tend to unity and RT

becomes

1

2

21

ln11

2 a

a

aaLR T

shT

(2.7)

For L ≫ d, Eq. (2.7) simplifies to

CLdL

R Tsh

T 22

(2.8)

where C is the correction factor [2.8]

1

2

12

1 lna

a

aa

aC

(2.9)

It can be seen from Eq. (2.8) that there is a linear relationship between RT and d. Thus,

LT and sh, can be obtained as shown below:

LT = (y-interception /slope) × 2 (2.10)

sh = (Slope) × 2a2 (2.11)

Using Eq. (2.6), Eq. (2.10) and Eq. (2.11), the value of c, can then be obtained:

shTc L 2

(2.12)


27

References

[2.1] S. M. SZE and KWOK K. NG: “PHYSISCS OF SEMICONDUCTOR DEVICS’’,

third edition, WILEY-INTERSCIENCE, p.157-p.176 (2007).

[2.2] Y. Taur and T. H. Ning: “Fundamentals of MODERN VLSI DEVICES,”

Cambridge University Press, p.114 (1998).

[2.3] K. Omote and J. Harada. ”Grazing-incidence x-ray diffractometer for determing

in-plane structure of thin folms,” JCPDS, 43, p.192-p.200 (2000)

[2.4] A. J. Willis and A. P. Botha, “Investigation of ring structures for metal-

semiconductor contact resistance determination,” Thin Solid Films, 146, p.15–p.20

(1987).

[2.5] G. K. Reeves and H. B. Harrison, “Obtaining the Specific Contact Resistance

from Transmission Line Model Measurements,” IEEE Electron Device Letters, 3,

p.111-p.113 (1982).

[2.6] G. S. Marlow and M. B. Das, “The effects of contact size and non-zero metal

resistance on the determination of specific contact resistance,” Solid-State Electronics,

25, p.91-p.94 (1982).

[2.7] S.S. Cohen and G.Sh. Gildenblat, “Metal-Semiconductor Contacts and Devices,”

VLSI Electronics, 13, p.424 (1986).

[2.8] D. Schroder, “Semiconductor Material and Device Characterization,” third

edition, WILEY-INTERSCIENCE, p.144-p.145 (2006).

Chapter 3. Composition and Morphology of Ni-Germanide Films

28

Chapter 3

Composition and Morphology

of Ni-Germanide Films

3 Composition and morphology of Ni-germanide films

3.1 Introduction.....................................................................................29

3.2 Cyclically stacked process..........................................................29-30

3.3 Measurement of Ge film density.....................................................30

3.4 Process of Ni-germanide..................................................................31

3.5 Measurement of sheet resistance...............................................31-32

3.6 XRD analysis of stacked germanide film..................................32-33

3.7 J-V characteristics of stacked germanide diode.......................33-35

3.8 Conclusions.......................................................................................36

References


29

3.1 Introduction

NiGe is promising candidate for use Ge MOSFET devices because of the low

formation temperature, the stable phase over wide temperature range, and low

resistivity [3.1]. One of the issues of NiGe on n-Ge substrates is that NixGey is formed

below 350oC and over 500oC [3.2]. Therefore, the interface roughness is increased due

to reacting between deposited Ni film and Ge substrate. The suppression of interface

reaction is advantageous to obtain flat interface between NiGe and Ge substrates. This

chapter mainly confirms the composition and sheet resistance of NiGe film and

electrical characteristics of NiGe/n-Ge diode.

3.2 Cyclically stacked process

Cyclically stacked process is simple process of obtaining a high-quality NiGe

film. Multi layers of Ni and Ge are formed by RF magnetron sputtering on n-Ge

substrate at room temperature and the average composition of the total multi-layers is

controlled so as to be stoichiometric NiGe [3.3]. Fig. 3.1 shows scheme of cyclically

stacked for NiGe film.

Fig. 3.1 Schemes of cyclic deposition


30

In this process, Ni films react only with Ge films deposited on the Ge substrate.

Therefore the reaction between Ni and Ge substrate can be avoid, and smooth interface

roughness is obtained.

3.3 Measurement of Ge film density

Density of Ge film deposited by RF magnetron sputtering is measured via x-

ray reflectivity (XRR). Density of Ge single crystal is 5.32g/cm3 at 25oC [3.4],

however density of Ge film in this study is 4.78g/cm3. XRR spectrum (blue line) and

simulation(red line) of Ge film is shown in Fig. 3.2. Thus, in this study thickness of

Ge film is 1.30nm which determined rationally as same number of Ni atoms per 0.5nm-

thick Ni film although the values of Ni/Ge layers thickness correspond to atomic

concentration of 1 to 1 are 0.50nm and 1.04nm, respectively. Measured low Ge density

has been attributed to low ionization rate in plasma.

Fig.3.2 XRR spectrum (blue line) and simulation (red line) of Ge film as deposited.


31

3.4 Process of Ni-germanide

The wafers used in this study were n-type Ge(100) with a doping density of

4.0×1016cm-3. A set of Ni/Ge(0.5nm/1.3nm) which was cyclically stacked for 8 times

was deposited by RF magnetron sputtering system after HF treatment of the substrates

as shown Fig. 3.3. The values of Ni/Ge layers thickness correspond to atomic

concentration of 1 to 1. The concept of this process is to suppress the interface reaction

between Ni and Ge substrate by Ge deposition in addition to Ni.

Fig. 3.3 Schemes for Ni-germanide process

of sputtered cyclic deposition of Ni/Ge layers.

3.5 Measurement of sheet resistance

The deposited films on Ge substrate were annealed in nitrogen (N2) gas at

annealing temperature ranging from 200 to 500oC for 1 minute. Fig. 3.4 shows sheet

resistance (sh) of the films on annealing temperature. For the sample with 3.0-nm-

thick Ni layer, sh showed a large decrease from 200oC to nearly 300oC, which is

attributed to the formation of NiGe phase. When the annealing temperature is over

350oC, the sh showed a large increase due to agglomeration of the germanides. For

the sample with 5.5-nm-thick Ni layer, temperature range of NiGe phase is wider than


32

3.0-nm-thick Ni layer. On the other hand, for the sample with cyclically stacked and

formed NiGe, a gradual reduction in the sh was observed over 250oC, and the value

became stable at annealing temperatures from 275oC to nearly 500oC, which gives

process compatibility for dopant activation in Ge devices. From 200 up to 250oC, it

would appeared that NixGey phase is formed.

Fig. 3.4 Annealing-temperature dependence of sheet resistance

of stacked NiGe on Ge substrate.

3.6 XRD analysis of stacked germanide film

The x-ray diffraction spectrum of NiGe on Ge substrates were analyzed by

XRD. The peaks of NiGe plane direction of the sample annealed at 400oC is shown in

Fig. 3.5. NiGe phase was formed with strong peaks obtained for NiGe(111) and (121)


33

planes[3.5].

Fig. 3.5 In-plane XRD profile of stacked NiGe annealed at 400oC.

3.7 J-V characteristics of stacked germanide diode

Fig. 3.6 shows the fabrication flow of Schottky diodes. Schottky diodes were

fabricated on HF-last n-type Ge(100) substrates with doping density of 4.0×1016 cm-3.

The surface contact metals were sputtered as shown in fig. 3.3. After lift-off process,

an Al film was formed as a backside contact using vacuum evaporation.


34

Fig. 3.6 Experimental procedure of Schottky diode process

Fig.3.7 shows current-voltage characteristics of the stacked NiGe at various

annealing temperature from 200 to 600oC. Schottky diode characteristics have been

observed, definitely. And Bn and n-factor of NiGe/n-Ge and 5.5-nm-thick Ni films on

n-Ge substrates were extracted from J-V characteristics of the Schottky diodes on

various annealing temperature as shown in fig. 3.8. Here, thermionic emission model

was used for the extraction with the effective Richardson constant A* was 133 A/cm2K2

in this study.

The Bn that determined for NiGe formed on Ni 5.5-nm-film and stacked

NiGe annealed up to 600C were within 0.54~0.57 eV and 0.53~0.55 eV, respectively.

The ideality factor of NiGe showed values of less than 1.3. Meanwhile, owing to

thermal stability of NiGe films, ideality factor lower than 1.2 could be maintained up

to 500oC, but the ideality factor were slightly increased at 600oC.


35

Fig. 3.7 J-V characteristics of the stacked-germanide diodes.

Fig. 3.8 (a) Bn and (b) ideality factors of Ge Schottky diodes

with stacked NiGe and 5.5-nm-thick Ni film.


36

3.8 Conclusions

NiGe with cycles of Ni/Ge stacked films on n-Ge substrate showed stable

sheet resistance in the temperature range from 275oC to nearly 500oC. This

temperature range is wider than the corresponding temperature range obtained for

NiGe formed on Ni 3.0- and 5.5-nm-thick films. The Bn determined for Ge Schottky

diode with stacked NiGe exhibit stable values within approximately 0.54eV even after

annealing at temperature up to 600 oC. Furthermore, the ideality factors of this diode

indicated less than 1.2 even after annealing at temperature up to 500oC. Cyclically

stacked process is confirmed to form stable NiGe phase.


37

References

[3.1] S.Gaudet, C.Detavetnier, A.J.Kellock, P.Desjardins, and C.Lavoie. “Thin film

reaction of transition metals with germanium,” Journal of Vacuum Science &

Technology A 24, 474 (2006)

[3.2] M.Mueller, Q.T.Zhao, C.Urban, C.Sandow, D.Buca, S.Lenk, S.Esteves, and

S.Mantl. “Schottky barrier height tuning of NiGe/n-Ge contacts using As and P

segregation,” Material Science and Enginnering B 154-155 (2008) 168-171

[3.3] A.Ishizaka and Y.Shirali, “Solid-phase epitaxy of NiSi2 layer on Si(111) substrate

from Si/Ni multi-layer structure prepared by molecular beam deposition,” Surface

Science, 174, p.671-p.677 (1986).

[3.4] C.Claeys, E.Simon. “GERMANIUM-BASED TECHNOLOGIES FROM

MATERIALS TO DEVICES,” p.23 (2007)

[3.5] S.L.Liew, R.T.P.Lee, K.Y.Lee, B.Balakrisnan, S.Y.Chow, M.Y.Lai, and D.Z.Chi.

“Enhances morphological stability of NiGe films formed using Ni(Zr) alloy,” Thin

Solid Films 504 (2006) 104-107.

Chapter 4. Schottky Barrier Height Lowering with Dopant Incorporation

38

Chapter 4

Schottky Barrier Height

Lowering with

Dopant Incorporation

4 Schottky Barrier Height Lowering with Dopant

Incorporation

4.1 Effect of P atoms incorporation.................................................39-42

4.2 Extraction of contact resistance on Ni3P/n-Ge diode....................42

4.3 Extraction of Schottky barrier height on Ni3P/n-Ge diode.....43-44

4.4 Incorporation P atoms for NiGe/n-Ge diode..................................45

4.5 Measurement of J-V characteristics...............................................45

4.6 Observation of cross-sectional surface...........................................47

4.7 Discussion and Conclusions.......................................................48-49

References


39

4.1 Effect of P atoms incorporation

Fig. 4.1 shows schematic illustration of deposited 22nm-thick-Ni and 30nm-

thick-Ni3P films on n-Ge substrate. The 22-nm-thick-Ni corresponded to the same Ni

atomic concentration of a 30-nm-thick-Ni3P. An Al film was formed as a backside

contact using vacuum evaporation after resist was eliminated.

Fig. 4.1 Schematic illustration of deposited 22nm-thick-Ni

and 30nm-thick-Ni3P on n-Ge substrate.

Next, J-V characteristics have been measured to extract Bn and ideality factor

using TFE model as shown in Fig.4.2. The stable Bn of Ni/n-Ge diode has been

observed. While at the same time, Bn of Ni3P/n-Ge diode have been gradually

decreased and lowest Bn value at 600oC has been appeared in Fig. 4.2(a). Ideality

factor of Ni/n-Ge diode has been gradually increased, however ideality factor is

observed to drop to below 1.5. Also, ideality factor of Ni3P/n-Ge diode is not posted

on Fig. 4.2(b) since Ni3P/n-Ge diode is completely out of touch with the ideal Schottky

diode.


40

Fig. 4.2 (a)Bn and (b)ideality factor of Ge Schottky diodes

with stacked 30nm-thick-Ni3P and 22nm-thick-Ni films

J-V characteristics of Ni and Ni3P/n-Ge diode at 600oC is extracted in Fig.4.3. Ni3P/n-

Ge diode shows Ohmic characteristics by effect of P incorporation whereas Ni/n-Ge

diode shows typically Schottky diode characteristics. It would appear that P atoms

penetrate into n-Ge substrate and part of shallow n-Ge substrate is heavily doped by P

atoms.


41

Fig. 4.3 J-V characteristics of Ni and Ni3P/n-Ge diode

on (a)logarithmic model and (b)linear model.

And here is SEM image of Ni3P(30nm)/n-Ge contact at (a)as-depo and

(b)600oC annealing as shown in Fig. 4.4.

Fig.4.4 SEM image of Ni3P/n-Ge contact at (a)as-depo and (b)600oC annealing.

SEM image shows regular thickness of Ni3P at (a)as-depo and large roughness due to

Ni3P/n-Ge reaction at (b)600oC annealing. The Ni3P/n-Ge diode shows Ohmic


42

characteristic at 600oC due to that large roughness and heavily doped state. In fact,

electrons can pass easier than before annealing.

4.2 Extraction of contact resistance on Ni3P/n-Ge diode

Electrical characterization of Ni3P on n-Ge substrate was performed with

CTLM with proper correction factor. Fig. 4.5 shows current-voltage characteristics of

Ni3P electrode at 600oC annealing. The extracted specific contact resistance (c) is

6.5x10-3cm2. Considering the doping density of 1016cm-3, the obtained value can be

understand either by extreme shallow doping of P atoms at surface of Ge substrate or

by Schottky barrier height modulation.

Fig. 4.5 Current-voltage characteristics of CTLM pattern


43

4.3 Extraction of Schottky barrier height on Ni3P/n-Ge diode

The c, is determined by field emission (FE) and thermionic-field emission

(TFE), in addition to the standard thermionic emission (TE). The most widely accepted

model for FE and TFE is given by Padovani and Stratton [4.1, 4.2] and is used in this

work. Yu had utilized this theory to calculate c [4.3] but the tunneling effective mass

used was only a variable, rather than a real value (the tunneling effective mass is

important since the tunneling probability is exponential with mass). There is a useful

term E00 defined as

sm

NqE

200

(4.1)

where m* is the effective mass, N is the doping level, and s is the permittivity. In this

work, 𝐸00 ≈ｋ𝑇 based on E00 = 1.74×10-22 J. Hence, in the medium doping regime,

TFE dominates, and

kT

E

kT

E

qTqA

Ek

nBn

c000000

cothcosh

kT

q

kTEE

q nnBn

0000 cothexp

(4.2)

where A* is the effective Richardson constant. In this work, A* = 133 A/cm2K2. In the

case that Nd = 4.0×1016 cm-3, calculated c as (2.7) at various Bn were shown in fig.

4.6. In the situation that c = 6.5×10-3cm2 as Fig. 4.6, Bn = 0.40eV (red line). This


44

indicates lowering Bn for compared to Bn = 0.54eV of Ni/n-Ge diodes without

incorporation as shown in fig.4.2(a).

Fig. 4.6 Calculated contact resistance on doping density

at various Schottky barrier heights.

If donor impurity density is increased by influence of Ni3P, c = 6.5×10-3cm2 as fig.

4.6 meets Bn = 0.45eV (blue line) and 0.50eV (brown line). Using Ni3P instead of Ni,

there is a possibility that doping density will be increased.


45

4.4 Incorporation P atoms for NiGe/n-Ge diode

As I discussed in the preceding section, Ni3P has possibilities for Ohmic

contact. In this section, the sample which contains Ni3P in cyclically deposited NiGe

is investigated. Fig. 4.7 shows schematic illustration of inserting P at the

germanide/substrate interface of the sample. In P case, a 0.68-nm-thick-Ni3P layer was

deposited instead of the first Ni layer. The 0.68-nm-thick-Ni3P corresponded to the

same Ni atomic concentration of a 0.5-nm-thick-Ni. An Al film was formed as a

backside contact using vacuum evaporation after resist was eliminated.

Fig. 4.7 P incorporation scheme for stacked-germanide process.

4.5 Measurement of J-V characteristics

J-V characteristics has been investigated and extracted Bn. Bn of NiGe with

Ni3P (NiGe:P) has been decreased according to annealing temperature although Bn of

NiGe has stabilized as shown in Fig. 4.8. Lowest Bn of NiGe:P shows 0.51eV at 500oC.

However Schottky characteristics has been observed despite P atoms incorporation (in

Fig. 4.9).


46

Fig. 4.8 Bn of Ge Schottky diodes with stacked NiGe:P and stacked NiGe.

Fig. 4.9 J-V characteristics of stacked germanide

with P incorporation annealed at 400oC and 500oC.

Effective Bn shift by P incorporation with stacked germanidation process.


47

4.6 Observation of cross-sectional surface

As shown in Fig. 4. 10, TEM images of germanide/n-Ge interface formed

NiGe after annealing at 500oC for 1 min in N2 ambient to form NiGe. TEM images

revealed the formation of approximately 8nm-thick stacked germanide, flat interface

and surface at 500oC because consumption of Ge from substrate is limited to the first

Ni3P layer. Stripes have been observed in right TEM image especially because light

reflected from crystal structure has created an interference pattern of light.

Fig. 4.10 TEM image of stacked germanidation process with P atoms

at 500oC annealing.


48

4.7 Discussion and Conclusions

From electrical characteristics, NiGe:P/n-Ge diode has showed Schottky

characteristics although Schottky barrier height of NiGe:P/n-Ge diode has been

alleviated by P atoms incorporation. On the other hand, NiSi2:P/n-Ge diode has

showed Ohmic characteristics [4.4]. Fig.4.11 and 4.12 shows J-V characteristics, TEM

image, and EDX analysis of NiSi2:P/n-Ge diode. A NiSi2 electrode with P atom

incorporation to obtain Ohmic characteristics on n-Ge has been performed as shown

in Fig.4 11. And Ohmic contact with resistance less than 10-2 cm2 has been achieved

with low temperature process as low as 300oC.

Fig. 4.11 J-V characteristics of the stacked-silicide diodes with P incorporation

[4.4].


49

Fig. 4.12 TEM image and EDX spectrum of the bright layer

at NiSi2/Ge interface [4.4].

The one of difference between NiGe and NiSi2 electrode is interface layer which is

formed by NiSi2 film/n-Ge substrate-reaction. As shown in Fig. 4.12, at the bright thin

layer of NiSi2/n-Ge interface, the EDX detected P in addition to Ge, Si, and Ni. Those

indicate that the bright thin layer is mixing layer of Ni, Si, P and Ge. The mixing layer

which is formed involuntarily has affected to decrease Schottky barrier height

effectively. In fact, insertion layer at NiGe/n-Ge interface is necessary to obtain Ohmic

characteristics using NiGe electrode.

0 2 4 6 8 100

50

100

150

200

250

300

Energy (keV)

Cou

nts

C

O

Ni

Ge Si

P Ar

Ni

Ni

Ge10nmGe sub.

500oC

NiSi2


50

References

[4.1] F. A. Padovani and R. Stratton, “Field and thermionic-field emission in Schottky

barriers,” Solid-State Electronics, 9, p.695-p.707 (1966).

[4.2] F. A. Padovani, “The voltage–current characteristic of metal–semiconductor

contacts,” Semiconductors and semimetals, 7, p.75-p.146 (1971).

[4.3] A. Y. C. Yu, “Electron tunneling and contact resistance of metal-silicon contact

barriers,” Solid-State Electronic, 13, p.239-p.247 (1970).

[4.4] R.Yoshihara. “Interface control process toward un-pinned metal/germanium

Schottky contact,” Master thesis, Tokyo Institute of Technology (2014)

Chapter 5. Thin Film Insertion into Metal/n-Ge Interface

51

Chapter 5

Thin Film Insertion

into Metal/n-Ge Interface

5 Thin Film Insertion into Metal/n-Ge Interface

5.1 Si film insertion................................................................................52

5.2 Measurement of J-V characteristics.........................................52-54

5.3 Dependence of Si thickness........................................................54-56

5.4 Extraction of contact resistance................................................56-57

5.5 Extraction of Schottky barrier height......................................57-59

5.6 Discussions..................................................................................60-62

5.7 Conclusions.......................................................................................63

References


52

5.1 Si film insertion

As described in the last chapter, effect of P atoms incorporation is observed

although NiGe:P/n-Ge diode does not show Ohmic characteristics. And so effect of Si

film insertion and dependence of Si thickness are discussed in this chapter. Fig. 5.1

shows schematic illustration of inserting Si film at the germanide/substrate interface

of the sample. In Si case, x = 0.1, 0.3, 0.6, and 1.0-nm-thick-Si layer was deposited in

addition to first Ni or Ni3P layer. The 0.68-nm-thick-Ni3P corresponded to the same Ni

atomic concentration of a 0.5-nm-thick-Ni along with Chapter. 4. An Al film was

formed as a backside contact using vacuum evaporation after resist was eliminated.

Fig. 5.1 Si incorporation scheme for stacked-germanide process.

5.2 Measurement of J-V characteristics

Particularly favorable J-V characteristics at 400oC has been extracted as

shown in Fig. 5.2. In 0.1nm-thick-Si layer insertion case, reverse current has been

increased in the presence or absence of P atoms incorporation. Specially, NiGe:P,


53

Si(0.1nm)/n-Ge diode shows Ohmic characteristics among various Si thickness.

Outside 0.1nm-thick-Si layer case, reverse current has no connection with thickness of

Si layer.

Fig. 5.2 J-V characteristics of the stacked-germanide diodes includes various

thickness of Si layer (a)without and (b)with P atoms incorporation.

And J-V characteristics of the Schottky diodes on various annealing temperature were

extracted Bn as shown in Fig. 5.3. Here, thermionic emission model was used for the

extraction with the effective Richardson constant A* was 133 A/cm2K2 in this study

along with chapter 4. Bn has been modulated by insertion of thin Si films with

annealing temperature from 200oC to 600oC as a parameter. The Bn modulation occurs

in the presence or absence of P atoms incorporation in that 0.1nm-thick Si layer

insertion of case. In Fig. 5.3(a)without P case, slightly Bn modulation has been

observed with various Si thickness outside 0.1nm-thick-Si layer, however in Fig.5.3


54

(b)with P case, 0.3nm-thick Si layer modulate Bn significantly in addition to 0.1nm-

thick Si layer.

Fig. 5.3 Bn of the stacked-germanide diodes includes various thickness of Si layer

(a)without and (b)with P atoms incorporation.

5.3 Dependence of Si thickness

Fig. 5.4 exhibits a relationship between Bn and thickness of Si layer which

is extracted (a)300oC, (b)400oC, and (c)500oC annealing. From 300oC up to 400oC, Bn

has been decreased by P atoms incorporation and thin Si films(0.1 and 0.3nm) insertion.

And Bn has been increased at 500oC annealing compared with 400oC annealing.

However, in thick Si films(0.6 and 1.0nm) insertion, there is rarely different whether

P atoms incorporation or not.


55

Fig. 5.4 Relationship between Bn and Si thickness at various annealing temperature.

Because it would appear that P atoms cannot penetrate the n-Ge substrate when Si film

is thick as shown in Fig. 5.5. Thus effect of P atoms incorporation does not appear. As

a result, thin (0.1 and 0.3nm) Si films insertion case, Fermi-level has been de-pinned

by both effect of P atoms incorporation and Si layer insertion.


56

Fig. 5.5 P atoms diffusion to substrate change dependent on Si thickness

5.4 Extraction of contact resistance

Electrical characterization of NiGe:P,Si(0.1nm) on n-Ge substrate was

performed with CTLM with proper correction factor. Fig. 5.6 shows current-voltage

characteristics of NiGe:P,Si(0.1nm) electrode at 400oC annealing. The extracted

specific contact resistance (c) is 3.7x10-3cm2. This Ohmic contact characteristics

and c have attributed to increased doping density by P atoms incorporation.


57

Fig. 5.6 Current-voltage characteristics of CTLM pattern.

5.5 Extraction of Schottky barrier height

Electrical characterization of P-incorporated and 0.1nm-Si-film-inserted

NiGe on n-Ge substrate was performed with CTLM method. Then the measured c is

3.7×10-3cm2. With reference to the measured c, Fig. 5.7 shows relationship between

c and Bn with various Nd. In the situation that Nd = 4.0x1016cm-3 (black line), Bn is

0.38eV. However, when Nd is increased by P atoms incorporation, for exsample, Bn

becomes altered at 0.39eV (blue line) and 0.42eV (red line) in Fig. 5.7.


58

Fig. 5.7 Calculated contact resistance on Schottky barrier heights at various Nd.

According to research of NiSi2:P/n-Ge diode [5.1], concentration distribution of

incorporated P were examined at 500oC annealing with backside SIMS measurement

as shown in Fig. 5.8. It showed that incorporated P atoms diffused to the n-Ge substrate

and NiSi2 electrode and remained NiSi2/n-Ge interface owing to thermal annealing.

Therefore, in NiGe:P/n-Ge case, it is believed that diffused P atoms were in the same

range. So that means that Nd has reached 1018cm-3.


59

Fig. 5.8 Incorporated P profiles of backside SIMS measured

with 500oC annealing [5.1]

As a consequence, Bn is 0.42eV (red line) in Fig. 5.7 by the thought of Nd has reached

1018cm-3. Schottky barrier height has had a 0.13eV reduced compared with Schottky

barrier height of NiGe/n-Ge diode as argued in chapter. 4.


60

5.6 Discussion

As discussed in the previous section, effect of P atoms and Si layer insertion

have caused Ohmic characteristic. In this section, concept regarding the cause of the

Ohmic characteristic is considered.

The energy band diagram of a NiGe with P atoms and Si layer insertion is

demonstrated in Fig. 5.9. Before contact, the Fermi level in n-Ge and Si was above

that in the pure NiGe in Fig. 5.9(a) (red line). After contact, the Fermi level becomes

contact throughout the system in equilibrium, and the vacuum band energies must be

bended because of its continuous characteristic. Then, the work function of NiGe was

decreased by Si, because the Si has lower work function as shown in Fig. 5.9(b). Also,

at shallow n-Ge substrate, energy band has been bended due to heavily doped by

diffused P atoms. Therefore, Schottky barrier height can be reduced for electrons in

appearance and Ohmic characteristic has been observed.


61

Fig. 5.9 Energy band diagram of NiGe with P atoms and Si layer insertion

(a)before contact, (b)after contact, (i)NiGe/n-Ge diode, (ii) NiGe/n-Ge diode with

Patoms, and (iii) NiGe/n-Ge diode with P atoms and Si layer [5.2]

Next, as noted in the chapter. 1, thin interfacial layer effectively released

Fermi level pinning and achieved Ohmic contact with low Schottky barrier height.

However in this study, when Ohmic characteristic was achieved deposited Si thickness

was 0.1nm. The diameter of Si atom is approximately 0.1nm, in fact, Si monolayer has

been deposited. Therefore in this case, metal induced gap states (MIGS) model is

questionable because Si monolayer is inadequacy presumably to block wave function

of metal which penetrated into n-Ge substrate [5.3]. Consequently, according to dipole

theory, Fermi level pinning has been caused due to dipole layer by large amount of

interface states. Density of interface states (Dit) which existed at NiGe/n-Ge interface

is calculated according to the following equations [5.4]:

𝑆𝐺𝑒 =1

1+0.1(𝜀𝐺𝑒−1)2 (5.1)

𝐷𝑖𝑡 = 1.1 × 1013 ×1−𝑆𝐺𝑒

𝑆𝐺𝑒 (5.2)


62

where S is the empirical pinning parameter describing the screening by the interfacial

states, is the dielectric constant of the Ge, Dit is interface state density. For S=0 and

1 regain the Bardeen and Schottky limits, respectively. According to above equations,

SGe is 0.04 and Dit is 2.64x1014states/cm2/eV where is 16.0. In this study, it would

appear that such a large modulation of Schottky barrier height due to insertion of

0.1nm-thick Si mono-layer is explainable by considering that Si atoms can work as a

valence mending adsorbate at NiGe/n-Ge interface and can alleviate the pinning of

Schottky barrier height, probably because of the reduction in the interface states. Any

chemical bonds between NiGe, Si, and n-Ge could change the effective Schottky

barrier height, for example, through the formation of the dipole layers originated from

Si layer (or atoms) at the interface.


63

5.7 Conclusions

A NiGe electrode with P atoms incorporation and Si film insertion for Fermi

level de-pinning has been performed. From electrical characteristics, modulated

Schottky barrier height with P atoms and Si layer has been observed, especially Si

thickness were 0.1nm and 0.3nm. And Ohmic contact with resistance less than 10-

2cm2 has been achieved with low temperature at 400oC when 0.1nm-thick Si layer

has been inserted at interface. On the other hand, extracted Schottky barrier heights on

various thickness of Si layers revealed that thick Si layer has interrupted diffusion P

atoms. Therefore, when Si layer was thick P atoms have not been diffused into Ge

substrate. Thus, both diffused dopant atoms and thin film insertion, such as P and Si

respectively, at metal/n-Ge interfaces are important in order to de-pin Fermi level

effectively. And further research is strongly needed to reveal the detailed mechanism.


64

References

[5.1] R.Yoshihara. “Interface control process toward un-pinned metal/germanium

Schottky contact,” Master thesis, Tokyo Institute of Technology (2014)

[5.2] D.S.Yu, C.H.Wu, C.H.Huang, A.Chin et al., “Fully Silicided NiSi and Germanide

NiGe Dual Gates on SiO2 n- and p-MOSFETs,” IEEE ELECTRON DEVICE

LETTERS, VOL.24, NO.11 p.739-p.741 (2003)

[5.3] M.Kobayashi, A.Kinoshita, K.Saraswatm, H.-S.P.Wong, and Y.Nishi. ”Fermi

level depinning in metal_nGe Schottky junction for metal source_drain Ge metal oxide

semiconductor field effect transistor application,” Journal of Applied Physics 105,

023702

[5.4] T.Nishimura, K.Kita, and A.Toriumi. “Evidence for strong Fermi level pinning

due to matal induced gap states at metal germanium interface,” Applied Physics

Letters 91, 123123(2007)

Chapter 6. Conclusions

65

Chapter 6

Conclusions

Chapter 6. Conclusions

66

NiGe with cycles of Ni/Ge stacked films on Ge substrate showed stable sheet

resistance in the temperature range from nearly 300oC to 500oC. This temperature

range is wider than the corresponding temperature range obtained for NiGe formed on

Ni 3.0- and 5.5-nm-thick films. Bn determined for Ge Schottky diode with cyclically

stacked NiGe exhibit stable values within approximately 0.54eV even after annealing

at temperature up to 500oC. Furthermore, the ideality factors of this diode indicated

less than 1.3 even after annealing at temperature up to 500oC. Modulated Bn has been

observed when P atoms were incorporated at germanide/germanium interface.

Additionally, incorporation of P atoms and insertion of thin Si film at

germanide/germanium interface have effectively changed the diode characteristics to

Ohmic behavior with resistance less than 10-2cm2 at 400oC. The extracted Bn from

contact resistance is 0.42 eV which is lower than 0.54 eV as NiGe/Ge Schottky diode

without P atoms and thin Si film insertion. This indicated electrically lowering Bn due

to band bending by effect of P atoms and Si film insertion and/or Fermi level de-

pinning by formed dipole layer at interface, probably. The above un-pinned process

gives further insights into Fermi level de-pinning and low contact resistance process

as well as interface researches.

Presentations and Acknowledgments

67

Presentations

and

Acknowledgments


68

Presentations

[International Presentations]

[1] Masaaki Motoki, Kuniyuki Kakushima, Yoshinori Kataoka, Akira Nishiyama,

Nobuyuki Sugii, Hitoshi Wakabayashi, Kazuo Tsutsui, Kenji Natori, and Hiroshi

Iwai, “Dependence between sheet resistance and annealing temperature of Ni

germanide formed by multi-layered Ni and Ge films”, WIMNACT 39, Tokyo,

February (2014).

[Domestic Presentations]


Nobuyuki Sugii, Hitoshi Wakabayashi, Kazuo Tsutsui, Kenji Natori, Hiroshi Iwai,

“A low temperature Ohmic contact process for n-type Ge substrate”, 74th JSAP

Autumn Meeting, Doshisya University, September (2013).


Nobuyuki Sugii, Hitoshi Wakabayashi, Kazuo Tsutsui, Kenji Natori, Hiroshi Iwai,

“Dependence between sheet resistance and annealing temperature of Ni

germanide formed by multi-layered Ni and Ge films”, 61th JSAP Spring Meeting,

Aoyama University, March (2014).


69

Acknowledgments

First of all, I would like to express my gratitude to my supervisor Prof. Hiroshi Iwai

for his continuous encouragement and advices for my study. He also gave me many

chances to attend conferences. The experiences are precious for my present and future

life.

I deeply thank to Prof. Yoshinori Kataoka, Prof. Akira Nishiyama, Prof. Nobuyuki

Sugii, Prof, Hitoshi Wakabayashi, Prof. Kazuo Tsutsui, Prof. Kenji Natori, and

associate Prof. Kuniyuki Kakushima for useful advice and great help whenever I met

difficult problem.

I would like to thank Prof. Hiroshi Nohira of Tokyo City University for XRR and

XRD observation.

I also thank research colleagues of Iwai Lab. for their friendship, active many

discussions and many of encouraging words.

I would like to appreciate the support of secretaries, Ms. Nishizawa and Ms.

Matsumoto.

Masaaki Motoki

February, 2015

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