ELCT201: Digital Logic Design Digital Logic De… · Dr. Eng. Ahmed H. Madian 19 Example 1 show how to build a 3- bit synchronous shift register using three positive edge-triggered

ELCT201: Digital Logic

Design Lecture 8

1

Dr. Eng. Rania.Swief e-mail: [email protected]

Dr. Eng. Haitham Omran e-mail: [email protected]

mailto:[email protected]

mailto:[email protected]

Dr. Eng. Ahmed H. Madian 2

Outlines

• Registers

– Structure

– Parallel registers

– Serial registers

– Universal register design


Registers

• FSM is one of the applications that you can use Flipflops on it.

• There are also another applications for Flip-flops like Registers – “Register” is a small amount of storage available on

the CPU whose contents can be accessed more quickly than storage available elsewhere. Typically, this specialized storage is not considered part of the normal memory range for the machine.

– Registers are normally measured by the number of bits they can hold (ex. 8-bits or 32-bits register)

– They have been implemented using individual flip-flops

http://en.wikipedia.org/wiki/Computer_storage

http://en.wikipedia.org/wiki/CPU

http://en.wikipedia.org/wiki/Bit

http://en.wikipedia.org/wiki/Flip-flop_(electronics)




• What’s the main structure of the register

from inside?

• Is there a types of registers?


Registers

An n-bit register consists of a group n flip -

flops capable of storing n bits of binary info.

All Flip-flops are connected to one clock

source

Each flip-flop can store one bit of Info.

Clear signal during normal operation is set

to high

The clear input is useful for clearing all the

content of the register to all 0’s

Problem:Typically don’t want to load every

clock

Solution: use a external signal to

control the operation of the load


D Q

CLK

I0

A0

D Q I1

A1

D Q I2

A2

D Q I3

A3

Load

MUX I0

I1

Y

S

MUX I0

I1

Y

S

MUX I0

I1

Y

S

MUX I0

I1

Y

S

Registers with Parallel Load


Registers with Parallel Load

1

1

0

0

0

1

1

0

0

1


Shift Registers A register capable of shifting its binary information in one or both direction is

called a shift register

A chain of flip-flops in cascade

0 1 0

SI

CLK

Qa

Qb

etc

0

Qa Qb Qc


Shift Registers

• Points to note:

– At every clock pulse, the first flip flop is loaded

with the value of the data in stream

– The data that was in this flip flop is then

loaded into the second and so on.


Serial Vs Parallel A digital system is said to operate in a serial mode when

information is transferred and manipulated one bit at a time

The serial transfer of information from register A to register B

is done with shift registers.

In the parallel mode, information is available from all bits of a

register and all bits can be transferred simultaneously during

one clock pulse

A

B

Parallel serial

11 / 28

Serial Transfer

Shift Register A SI Shift Register B

SO SI

Clock

Shift

Control

Shift

Control

CLK CLK

Clock

CLK


Serial Operations (Addition) Parallel Addition

Serial Addition

FA Co

S 1 0 1 0

0 1 1 1

1 0 0 1 0

1 0 0 1 Shift Reg.

A

Shift Reg.

B

Shift Reg.

Result

CLK

Dr. Ahmed Madain 13

Serial In/Serial Out Shift Registers

Serial-transfer example.

Timing Pulse Shift register A Shift register B Serial output of B

Initial value 1 0 1 1 0 0 1 0 0

After T1 1 1 0 1 1 0 0 1 1

After T2 1 1 1 0 1 1 0 0 0

After T3 0 1 1 1 0 1 1 0 0

After T4 1 0 1 1 1 0 1 1 1

Dr. Ahmed H. Madian 14

Serial In/Parallel Out Shift Registers

Accepts data serially.

Outputs of all stages are available simultaneously.

Q0

CLK

D

C

Q

Q1

D

C

Q

Q2

D

C

Q

Q3

D

C

Q Data input

D

C CLK

Data input

Q0 Q1 Q2 Q3

SRG 4

Logic symbol


Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.

D0

CLK

D

C

Q

D1

D

C

Q

D2

D

C

Q

D3

D

C

Q

Data input

Q0 Q1 Q2 Q3

Serial

data

out

SHIFT/LOAD

SHIFT.Q0 + SHIFT'.D1


Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.

Logic symbol

C CLK

SHIFT/LOAD

D0 D1 D2 D3

SRG 4 Serial data out

Data in

Universal Shift Register

• Question: Design a Universal Shift

Register with the following capabilities: • A clear control to clear the register to 0

• A clock to synchronize the operations

• A shift-right control (associated with serial

in/out)

• A shift-left control (associated with serial in/out)

• A parallel-load control (to parallel load n bits)

• n-parallel output lines

• A control signal to leave register unchanged

Dr. Ahmed H. Madian


Universal Shift Registers

S1 S2 Action

0 0 No Change

0 1 Shift Right

1 0 Shift Left

1 1 Parallel

Load

No Change

Shift Right

Shift Left

Parallel Load

Need a Clear and Clock


Example 1 show how to build a 3- bit synchronous shift register

using three positive edge-triggered D flip-flops and three 4-to-1 multiplexers. To apply a constant (e.g., 0 or 1) at any input, simply write the value of the constant at the input. The shift register has two control inputs Sh1 and Sh0, three data inputs D2, D1, and D0, and three data outputs Q2, Q1, and Q0. Sh1and Sh0 specify the operations of the shift register as shown in the table below. With the rotate left operation (Sh1=1, Sh0=0), all of the bits get shifted one position to the left, and Q0 gets the value of Q2. All operations must occur at the rising edge of the CLK.


Solution

Documents

ELCT201: Digital Logic Design Digital Logic De… · Dr. Eng. Ahmed H. Madian 19 Example 1 show how to build a 3- bit synchronous shift register using three positive edge-triggered