Very Large Scale Integration (VLSI) - GUCeee.guc.edu.eg/Courses/Electronics/ELCT904 Very Large Scale... · Very Large Scale Integration (VLSI) Dr. Ahmed H. Madian [email protected]

Dr. Ahmed H. Madian-VLSI 1

Very Large Scale Integration (VLSI)

Dr. Ahmed H. [email protected]

Lecture 2

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Acknowledgement

This lecture note has been summarized fromlecture note on Introduction to VLSI Design, VLSICircuit Design all over the world. I can’t rememberwhere those slide come from. However, I’d like tothank all professors who create such a good workon those lecture notes. Without those lectures, thisslide can’t be finished.

Dr. Ahmed H. Madian-VLSI

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Circuit simulation

Circuit simulators like Spice numerically solve device models and Kirchoff’s laws to determine time-domain circuit behavior.

Numerical solution allows more sophisticated models, non-functional (table-driven) models, etc.


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Spice MOSFET models

Level 1: basic transistor equations of Section 2.2; not very accurate.

Level 2: more accurate model (effective channel length, etc.).

Level 3: empirical model.

Level 4 (BSIM): efficient empirical model.

New models: level 28 (BSIM2), level 47 (BSIM3).


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Some (by no means all) Spice model parameters

L, W: transistor length width.

KP: transconductance.

GAMMA: body bias factor.

AS, AD: source/drain areas.

CJSW: zero-bias sidewall capacitance.

CGBO: zero-bias gate/bulk overlap

capacitance.



Contents

Design Rules Wiring tracks Latch-up Circuit characterization & performance Resistance estimation Capacitance estimation Inductance estimation Delay estimation

Simple RC model Penfield-Rubenstein Model

Delay minimization techniques Transistor sizing Distributed drivers Large driver

Wiring techniques


Design Rules

Why we need design rules? We can specify the design rules using some

convenient units, e.g., microns but what happens if we want to manufacture the chip using different manufacturers? use an abstract unit, the lambda (), and scale the design

to the appropriate actual dimensions when the chip is to be manufactured.

Each piece of fabrication equipment used in the IC manufacturing process has limited accuracy.

So, we need rules to ensure that the inaccuracy in the fabrication will not result in malfunction IC.


Lambda-based Rules

One lambda (λ)= one half of the “minimum” mask dimension, typically the length of a transistor channel. This can be used to derive design rules and to estimate minimum dimensions of a junction area and perimeter before a transistor has to be laid out.

Lambda Rule (cont.)

Design rules based on single parameter, λ

Simple for the designer

Wide acceptance

Provide feature size independent way of setting out mask

If design rules are obeyed, masks will produce working circuits

Minimum feature size is defined as 2 λ

Used to preserve topological features on a chip

Prevents shorting, opens, contacts from slipping out of area to be contacted



Design Rules

A set of geometrical specifications that dictate the design of the layout masks.

It provides numerical values for minimum dimensions, line spacing, and other geometrical quantities that are derived from the limits of a specific processing line.

This rules must be followed to ensure functional structures on the fabricated chip.

Poly (gate)

Poly (gate)

Sp-p

wp

wp

Wp = min. width of a polysilicon lineSp-p = min. poly-to-poly spacing


Design Rules

Classified into four main types

Min. width to avoid breaks

Min. spacing to avoid shorts

Min. surround

Min. extension

N+

oxideoxideActive

contact

cut

P-substrate

Sa-ac

Poly (gate)

Poly (gate)

Sp-p

wp

wp

N+

oxideoxide

P-substrate


Design Rules

Min. extension to ensure complete overlaps

dpo

Drain-source

short


Design Rules (cont.)

Most foundry allows submission of designs using simpler set of design rules that can be easily scaled to different processes.

These are called “lambda design rules” that has units of µm.

All distance and widths and spacing are written as value = m, where m is scaling multiplier.

for ex.: w =3 , s = 4 If the factory will use technology =0.15 µm

w =0.45 µm, s = 0.6 µm


Design Rules

The masking sequence was established as: P-type substrate

nWell

Active

Poly

pSelect

nSelect

Active contact

Poly contact

Metal1

Via

Metal2

Overglass


DR for N-Wells

Required for pFET

Snw-nw

Wnw-nw

P-substrate

N-Well N-Well

Snw-nw

wnw-nw wnw-nw


DR for Active Areas

Silicon devices are built on active areas of the substrate Wa = min width of active feature

Sa-a = min. edge-to-edge spacing of active mask polygon

Silicon substrate

FOXActive Active

Sa-a

Wa


DR for Doped silicon (n+)

Wa = min width of an active area

sa-n = min. active-to-nSelect spacing

Silicon substrate

FOXActive Active

N+ N+

wa

Sa-n

Sa-n


Silicon substrate

N-well

DR for Doped silicon (P+)

Wa = min width of an active area

sa-p = min. active-to-nSelect spacing

Sa-nw = min. p+ to nWell spacing

FOXActive

wa

Sa-n

Sa-n

P+

P SelectSp-nw

Sp-nw Active

P Select


MOSFETs MOSFET structure exists every time a poly gate line completely

crosses an n+ or p+ region

DRs for poly features are

Wp = min. poly width of a poly line

dpo = min. extension of poly beyond Active

P substrate

N+ N+

Poly L

N+ N+

wp

N+

Sp-p

dpo


DR for Active contact

Active contact is a cut in the oxide that allows the first layer of metal to contact as active n+ or p+ region.

Sa-ac = min. spacing between active and active contact

dac,v = vertical size of the contact

dac,h = horizontal size of the contact

P-substrate

N+

N-well

P+

Active contact

dac,h

dac,v

Sa-ac


DR for Metal1

Metal1 is applied to the wafer after oxide. It is used as interconnect for signals and also for power supply distribution.

Wm1 = min. width of Metal1 line

Sm1-ac = min. spacing from Metal1 to Active Contact

P-substrate

N+

Metal 1

Sm1-ac

wm1


DR Vias and higher level Metals

Vias is a cut in the oxide layers to contact between two metals.

P-substrate

N+

Metal 1

Via

Metal2

Via

metal1

metal2

dv Sv-m2

Sv-m1

Sm2-m2

wm2

Layout Design Rules summary


Layout Design Rules (cont.)

Transistor dimensions are in W/L ratio

NFETs are usually twice the width

PFETs are usually twice the width of NFETs

Holes move more slowly than electrons (must be wider to deliver same current)

Dr. Ahmed H. Madian-VLSI25

Layout example


3-input NAND

VLSI layout library

Dr. Ahmed H. Madian-VLSI27

Layout

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Types of Design Rules

Scalable Design Rules (e.g. SCMOS)

Based on scalable “coarse grid” - (lambda)

Idea: reduce value for each new process, but keep rules the same

Key advantage: portable layout

Key disadvantage: not everything scales the same

Not used in “real life”

Absolute Design Rules

Based on absolute distances (e.g. 0.75µm)

Tuned to a specific process (details usually proprietary)

Complex, especially for deep submicron

Layouts not portable


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SCMOS Design Rules

Intended to be Scalable

Original rules: SCMOS

Submicron: SCMOS-SUBM

Deep Submicron: SCMOS-DEEP

Authoritative Reference: www.mosis.org



Contents

Wiring tracks Latch-up Circuit characterization & performance Resistance estimation Capacitance estimation Inductance estimation Delay estimation

Simple RC model Penfield-Rubenstein Model

Delay minimization techniques Transistor sizing Distributed drivers Large driver

Wiring techniques


Wiring Tracks

A wiring track space required for a wire

4 width, 4 spacing from the neighbor=8

Transistor consumes one wiring track

4

4

4

4


Area Estimation

Estimate Area by Counting wiring tracks

Multiply by 8 (4Width + 4Spacing) to express in

40

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Latch up

Latch up is a condition that can occur in a circuit fabricated in a bulk CMOS technology.

N+ N+ P+ P+

VDDGND

N-well

P

N

P

N

VDD


P-substrate

Latch up Prevention

This could be corrected by: Include an N-well contact every time a pFET is connected to VDD

Include an p-substrate contact every time a NFET is connected to GND

N+ N+ P+ P+

VDDGND

N-well

VDDGND


It’s required to draw the layout of:

Inverter

4 input NAND gate

4 input NOR gate

3 input XOR gate

MUX 2X1 using pass transistor logic

according to the Design rules given in the lecture due date next Saturday.

(use any layout tool (Microwind)submission will be soft copy and hard copy)

Late submissions with reduction 10%.

1st assignment

Documents

Very Large Scale Integration (VLSI) - GUCeee.guc.edu.eg/Courses/Electronics/ELCT904 Very Large Scale... · Very Large Scale Integration (VLSI) Dr. Ahmed H. Madian [email protected]