ELCT201: DIGITAL LOGIC DESIGN · ELCT201: DIGITAL LOGIC DESIGN Prof. Dr. Eng. Tallal El-Shabrawy, [email protected] Dr. Eng. Wassim Alexan, [email protected] Following

ELCT201: DIGITAL LOGIC DESIGN Prof. Dr. Eng. Tallal El-Shabrawy, [email protected]

Dr. Eng. Wassim Alexan, [email protected]

Lecture 10

هــ 1441محرم

Spring 2020

Following the slides of Dr. Ahmed H. Madian

mailto:[email protected]

COURSE OUTLINE

1. Introduction

2. Gate-Level Minimization

3. Combinational Logic

4. Synchronous Sequential Logic

5. Registers and Counters

6. Memories and Programmable Logic

2

LECTURE OUTLINE

• Design Steps of Sequential Circuits • Synthesis with T Flip-Flops

• Synthesis with D Flip-Flops

• Registers • Structure and Definition

• Serial Registers

• Parallel Registers

• Serial Adder

• Universal Shift Register

• Universal Shift Register: Applications

3

DESIGN OF SEQUENTIAL CIRCUITS

4

The procedure of designing synchronous sequential circuits can be summarized in the following points:

1. From the word description and specifications of the desired operation, derive a state diagram of the circuit

2. Assign binary values to the states

3. Obtain the binary-coded state table

4. Choose the type of flip-flop to be used

5. Derive the simplified flip-flop input and output equations

6. Sketch the logic diagram

5

SYNTHESIS WITH 𝑇 FLIP-FLOPS

Example I

Using 𝑇 flip-flops, it is required to design a 3-bit binary counter that can count from 0 to 7 with a step of 1

Solution:

1. From the word description and the required specifications, we sketch the state diagram. Since each state consists of 3 bits, we need 3 flip-flops

6


Example I

7


Example I

2. Next, we derive the state table. The present and next states are known from the state diagram. While the FF inputs are obtained with the help of the 𝑇 FF excitation table or characteristic equation

8


Example I

9


Example I

3. The FF input equations are then simplified using K-maps

𝑇𝐴2 = 𝐴1𝐴0

10


Example I


𝑇𝐴1 = 𝐴0

11


Example I


𝑇𝐴0 = 1

12


Example I

4. Using the simplified Boolean expressions for the inputs and outputs of the FF, we can sketch the logic diagram of this counting circuit

𝑇𝐴2 = 𝐴1𝐴0

𝑇𝐴1 = 𝐴0

𝑇𝐴0 = 1

𝐶𝑙𝑘

𝐴2 𝐴1 𝐴0

1

13

SYNTHESIS WITH 𝐷 FLIP-FLOPS

Example II

Design a FSM that detects 3 or more consecutive ones

Solution:

1. From the word description and the required specifications, we sketch the state diagram

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Example II

• The state diagram is derived by starting with state 𝑆0, the reset state

• If the input is 0, the circuit stays in 𝑆0, but if the input is 1, it goes to state 𝑆1 to indicate that a 1 is detected

• If the next input is 1, the change is to state 𝑆2 to indicate the arrival of two consecutive 1s, but if the input is 0, the state goes back to state 𝑆0

• If more 1s are detected, the circuit stays in 𝑆3

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Example II

• Any 0 input sends the circuit back to 𝑆0

• This way, the circuit stays in 𝑆3 as long as there are 3 or more consecutive 1s received

• Note that the output does not depend on

the input. It only depends on the state!

(which is why the output is inside the state

nodes, not on the arrows)

• If we reach 𝑆3, this means that the circuit

has detected 3 successive 1s

16


Example II

2. Next, we derive the state table

• The present and next states are known from the logic diagram

• The FF inputs are obtained with the help of the 𝐷 FF excitation table or characteristic equation

• The output attains a value of 1 after three successive 1s are detected

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𝑸(𝒕) 𝑸(𝒕 + 𝟏) 𝑫

0 0 0

0 1 1

1 0 0

1 1 1

Example II


The columns for the FF input equations are

exactly the ones for the next state, since we are

using 𝐷 flip-flops!

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Example II


𝐷𝐴 = 𝐴𝑥 + 𝐵𝑥

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Example II


𝐷𝐵 = 𝐴𝑥 + 𝐵′𝑥

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Example II


𝑦 = 𝐴𝐵

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Example II

4. Using the simplified Boolean expressions for the inputs and outputs of the FF, we can sketch the logic diagram of this sequential circuit

𝐷𝐴 = 𝐴𝑥 + 𝐵𝑥, 𝐷𝐵 = 𝐴𝑥 + 𝐵′𝑥, 𝑦 = 𝐴𝐵

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𝐷𝐴 = 𝐴𝑥 + 𝐵𝑥, 𝐷𝐵 = 𝐴𝑥 + 𝐵′𝑥, 𝑦 = 𝐴𝐵

𝑥

𝐴

𝐵

𝐵′

𝑦

REGISTERS

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• A register is a memory element that can be used to store more than a single bit of information

• A register is made up of several flip-flops with common control signals that control the movement of data to and from the registers

• An 𝑛-bit register consists of 𝑛 flip-flops and is capable of storing an 𝑛-bit word

• The main operations on a register are the same as for any storage element, namely: • load or store: input new data into the register

• Read: retrieve the stored data in the register

SERIAL I/P AND O/P REGISTERS

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𝐶𝑙𝑘

𝑆𝑒𝑟𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡

𝑆𝑒𝑟𝑖𝑎𝑙 𝑜𝑢𝑡𝑝𝑢𝑡

𝐼𝑛 𝑄1 𝑄2 𝑄3 𝑄4

= 𝑜𝑢𝑡

𝑡0 1 0 0 0 0

𝑡1 0 1 0 0 0

𝑡2 1 0 1 0 0

𝑡3 1 1 0 1 0

𝑡4 1 1 1 0 1

𝑡5 0 1 1 1 0

𝑡6 0 0 1 1 1

𝑡7 0 0 0 1 1

𝑄1 𝑄2 𝑄3

PARALLEL I/P AND O/P REGISTERS

25 𝐶𝑙𝑘 𝐶𝑙𝑒𝑎𝑟

𝐼3

𝐼2

𝐼1

𝐼0

𝐴3

𝐴2

𝐴1

𝐴0

But what if we do not want to load new

data with every clock cycle? What if we

want to keep the same data in the

register?

• With every positive edge of the clock,

new data is loaded into the register, in a parallel fashion

PARALLEL I/P AND O/P REGISTERS

26 𝐶𝑙𝑘

𝐿𝑜𝑎𝑑

𝐼3

𝐼2

𝐼1

𝐼0

𝐴3

𝐴2

𝐴1

𝐴0

This design allows us to:

1. Either load new

data bits into the

register (Load is 1)

2. Or keep the old

outputs, by

recirculating them

back into the FF

inputs (Load is 0)

SERIAL ADDITION USING REGISTERS

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𝐶𝑙𝑘

𝑆ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙


𝐶𝑙𝑒𝑎𝑟

Circuit implementation

using a FA and a 𝐷 FF


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• Initially, register 𝐴 holds the augend and register 𝐵 holds the addend, while the carry FF is cleared to 0

• The outputs 𝑆𝑂 of 𝐴 and 𝐵 provide a pair of significant bits for the full adder at 𝑥 and 𝑦. Output 𝑄 of the FF provides the input carry at 𝑧

• The 𝑠ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 enables both registers and the carry FF, so that at the next clock pulse, both registers are shifted once to the right, the sum bit from 𝑆 enters the left-most FF of 𝐴, and the output carry is transferred into FF 𝑄

• The 𝑠ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 enables the registers for a number of clock pulses equal to the number of bits in the registers

• For each succeeding clock pulse, a new sum bit is transferred to 𝐴, a new carry is transferred to 𝑄, and both registers are shifted once to the right

• This process continues until the 𝑠ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is disabled


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• Thus, the addition is accomplished by passing each pair of bits together with the previous carry through a single full adder circuit and transferring the sum, one bit at a time, into register 𝐴

• Initially, register 𝐴 and the carry FF are cleared to 0, and then the first number is added from 𝐵

• While 𝐵 is shifted through the full adder, a second number is transferred to it through its serial input

• The second number is then added to the contents of register 𝐴 while a third number is transferred to serially into register 𝐵

• This can be repeated to perform the addition of 2, 3 or more 4-bit numbers and accumulate their sum in register 𝐴 (assuming that register 𝐴 is built of 4 FFs only)


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State table for the full adder implementation using a 𝐽𝐾 FF


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𝐶𝑙𝑘

𝑆ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙



Circuit implementation using a 𝐽𝐾 FF

𝐽𝑄 = 𝑥𝑦

𝐾𝑄 = 𝑥 + 𝑦 ′

𝑆 = 𝑥 ⊕ 𝑦 ⊕ 𝑄

FF input and output equations

UNIVERSAL SHIFT REGISTER

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This is the most general case of a register and has the following capabilities:

1. A clear control to clear the register to 0

2. A Clk input to synchronize the operations

3. A shift-right control to enable the shift-right operation and the serial input and output lines associated with the shift right

4. A shift-left control to enable the shift-left operation and the serial input and output lines associated with the shift left

5. A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer

6. n parallel output lines

7. A control state that leaves the information in the register unchanged


33

𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛 𝑡𝑎𝑏𝑙𝑒

𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝑠0 𝑠1

𝐶𝑙𝑘


𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐼 𝑖𝑛𝑝𝑢𝑡𝑠

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐴 𝑜𝑢𝑡𝑝𝑢𝑡𝑠

𝑀𝑆𝐵_𝑖𝑛 𝐿𝑆𝐵_𝑖𝑛

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𝑠1

4 − 𝑏𝑖𝑡 𝑈𝑛𝑖𝑣𝑒𝑟𝑠𝑎𝑙 𝑆ℎ𝑖𝑓𝑡 𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟

𝑠0

𝐴3 𝐴2 𝐴1 𝐴0

𝐼1 𝐼0 𝐼2 𝐼3

𝐶𝑙𝑘


𝑆𝑒𝑟𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡 𝑓𝑜𝑟

𝑠ℎ𝑖𝑓𝑡 − 𝑙𝑒𝑓𝑡

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐼𝑛𝑝𝑢𝑡𝑠

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝑂𝑢𝑡𝑝𝑢𝑡𝑠


𝑠ℎ𝑖𝑓𝑡 − 𝑟𝑖𝑔ℎ𝑡

35

𝑠1

4 − 𝑏𝑖𝑡 𝑈𝑛𝑖𝑣𝑒𝑟𝑠𝑎𝑙 𝑆ℎ𝑖𝑓𝑡 𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟

𝑠0

𝐴3 𝐴2 𝐴1 𝐴0

𝐼1 𝐼0 𝐼2 𝐼3

𝐶𝑙𝑘



𝑠ℎ𝑖𝑓𝑡 − 𝑙𝑒𝑓𝑡

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐼𝑛𝑝𝑢𝑡𝑠

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝑂𝑢𝑡𝑝𝑢𝑡𝑠


𝑠ℎ𝑖𝑓𝑡 − 𝑟𝑖𝑔ℎ𝑡


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• Each of the four multiplexers has two common selection inputs 𝑠1 and 𝑠0

• Input 0 in each mux is selected when 𝑠0𝑠1 = 00, input 1 is selected when 𝑠0𝑠1 = 01, and similarly for the other two inputs

• The selection inputs control the mode of operation of the shift register, according to the function table

• When 𝑠0𝑠1 = 00, the present value of the register is applied to the 𝐷 inputs of the FF, so that the output recirculates to the input

• The next clock edge transfers into each FF the binary value it held previously, and no change of state occurs


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• When 𝑠0𝑠1 = 01, terminal 1 of the mux inputs has a path to the 𝐷 inputs of the FFs. This causes a shift-right operation, with the serial input transferred into FF 𝐴3

• When 𝑠0𝑠1 = 10, a shift-left operation results, with the other serial input going into FF 𝐴0

• Finally, when 𝑠0𝑠1 = 11, the binary info on the parallel input lines is transferred into the register simultaneously during the next clock cycle

UNIVERSAL SHIFT REGISTER: APPLICATIONS

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• Shift registers are often used to interface digital systems located remotely from each other

• For example, if we need to transmit an 𝑛 −bit message between two distant points, it will be expensive to use 𝑛 lines to transmit the 𝑛 bits in parallel

• It is more economical to use a single line and transmit the message serially, one bit at a time

• The transmitter accepts the 𝑛 −bit message in parallel into a shift register and then transmits the data serially along the common line

UNIVERSAL SHIFT REGISTER: APPLICATIONS

39

• The receiver accepts the message serially into a shift register

• When all 𝑛 bits are received, they can be taken from the outputs of the register in parallel

• Thus, the transmitter performs a parallel-to-serial conversion of the message and the receiver does a serial-to-parallel conversion

Documents

ELCT201: DIGITAL LOGIC DESIGN · ELCT201: DIGITAL LOGIC DESIGN Prof. Dr. Eng. Tallal El-Shabrawy, [email protected] Dr. Eng. Wassim Alexan, [email protected] Following