Dual 3-Channel Analog Multiplexer

HEF4952BDual 3-channel analog multiplexer/demultiplexer with supplementary switches1. General description

The HEF4952B is a dual 3-channel analog multiplexer/demultiplexer with supplementary switches and common select logic. Each switch features three independent inputs/outputs (pins nY0, nY1 and nY2) an input/output nY3 that can be connected to nY2 or VSS and an input/output (nZ) common to nY0, nY1 and nY2. Three digital select inputs (S1, S2 and S3) are common to both switches. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs in excess of VDD.

VSS and VDD are the digital control supply pins.

The HEF4952B is suitable for use over the full industrial (40 C to +85 C) temperature range.

2. Features

Fully static operation 5 V, 10 V, and 15 V parametric ratings Schmitt-trigger action at control inputs Small signal switch Standardized symmetrical output characteristics Operates across the full industrial temperature range 40 C to +85 C Complies with JEDEC standard JESD 13-B

3. Applications

Industrial Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating

4. Ordering information

Rev. 03 16 December 2009 Product data sheet

Table 1. Ordering informationAll types operate from 40 C to +85 C.Type number Package

Name Description VersionHEF4952BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

NXP Semiconductors HEF4952BDual 3-channel analog multiplexer/demultiplexer

5. Functional diagram

Fig 1. Functional diagram

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LOGICLEVEL

CONVERTER

VDD

3-TO-5DECODER

7S1

9S2

10S3

16 1Y0

15 1Z

14 1Y1

12 1Y2

11 1Y3

VEEVSS

VSS

1 2Y0

2 2Z

3 2Y1

5 2Y2

6 2Y3

VSSHEF4952B_3 NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 16 December 2009 2 of 15


Fig 2. Logic diagram

VSS

VSS

1Y0

1Z

1SY0

1Y21SY2

1Y31SY3

1SY4

1Y1S2

S1

S3

1SY1

2Y0

2Z

2SY0

2Y22SY2

2Y3

001aad873

2SY3

2SY4

2Y12SY1

logic levelconverterHEF4952B_3 NXP B.V. 2009. All rights reserved.



6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 3. Pin configuration

HEF4952B

2Y0 1Y0

2Z 1Z

2Y1 1Y1

VEE VDD

2Y2 1Y2

2Y3 1Y3

S1 S3

VSS S2

001aad871

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Table 2. Pin descriptionSymbol Pin DescriptionVEE 4 supply voltage

VSS 8 ground supply voltage

S1, S2, S3 7, 9, 10 select input

1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 16, 14, 12, 11, 1, 3, 5, 6 independent input or output

1Z, 2Z 15, 2 common output or input

VDD 13 supply voltageHEF4952B_3 NXP B.V. 2009. All rights reserved.



7. Functional description

7.1 Function table

[1] H = HIGH voltage level;L = LOW voltage level.

8. Limiting values

[1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Table 3. Function tableInput SwitchS3 S2 S1 nSY0 nSY1 nSY2 nSY3 nSY4L L L open nY1 to nZ open open nY3 to VSSL L H nY0 to nZ open open open nY3 to VSSL H L open open nY2 to nZ open nY3 to VSSL H H nY0 to nZ open nY2 to nZ open nY3 to VSSH L L open nY1 to nZ open nY2 to nY3 open

H L H nY0 to nZ open open nY2 to nY3 open

H H L open open nY2 to nZ nY2 to nY3 open

H H H open open open nY2 to nY3 open

Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).

Symbol Parameter Conditions Min Max UnitVDD supply voltage 0.5 +18 VVEE supply voltage referenced to VDD [1] 18 +0.5 VIIK input clamping current pins Sn;

VI < 0.5 V or VI > VDD + 0.5 V- 10 mA

VI input voltage 0.5 VDD + 0.5 VII/O input/output current - 10 mAIDD supply current - 50 mA

Tstg storage temperature 65 +150 CTamb ambient temperature 40 +85 CPtot total power dissipation Tamb = 40 C to +85 C [2] - 500 mWP power dissipation per output - 100 mWHEF4952B_3 NXP B.V. 2009. All rights reserved.



9. Recommended operating conditions

10. Static characteristics

Table 5. Recommended operating conditionsSymbol Parameter Conditions Min Typ Max UnitVDD supply voltage see Figure 4 5 - 15 V

VEE supply voltage see Figure 4 -15 - 0 V

VI input voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +85 C

Fig 4. Operating area as a function of the supply voltages

VDD VEE (V)0 15105

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5

10

15

VDD VSS(V)

0

operating area

Table 6. Static characteristicsVSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C UnitMin Max Min Max Min Max

II input leakage current

15 V - 0.3 - 0.3 - 1.0 A

IS(OFF) OFF-state leakage current

Y port; per channel; see Figure 5

15 V - - - 200 - - nA

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 A10 V - 40 - 40 - 300 A15 V - 80 - 80 - 600 A

CI input capacitance

Sn inputs - - - - 7.5 - - pFHEF4952B_3 NXP B.V. 2009. All rights reserved.



10.1 Test circuits

10.2 On resistance

10.2.1 On resistance waveform and test circuit

Fig 5. Test circuit for measuring OFF-state leakage current nYn port

IS

001aak653

VO

switch

VSS = VEE

S1 to S3

nZ

Y0VDD or VSS

VDD

nYn

1

2

VI

Table 7. ON resistanceTamb = 25 C; ISW = 200 A; VSS = VEE = 0 V.Symbol Parameter Conditions VDD VEE Typ Max UnitRON ON resistance VI = 0 V; see Figure 6 and Figure 7 10 V 45 150

VI = 2.5 V; see Figure 6 and Figure 7 10 V 65 365 VI = 5.0 V; see Figure 6 and Figure 7 10 V 110 360

RON ON resistance mismatch between channels

VI = 2.5 V; see Figure 6 10 V 10 -

RON = VSW / ISW.

Fig 6. Test circuit for measuring RON

V

001aak654

VI

VSW

ISW

VSS = VEE

S1 to S3

nZVDD or VSS

VDD

nYnHEF4952B_3 NXP B.V. 2009. All rights reserved.



11. Dynamic characteristics

Fig 7. Typical RON as a function of input voltage

VI (V)0 642

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40

80

120

RON()

0

VDD = 10 V

Table 8. Dynamic characteristicsTamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 10.Symbol Parameter Conditions VDD Typ Max UnittPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; VI = 1.0 V;

see Figure 85 V 5 - ns

10 V 3 6 ns

15 V 2 - ns

tPLH LOW to HIGH propagation delay nYn, nZ to nZ, nYn; VI = 1.0 V; see Figure 8

5 V 5 - ns

10 V 3 6 ns

15 V 2 - ns

tPZL OFF-state to LOW propagation delay

Sn to nYn, nZ; VI =VEE; see Figure 9 5 V 125 - ns

10 V 50 100 ns

15 V 35 - ns

tPZH OFF-state to HIGH propagation delay

Sn to nYn, nZ; VI = 1.0 V; see Figure 9 5 V 125 - ns

10 V 50 100 ns

15 V 35 - nsHEF4952B_3 NXP B.V. 2009. All rights reserved.



11.1 Waveforms and test circuit

Measurement points are given in Table 9.

Fig 8. nYn, nZ to nZ, nYn propagation delays

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nYn or nZ input

nZ or nYnoutput

tPLH tPHL

VI

VEE

VM

VM

VO

VEE

Measurement points are given in Table 9.

Fig 9. Enable and disable times

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switch OFF switch ONswitch ON

nYn or nZ outputLOW-to-OFFOFF-to-LOW

nYn or nZ outputHIGH-to-OFFOFF-to-HIGH

Sn input

VO

VO

VEE

VEE

VDD

VSS

VM

tPZL

tPZH

90 %

90 %

10 %

10 %

Table 9. Measurement pointsSupply voltage Input OutputVDD VM VM5 V to 15 V 0.5VDD 0.5VDDHEF4952B_3 NXP B.V. 2009. All rights reserved.



Test data is given in Table 10.Definitions:DUT = Device Under Test.RT = Termination resistance should be equal to output impedance Zo of the pulse generator.CL = Load capacitance including test jig and probe.RL = Load resistance.

Fig 10. Test circuit for measuring switching times

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VI VO

RT CL

RL S1DUTPULSEGENERATOR

tW

VM

VI

VIVDD1.0 V

VSSVEE

open

0 V

negativepulse

VI

0 V

positivepulse

10 %

90 %

90 %

10 %VM

VM

VM

tW

tftf

trtr

Table 10. Test dataInput Load S1 positionnYn, nZ Sn tr, tf VM CL RL tPHL, tPLH tPZH tPZL OtherVI or VEE VDD or VSS 20 ns 0.5VDD 50 pF 10 k VEE VEE 1.0 V VEE

Table 11. Dynamic power dissipation PDPD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.Symbol Parameter VDD Typical formula for PD (W) Where:PD dynamic power

dissipation5 V PD = 1300 fi + (fo CL) VDD2 fi = input frequency in MHz;

fo = output frequency in MHz;CL = output load capacitance in pF;VDD = supply voltage in V;(fo CL) = sum of the outputs.

10 V PD = 6100 fi + (fo CL) VDD215 V PD = 15600 fi + (fo CL) VDD2HEF4952B_3 NXP B.V. 2009. All rights reserved.



11.2 Transfer characteristics

Table 12. Control input characteristicsVSS = VEE = 0 V unless otherwise specified.

Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +85 C UnitMin Max Min Max

VT+ positive-going threshold voltage VDD = 5 V - 2.90 - 3.00 V

VDD = 10 V - 4.37 - 4.50 V

VT negative-going threshold voltage VDD = 5 V 1.03 - 1.00 - VVDD = 10 V 2.10 - 2.00 - V

VH hysteresis voltage VDD = 5 V 0.16 - 0.10 - V

VDD = 10 V 0.11 - 0.10 - VHEF4952B_3 NXP B.V. 2009. All rights reserved.



12. Package outline

X

w M

AA1A2

bp

D

HE

Lp

Q

detail X

E

Z

e

c

L

v M A

(A )3

A

8

9

1

16

y

pin 1 index

UNIT Amax. A1 A2 A3 bp c D(1) E(1) (1)e HE L Lp Q Zywv

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm

inches

1.75 0.250.101.451.25 0.25

0.490.36

0.250.19

10.09.8

4.03.8 1.27

6.25.8

0.70.6

0.70.3 8

0o

o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.00.4

SOT109-1 99-12-2703-02-19 076E07 MS-012

0.069 0.0100.0040.0570.049 0.01

0.0190.014

0.01000.0075

0.390.38

0.160.15 0.05

1.05

0.0410.2440.2280.0280.020

0.0280.0120.01

0.25

0.01 0.0040.0390.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1HEF4952B_3 NXP B.V. 2009. All rights reserved.


Fig 11. Package outline SOT109-1 (SO16)

1. General description2. Features3. Applications4. Ordering information5. Functional diagram6. Pinning information6.1 Pinning6.2 Pin description

7. Functional description7.1 Function table

8. Limiting values9. Recommended operating conditions10. Static characteristics10.1 Test circuits10.2 On resistance10.2.1 On resistance waveform and test circuit

11. Dynamic characteristics11.1 Waveforms and test circuit11.2 Transfer characteristics

12. Package outline13. Revision history14. Legal information14.1 Data sheet status14.2 Definitions14.3 Disclaimers14.4 Trademarks

15. Contact information16. Contents

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Dual 3-Channel Analog Multiplexer