DESIGN-FOR-TEST OF MIXED-SIGNAL INTEGRATED CIRCUITSiie.fing.edu.uy/~mdavid/adjuntos/NICRON2008_1.pdf · Most difficulties for Mixed-signal Test are due to: ♦ accuracy requirements

NICRON, July 2008 Montevideo, Uruguay 1

DESIGN-FOR-TEST OF MIXED-SIGNAL INTEGRATED CIRCUITS

José L. Huertas

Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC)Universidad de Sevilla [email protected]


Outline

IntroductionMain test conceptsTechnology TrendsDesign-for-test: a must for present electronic systems?

Functional Test for Mixed-signal ICsCircuit classes and metricsTest-on-Chip: signal generation & response acquisitionTest & BIST approaches

Structural Test for Mixed-signal ICsConventional structural testIDDQ TechniqueOscillation-based Test (OBT)Reconfiguration-based technique

Emerging solutions for ADC testing


INTRODUCTION


Main steps in ICs realization

STIMULIDECISION

RESPONSE

analog

digital

analog

digital

PASS

FAIL

CUT

Design

Fabrication

Test

Perfect design+

Perfect fabrication process

no test required

yes

IC´s are more and more complex (perfect designsnot assured)

process defects exist with different impact on dif-ferent circuit types

but

test required

test quality?

IDEAL TEST REAL TEST


What does Test mean? Testing (in general) is the process of verifying that an IC meetsthe specs for what it was designed

Testing (alternative) is the process of verifying that the intendedbehavior of an IC is not affected by a defect

Design Mistakes Human Errors Modelling Oversimplifications Design Rules Violations Fabrication Flaws

Process fluctuations, mask misalignment Spot defects Handling & Finishing problems

Operation Damages Ageing Mechanical Breaks Thermal Stress Electrical Influences Environmental Changes

Conception

Operation

Fabrication

General causes for IC fail:


Depending on the product lifetime testing proceduresare different, and have different goals and costs

Test Types

Specification & Design

DesignValidation

PrototypeCharacterization

ProductionTest

Board/In-field

Design Bugs

Fab Defects

Degradation

Monitoring & on-line testDiagnosis

THD < 45dB

2.7V to 5.5V-40 to 120ºC

circuit tester

pass

fail

Cost:

x 1

x 10

x 100 to 1000

x 10000

Validation:nominal specs checkedbench equipment

few IC samples

Characterization:full specs measured (datasheet)bench equipment

significant set of IC samples

Full test Go/No-Go:small set of specs checkedindustrial testerbefore package / after packageapplied to all ICs

MaintenanceOperator


Defects and their effects

Conception

Operation

FabricationFAILUREERRORFAULTDEFECT

Latency Burn-in Operational Life Testing

nonperformance of some action that isexpected or performance of a function in asubnormal quantity or quality.

physical imperfection or flawaffecting a component

electrical impact of a defect at a level ofabstraction (representation of a defect: short,open...)

manifestation of a fault, i.e., deviationfrom accuracy or correctness in a device

VDD

Z

XY

00011110

Z

0 -> 1111 ERROR

XYW0 0 00 0 10 1 00 1 1

SWITCH

1 0 01 0 11 1 01 1 1

00 -> 101 0101

FAILURE

DEFECT

+XY

Z

&W

BAT.

+X Z

Yshort

IC


Yiel & IC Product QualityTest Importance (in general):

ICs are more and more complex (design not fully simulated)

Time-to-Market is conditioned by Test Speed/Quality

Test Cost (test time) is dominating in many Products

Quality Enhancement is driven some Markets

Present Quality Figures decreased (500 ppm ---> 1 ppm)

Real TestPass

Rejec

Test Quality: minimum test escapes

Product Quality: maximum Yield and minimum Defect-level

defect-free+escapes

Manufacturing Yield number of defect free–total manufactured-----------------------------------------------------------------= Defect level– number of escapes

total passed-----------------------------------------------------=


Two Test Approaches

Stimuli Generator

Response InterpreterCUT

The Fabricated Chip Complies Specs

Specification-based Test

There is No Defect Provoking an Error

Defect-oriented Test

Functional Test Structural Test

Structure Unknown!!

Structure Known!!

All I/O relationships of interest must be checked out

It takes long time It requires quite different test stimuli and instruments

Determine all defects Look for a minimal input signals showing up these defects

It takes shorter times It requires simple instrumentation and stimuli

I/O Behavior Defect Effects

VALIDATION TESTPROTOTYPE TESTPRODUCTION TESTIN-FIELD TEST

Test experiment

Typical Digital TestTypical Analog Test


Yield & PQ for Structural TestsProcess Yield:

Referred to the Number of Good Fabricated Circuits

YFFabricated Good–

Fabricated--------------------------------------------------=

Test Yield: Referred to the Number of Correctly Tested Circuits

YTTested Correct–

Tested--------------------------------------------=

IC Product Quality

Design

DfTFeatures

TestApproach

Test EvaluationMethod

ManufacturingEnvironment

TechnologyParameters

The quality level can vary greatly de-pending on the type of failures occur-ring and the type of failures targetedby the test approach

Factors affecting IC Quality:

Some models for Quality Level:

QL Y 1 T–( )=

QL 1 1 T–( ) 1 Y–( )e n 1–( )T–

Y 1 T–( ) 1 Y–( )e n 1–( )T–+-----------------------------------------------------------------------–=

T: Test Coverage=modeled faults detected/modeled faults

Improving quality could mean moreimprovements in test coverage than in

manufacturing yield

Y: Manufacturing Yield= defect-free parts tested/parts tested

n: average of faults per faulty part

relation betweenfaults modeled and yield is needed


Technology Trends

System-on-chip (SoC) designs are increasing

Semiconductor industry is changing: fabless companies growth

emerging failure mechanisms

New Failure and Yield analysis challenges

many agents to have care of IC yield, quality and reliability (IP providers, designers, fabs)

different cores with different modelling, different test requirements and different tester languages

Technology Scaling and the Cost of Test

more to test, less test access (less pin/device): yield losses

increasing metals and circuit complexity lead to reduction of the traceability of signals: more complex monitor structures increasing wafer size and process variations across wafer

manufacturing cost reduces for each technology generation but

tester speeds not growing as chip speeds test cost remains almost constant: test cost will dominate product cost


Design-for-Test: a solution?

Why to enhance Testability?

Decreasing Test Time/Cost

At-Speed Testing

Alleviating Tester Limitations

Reducing External Interfaces

Providing Periodic Re-Testing

Helping Maintenance

Increasing Long-term Quality

How to enhance Testability?

Reducing Defect Probability

Optimizing/simplifying the Test Process

Re-designing the Circuit (or some parts) to support easier measurements

ProvidingTester Functions into Chips (BIST)

Using Circuit Properties to Decrease Test Cost

Re-configuring the Chip to Speed-up the Test or to test other parts

Design-for-Test (DfT): any method of improving the testability of a circuit by design


Most difficulties for Mixed-signal Test are due to:♦ accuracy requirements for measuring analog signals

♦ lack of ”accepted” analog fault models

♦ access issues for embedded components

♦ most class of circuits need specific testing methods

♦ current mixed-signal test requirements exceed available tools and ATEs

♦ lack of a structured test methodology

♦ advanced processes not stable: no good process characterization data

Mixed-signal DfT Challenges

DfT practical trade-offs:

♦ performance impact♦ extra area♦ design impact♦ yield loss♦ availability of tools♦ test time

A DfT scheme can be targeted to:

a) improve fault coverageb) reduce test generation costc) reduce test application timesd) facilitate testing at system levele) improve test quality

Is it possible to move the Test problem on chip?


Mixed-signal Built-in Self Test (BIST)

Techniques

Functional: Measure parameters related to specs

Structural: High fault coverage and predict future yield problems

Requirements:♦ Put some ATE functions into the Chip

On-chip test stimuli generationOn-chip output response analysis (ORA)On-chip BIST controlOption to support production test

♦ Extra Area

Examples:♦ HBIST (functional)♦ MADBIST (functional)♦ OBIST/BISTmaxx (functional &

structural)♦ adcBIST (functional)♦ Ad-hoc BIST schemes (func.&

struc.)

BIST goals:

♦Test mixed-signal IC on digital ATE >>> reduce cost

♦Customised and optimised test♦Test time reduction♦Test the untestable:

- measure performance in embeded ICs- measure IC functions that are faster than

ATE- measure in situ: wafer, board, field

♦Facilitate test program generation


Mixed-signal Systems: An architectural view A diversity of components:

♦ ADC♦ DAC♦ Digital subsystems♦ Analog parts

Filter ADC Digital DAC Filter

Timing

Testing the whole system at once is usually imposible(functional test).

Splitting the system is feasible but requires:♦ A test procedure for every block (functional meas-

urements)♦ System reconfiguration♦ Access to every block♦ Dedicated input signal generation♦ Specific output signal interpretation


Involved Analog Signals


Timing

DigitalTestProcedures

AnalogTestOutputs

AnalogTestInputs

AnalogTestI/O

TimingSignals


Principles of MS-BIST: Straightforward Reconfiguration (SR)


Filter ADC DAC FilterDigitalDigital

Filter ADCDAC FilterDigital DigitalDigitalOutput

DigitalInput


SR examples: HBIST

Ana

log

MU

X

Scan

Reg

iste

r

Out

put D

isab

le

Scan

Reg

iste

r

A/D DSP D/A

Timing

Control Logic

Test Control LogicDigital In

Analog In

Digitized In

Analog Out

Digital Out

Digitized OutTest Access

Test Access

A self-test scheme for a complete A-D-A system with a DSP-core (CODEC/MODEM)

ASC1ASC2

loop

Functional Test

[Ohletz, 91]


SR examples: MADBIST

Digital Processing Unit (DPU)

Oscillator Control

SmoothingFilter

Signal Generator

Anti-Aliasing

ADC

DAC

DAC Control

Analog Output Analog Input

MADBIST structure

BIST scheme for Functional Test

Step 0: Run digital BIST (scan chain) to verify all the digital cir-cuitryStep 1: ADC testing= Signal Gen-erator providing PDM stimulus for ADC testingStep 2: DAC Smoothing filter test = set ADC and Smoothing Filter in its normal mode+ test DAC Step 3: Testing other external analog components: DAC as ana-log signal source and ADC/DSP as Output Response Analyser

[Toner & Roberts, 93]

Additional components:- Test Signal Generator- SwitchesAdditional functionality:- On-chip signal generation- Narrow band filtering in the DPU


The simplest case: Testing an ADC with a DAC

[Ehsanian 1996]:

Applies this scheme to ADC with internal DAC or viceversa

In a chip, the DAC resolution is usually the same than that on the ADC

Then, there is a lack of test resolution

This part of the code must be the same

step width measure

0 1 1 1 0 0 1 0 1 1 0 1

0 1 1 1 0 0 1 0 1

1 0 1

m+n bits

n bits

m bits

Comparator

n+m bitsDAC

n bitsADC

n+m bits

counter


SR Advantages & Drawbacks

Advantages:

♦ The test problem is reduced to handle digital I/O signals (which do not need to besent outside the chip)

♦ Internal resources are used to Test♦ Test interpretation is internal

Drawbacks:

♦ Test accuracy and speed are limited by the accuracy and speed of the on-chipanalog components

♦ Test capabilities are strongly dependent on the digital processing power availableon chip

♦ Only applicable to very specific cases♦ Increase the complexity of the Test ♦ It can impede the parallel test of different components in a SoC (a very recomend-

ed technique to speed-up production test)


Reconfiguration AlternativesPartial Reconfiguration and/or Standardization are preferred:

♦ Partition the System into component blocks (divide-and-conquer). ♦ Provide access to every block (Input/Output). ♦ Test procedures are usually limited to block level.♦ Signals can be externally handled when the highest performance is required.♦ Signals can be internally generated when Test time is a main issue.♦ Many ad-hoc solutions reported.

Partitioning Increasing Accessibility

Accessibility is a property own by nodes that are ei-ther controllable or observable.

A node is controllable if stimuli can be directlyapply to that node.A node is observable if access to it to performa measurement is possible.

Four main strategies:- Multiplexing- Macro-reconfiguration for

by-passing - Analog Scan- Test buses

MixedSignal-BIST


IEEE 1149.4 Test Bus: a multiplexer-based DfT standard which extends the capabilities of the digital 1149.1 Boundary Scan to mixed-signal ICs

AB

MA

BM

CoreCircuit

TBIC

Test Control Circuitry

(Test Bus Interface Circuit)

TAP controllerInstruction register and decoder

Digital Boundary Module(DBM)

Digital I/O pins

Internal analog test bus

Boundary-Scan Path

Test Access Port(TAP)

Analog BoundaryModule (ABM)

AnalogI/O Pins

ControlRegisters

Analog TestAccess Port(ATAP)

{}

}

Accesibility Issue: A Standard Approach


Partitionning and Accessibility (I)A Rationale for Partition:

- Separating Functions with Different

Functionality

- Unifying Test Measurements

- Simplifying Test Application

- Reducing Time & Cost

System

H(s) A/D

4th orderAnti-aliasing

Filter

2nd orderSmoothing

Filter

4th orderAnti-aliasing

Filter

R

RC

VoutVin6th order

SC Bandpass Filter

RDS demodulation System

Design-induced partitioning (examples):

++

-

k

k

k bitADC

k bitDAC

Vin

code[0:n-1]

2k

SHA

SH ++

-

kk bitADC

k bitDAC

2k

SHA

++

-

kk bitADC

k bitDAC

2k

SHA

k k

xi yi

Pipeline A/D Converter


Partitionning and Accessibility (II)

AIB

AOB

AOAI Analog Block

Analog Block

Analog Block

test selection

AO /Analog Block

K

Analog Block

K

Analog Block

KAOB

AI /AIB

test selection

Reconfigured Blocks

multiplexing

by passing

analog scan -+ +

-

a bAnalog Circuit

Shift in Shift out

AI


Access Techniques: Implementation examples (I)

Subcircuit 1mu

mu

Subcircuit 2

mu mu

1

21

2

1 21 2

Output Selection Primary Output

Primary Ouput

Primary Input

PrimaryInput

Mode Selection Test/ Normal

[Fasang88] & [Wagner88]

BA

Control Digital

BA BA

Test_ITest_O

[Shapher91]

Partitioning & Multiplexing

Analog Bus

B

B

CUT PrimaryInput

Primary Output

Test Input

Test Output

C

B

B

B

B

SIn

SI1

SI0

C CASRASRASR

bufferbufferbuffer

[Wey90]Analog Scan

: Vin (controlable)

Vout (observable)

[Soma90]]

Parallel loading, serial passing

Controlability and Observabilitythrough additional control switches


Access Techniques: Implementation examples (II)

Test Stimulus Application

Primary OutputAnalog

BlockAnalog Block

Analog Block

Digital Control

Sw-Opamp

Primary Input

V1 V2#1 #2 (SUT) #3

VT VT VT+,- +,- +,-

Analog OutputAnalog

BlockAnalog Block

Analog Block

Digital Control

Sw-Opamp

Analog Input

V1 V2#1 #3

VT VT VT+,- +,- +,-

#2

Test Data Input

Test Data Output

AIB

TDO

Control & Observation through the main signal path

Vin

Vo

Vin

Vo

Φj 1=

Φk 0= ⎭⎬⎫Vj Vj 1– Vin= = j k<

Vj Vj 1– Vk= = j k>

Vj Φj( )TDI Φj( )Fj Vj 1–( )+=F1 F2 F3

Use of the Sw-Opamp

[Vázquez 96]


FUNCTIONAL TEST FOR MIXED-SIGNAL ICS


Previous questions: What to test? What the needs are?

Functional test : Parameters related to specs standard metrics / standard measurements stimulus generation issues acquisition issues output processing

Structural test: Fault coverage and predict future yield problemsdefect-to-fault mappingfault models & fault simulationsstimulus generation issuesacquisition and response analysis issues

This depends on the kind of Test and the Circuit under test


Circuit/Block Taxonomy & Diversity

Data Converters Time Domain Linearity (INL, DNL) SNR, ENB

Filters Frequency Domain Passband + Rejectionband Phase Distorsion Dynamic Range

Oscillators (PLL´s) Frequency Domain Frequency Stability (Drift, Temperature...)

THD Capture Range, Jitter...

Basic Blocks (Opamps, OTA´s) DC, AC, Transient...

Combining within aComplex IC (even pure-ly Analog) Requires Dif-ferent Techniques !!

Circuit classes: Filters Comparators DAC´s ADC´s PLL´s RF Transceivers


Metrics & Methods: Filters

Filters Gain and Phase Variation within the Passband Passband Edges Location Performance within the Stopband Dynamic Range, Voltage Range, Output Noise Maximum Input Frequency (+Maximum Clock Freq. in SC)

Step Response Time Domain Transformed into frequency

Multitone Frequency Domain Extrapolated using a minimum number

White Noise Frequency Domain


Testing Filters: Concepts

Time-domain

Frequency-domain


Metrics for ADC´s

ADC Parameters: Intrinsic (characterize the ADC, are independent of the input signal):

Gain INL (Integral Non Linearity) DNL (Differential Non Linearity) ENOB (Effective Number of Bits or Resolution) FSR (Full Scale range) Maximum Clock Rate Code Format

Transmission/Performance (characterize the channel in which theADC is embedded):

SNR (Signal-to-Noise Ratio) IM (Intermodulation distorsion) NPR (Noise Power Ratio) SFDR (Spurious-Free Dynamic Range) Input Signal Bandwidth


Static set of metrics

DNL

INL

Missing code

Gain error

Offset error

Static metrics for ADC:Gain error: how different is the slope to 1

Offset: which input value gives code 0

DNL: Differential No-Linearity. Step width -1 LSB

INL: Integral No-Linearity. Sum of previous DNL.

It’s the most spread set of parameters used to characterize ADCs

However, they are more adapted to “slow” ADCs used in control applications.


Dynamic set of metrics

SNR

SFDR

Signal to Noise Ratio: SNR

Spurious Free Dynamic Range: SFDR

Signal to Noise and Distortion Ratio:SNDR: relation of signal power to noise and distortion power.

Effective number of bits:ENOB=(SNDR-1.78)/6.02

Total Harmonic Distortion:

THDk=A22+A3

2+...+Ak2

InterModulation Distortion: IMD

+

+

THD

Frequency

dB

Also: bandwidth, NPR, differential gain and phase, aperture effects,...


Methods for Testing ADC´s (1)

Histogram

FFT

ProcessingINL

DNL

ENOB

N

SNR

A/D

A/D

A/D

Digital FilterA/D

FFTDigital Generator A/DD/A

Full-digital


Methods for Testing ADC´s (2)

Code transition location

Sine-wave fit

Discrete Fourier transform

- servo-loop- ramp histogram- sinewave histogram

- three parameters- four parameters

IEEE Std 1241-2000

Ramp TestInformation on DNL & INL after computer processingRamp slope determined by speed and resolutionRamp has to be generated with a high accuracy

Spectral Analysis (Sinusoid)Spectrum of the digital output sequence calculated through FFT Noise power, SNR, ENOB calculated sequencially

Histogram (Ramp or Sinusoid, Signal with Known Probability Density) Signal sampled at given points---> Measured output codes --> Histogram

(how many times a code appears at the output)Transitions calculated ----> INL, DNL, ENOB

Closed Loop: Servo method


Moving Test on chip: Requirements &Drawbacks

Ramp TestRamp Size = Full Conversion rangeSub-LSB Increments Slope depending on the maximum conversion rateEvery conversion value must be storedRepeated measurements through several ramp periods

Spectral Analysis (Sinusoid)Low-distorsion & Low-noise floor Sinewave GeneratorsComplex Digital Circuitry with Large MemoryRepeated measurements through many signal periods

Histogram (Ramp or Sinusoid, Signal with Known Probability Density) Large memory requeriments Repeated measurements through many signal cycles


Moving Test on chip: Possibilities

Functional test : Demanded by users/costumers standard metrics: reducing the number of parameters to test stimulus generation: relaxing accuracy acquisition issues: simplfying measurements accessibility: isolating blocks

WaveformGenerator

Clock

CUT

DSP

DigitizerWaveform

Counters

Memory


Example: adc-BISTTM [Logic Vision]-n/2 -n/4 0 n/4 n/2

S0 S1 S2 S3

x

y

y=b0+b1x+b2x2+b3x3

SI: Sum of y in an intervalI

b3 S3 S0– 3S2– 3S1+( )1283n4---------=

b14 S3 S0 S2– S1–+( )

n2------------------------------------------------ n2

8-----b3–=

b2 S3 S0– S2– S1+( )16n3------=

b0S3 S0 S2 S1+ + +( )

n--------------------------------------------- n2

12------b2–=

B0 S3 S2 S1 S0+ + +=

B2 S3 S2– S1– S0+=

B1 S3 S2 S1– S0–+=

B3 S3 3S2– 3S1 S0–+=

x=(n/2)coswt y b0 b2n2

8------+⎝ ⎠⎜ ⎟⎛ ⎞

b1n2--- b3

3n3

32---------+⎝ ⎠⎜ ⎟⎛ ⎞

wt( )cos b2n2

8------⎝ ⎠⎜ ⎟⎛ ⎞

2wt( )cos b33n3

32---------⎝ ⎠⎜ ⎟⎛ ⎞

3wt( )cos+ + +=

“DIGITAL” SIGNATURE

Offset 2n---

12---B0

13---B2+⎝ ⎠

⎛ ⎞ 1n---B0≈=

Gain 4n2----- B1

23---B3+⎝ ⎠

⎛ ⎞ 4n2-----B1≈=

2nd harmonicB2

B123---B3+

----------------------B2B1------≈=

3rd harmonic 1

1 32---

B1B3------+

------------------- 23---

B3B1------≈=

Purely digital spec BIST

Just 4 specs (no THD)Functional At-speed test


Example: Histogram-based BIST

CUTD/AGenerator

Test Ck

ExpectedHistogram

Difference CompressEncoder

S&H HistogramGenerator

The idea is to process activity at a node as an histogram, and compare it with an histo-gram of reference. Functional and structural test possible

Histogram of # of codes in each bin

Center value for bin

# co

des i

n bi

ns

CUT Signature

[Frisch & Almy, 97]


Constraints:- High-precission Frequency- High Linearity (ramps)- (Highly) Programmable- Multiple tone Generation- White Noise Generation- No external calibration or trimming- Minimal Area- Small consumption- Idle when not in test mode

On-chip Signal Generation

Available Techniques:- Sinusoidal Oscillators- Relaxation Oscillators- Chaotic Oscillators- Direct Digital Synthesizers- Digital Resonators- Oversampled Synthesizers- FM Generators- Periodic Bit-stream Generators


Generating ramps

Self-calibration scheme [Bernard 01] 15 bit linearity 0.4% slope error

Some ramp generators have been proposed

cascoded current mirror

Adaptative scheme [Provost 03] 15 bit linearity simulated 11 bit measured 0.6% slope error

- require 9-10 calibration cycles

- need a buffer

The idea:

Embeded in an adaptive closed loop


Generating sine-wavesSome proposals:

- Sinusoidal Oscillators- Direct Digital Synthesizers- Digital Resonators- Periodic Bit-stream Generators

The scaling brings the stimulus noise below the modulator noise

100 10 2 104

–100

0

Polar return-to-zero sequence

Coherent sampling

Register length => frequency limitations

Also for ΣΔ ADCs:Use a recirculating bitstream of ΣΔ encoded sine-wave + a simple filter

Use directly the scaled digital bitstream to test ΣΔ modulators


Direct Digital Frequency Synthesis (DDFS)

Regist. Regist. D/A LowpassFilter

ROMF

(tuning word)

φ(n)

2πφ n( )

2L---------------⎝ ⎠⎛ ⎞sin

foscφ n( ) φ n 1–( )–

2πΔtclk-------------------------------------

fclkF

2L-------------= =

Phase Accumulator (L bits)

Requires a lot of area (very large ROM)specially for high resolution & low frequencies

Offers fast switching speedand good frequency resolution (<1 Hz)

A sinus is stored in the ROMThe phase accumulator repeats value every 2L pulses, reading the ROM once and again

[Tierney 71]


Digital Sine-wave Generator: LDI ResonatorsClassical Approach (based on [Turner 92]):

Interpolation

z-1

z-1

z-1

z-1

z-1

Σ−Δ

Σ−ΔFilterLow-pass

Filter

Low-pass

Filter

DAC

Large amount of area

Oversampling Modification [Lu 94]:

Signifficant area reductionEasily extended to multi-tone

LDI res.

LDI resonator Bandpass version [Rebais 04]: Bandpass type


Σ-Δ modulated Stored-pattern Streams

RAMClock DAC AnalogLP Filter

Operational Phase: The RAM is periodically read

AWG

AWG

Initial Phase: A periodical signal is encoded by a Σ−Δ modulator (1-b or m-b) and the sequence is loaded into the RAM

[Dufort 00]


WaveformGenerator

Clock

CUT

DSP

DigitizerWaveform Counters

Memory

Code-basedFrequency-based

On-chip Response Analysis (I)

Others

Signal

Analysis


On-chip Response Analysis (II)

BIST scheme for linear histogram testing of ADCs

ADCanalog input digital output

Triangle-waveSignal Generator

Memory(measured histogram)

Memory(ideal histogram)

ControlUnit

DSPorμ-proc.

OffsetGainDNLINL

[Bernard 01]

DSP

DigitizerWaveform

Frequency-based

CUT OutputAAFilter

ADC

Bandpass Output

Notch Output

Noise Power

Signal Power

Digital Filter

Counters

Memory

Code-based


Sinusoid Analyser: Analysis Principle

Signal under evaluation

DC-level

( ) ∑ ++=k

kk TkABtx )/2sin( φπDC-Level kth-harmonic Amplitude

T

Delay90º

T/k

SquareModulation

x(t)

SQkT(t)

TT

Delay90º

T/kT/k

SquareModulation

x(t)

SQkT(t)

1st-orderΣΔ Mod.

1st-orderΣΔ Mod.

d1k

d2k

Digitalbit-streams

Sigma-DeltaModulation

Analog (on-chip)

1st-orderΣΔ Mod.

1st-orderΣΔ Mod.

d1k

d2k

Digitalbit-streams


Analog (on-chip)Analog (on-chip)

Vázquez05(JETTA)

T

Delay90º

T/k

SquareModulation

x(t)

SQkT(t)

TT

Delay90º

T/kT/k

SquareModulation

x(t)

SQkT(t)

1st-orderΣΔ Mod.

1st-orderΣΔ Mod.

d1k

d2k

Digitalbit-streams


Analog (on-chip)

1st-orderΣΔ Mod.

1st-orderΣΔ Mod.

d1k

d2k

Digitalbit-streams


Analog (on-chip)Analog (on-chip)

counter

DSPRegisters

&Adders

counter

I1k

I2k

BAk

DigitalSignatures

Digital Algorithm

Digital (on- or off-chip)

counter

DSPRegisters

&Adders

counter

I1k

I2k

BAk

DigitalSignatures

Digital Algorithm

Digital (on- or off-chip)Digital (on- or off-chip)

[Vázquez 02,05]


N= Oversampling ratio in the modulator (T/Ts)M= Number of periods of x(t) taken for evaluation

Unknown error termsdue to the quantization

in the modulator, but limited to:

( ) 42,1 ≤kε

Unknown error termsdue to the quantization

in the modulator, but limited to:

( ) 42,1 ≤kε

{ }

( ) ( ) ( ){ }⎥⎦

⎤⎢⎣

⎡+++⎟

⎠⎞

⎜⎝⎛∈

⎥⎦

⎤⎢⎣

⎡+∈

222

211

22

0)2,1(0)2,1(

maxmin1

2

maxmin1

kkkkk IIMN

A

IMN

B

εεπ

ε

* Values are normalized w.r.t. the full scale range of the Sigma-Delta modulator.

The targeted parameters are extracted from the digital signatures I1k and I2kwith bounded errors:

{ }

( ) ( ) ( ){ }⎥⎦

⎤⎢⎣

⎡+++⎟

⎠⎞

⎜⎝⎛∈

⎥⎦

⎤⎢⎣

⎡+∈

222

211

22

0)2,1(0)2,1(

maxmin1

2

maxmin1

kkkkk IIMN

A

IMN

B

εεπ

ε

* Values are normalized w.r.t. the full scale range of the Sigma-Delta modulator.

The targeted parameters are extracted from the digital signatures I1k and I2kwith bounded errors:

The relative error of the measurements are reduced by increasing the total number of samples (MN).

Θ+=+ MNAII kkk π

222

21

Dependency

Bounded error term

Dig

ital C

ode

Wor

d

A=0.6, fsampling=1MHz, FS=0.7V

Θ+=+ MNAII kkk π

222

21

Dependency

Bounded error term

Dig

ital C

ode

Wor

d

fsampling=1MHz, FS=0.7V, N=144, M=20

Sinusoid Analyser: Evaluation


280u

250u

280u

250u

1st-orderΣΔ Mod. counter

DSPRegisters

&Adders


Delay90º

d1k

d2k

I1k

I2k

BAk

Digitalbit-streams

DigitalSignatures


DSPRegisters

&Adders


Delay90º

d1k

d2k

I1k

I2k

BAk

Digitalbit-streams

DigitalSignatures

Analog Digital

Analog + Digital:0.18mm2

25 Runs per meas Accuracy reachesdB fractions

-11dB Aprox. -31dB Aprox.

-51dB Aprox.

20dB

40dB

20dB

Sinusoid Analyser: Experimental results


On-chip Spectrum Analyser[Méndez-Rivera 04]

DUT

TestCircuitry

Test control

Data

InformationProcessing

Pass/Fail

On-Chip Off-Chip

Extended to high fre-quency using up&down-conversion

Documents

DESIGN-FOR-TEST OF MIXED-SIGNAL INTEGRATED CIRCUITSiie.fing.edu.uy/~mdavid/adjuntos/NICRON2008_1.pdf · Most difficulties for Mixed-signal Test are due to: ♦ accuracy requirements