Debugging Mixed Signal AMS

8/16/2019 Debugging Mixed Signal AMS

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Debugging Techniques for Mixed-SignalAMS Top Level Simulations

Sundaram Sangameswaran, Jasmine Sun, and William Meier

Texas Instruments Inc.March 11, 2015

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Contents

• Brief on AMS UNL (Unified NetLister) Flow

• What is Slowness and Convergence – Multithreading for performance – Better configuration or partitioning

– Modeling Practices

• Debugging Techniques – Analog solver based

• Linter (VerilogAMS/VerilogA)

• Simulation diagnostics (+diagnose)• warnminstep and d2aminstep

– Mixed simulator based• Profiler • Tracing the busy nets and optimization of IEs(CMs)

– Digital simulator based

• Infinite loop in RTL & Gate level code• Case studies

• Conclusions


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AMS UNL (AMS Unified Netlister)

• Cadence AMS team has been working to provide a fully fit-for-purpose AMS Virtuoso Flow that works out-of-the-box enabling a scalable mixedsignal verification solution – Single/Simple technology that works for all customers

– Foundation of our mixed signal capabilities in Virtuoso

• AMS UNL contains important new technologies – Shadow-free Netlisting

– DNA (Dual Netlisting Architecture)

– New Binding Engine (AKA BIND2)

– Pin-checker

– HED –v/-y Support

• Supports all design languages

• Consolidated solution for verimix, CBN/3-step (Eden & ADE) and existing OSSN

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ADE + AMS UNL + irun

courtesy cadence


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ADE: Export for irun command line

4courtesy: cadence


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Slowness and Convergence in AMS

• Slowness or performance degradation

– Bad configuration or partition – Non-use of multi-threading to exploit parallelism

– Bad Modeling practices e.g. in verilog-A/AMS

• Excess amount of time steps

• Excess of step size limiting signals in simulation

• Convergence Issues – Solution convergence failure at some transient time point in the

numerical techniques

– Excess of LTE check failures – Residue convergence failure (KCL)

– Nonlinear discontinuities on models


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Bad Partitioning Practices

Redundant libraries in Lib list

schematic in front in Inh. view list

Digital partitioned as analog

No Unbound cells in RED

Redundant Libraries

Keep analog partition in analog


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Modeling Practices

analog begin

if (V(ps,ns) > 0)

V(p,n)


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Missing Transition w/ cross/above

• Cross/above are better for crossing detections than if/else

• It is safer to specify time/voltage tolerance for cross/above than leave it to simulatordefault. Use of hysteresis value acceptable to the error tolerance of the signal

@(cros s(V(in )-0.62, 0, 1p,0.01));

State = (V(in )>0.62);

• If using above for crossing detection, better to add a +/-delta in case two voltages are the

same .

@(above(V(INP2)-V(INN)-1e-6)) begin

y2 = 1;

end

@(above(V(INN)-V(INP2)+1e-6)) begin

y2 = 0;

end

• If using additional condition inside cross/above statement, unless both conditions are

satisfied, crossing won’t flag; so need to be sure that is what is intended.

@(cross(V(INP2, INN)-minimum, 1)) beginy2 = (V(INP2,AVSS)>0.5);

end

courtesy cadence


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Missing Transition @ A-D boundaries

• This likely to happen when:

– Set all STD. cells inside analog blocks to behavioral views, as a result there are a lot connect elements inserted

– The fastest clock in the design is very fast, e.g. GHz

• By default tr/tf of connect elements are set to 0.2ns; you may need to customize the Connect rule, otherwise,

there may be unexpected sim results such as missing transition

– Few corner simulations

• How to work around it?

– Set d2aminstep, the D-A conversion time step, to be smaller, e.g. 1e-12,

Note: this wil l negatively im pact the simu lat ion perform ance, especial ly if smaller than 2e-15

– At times setting a cmin will also help, will speed up the sim as well, especially if you have thousands+ of connectelements. But these are not recommended for certain designs like charge sharing sensitive designs

• Misc

– Currently there is a UNL bug: if only a slice of a bus in your schematic comes out as pins, module port declaration

will have the full bus not the slice; This will mess up the connection, you may see missing transition because of

this. Please use node breaker for such bus


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Performance Improvements: multi-threading

• Multi-threaded computation on multi-core computer platforms

• Spectre baseline, APS, and XPS SPICE technologies support multi-threaded computation

• APS and XPS SPICE has better multi-threading scaling compared tospectre baseline technology

• When a circuit is too small, the multi-threading option will be turned offautomatically (< 250 analog devices )

• When using APS technology, save currents=all will degrade theperformance

• “mt=, switch defines number of threads for analog solver

• Always pair LSF CPU count with simulator mt count or +mt=lsf

– bsub -n 4 -q regress -R “select[sles11] rusage=1000]” irun +mt=4 – bsub -n 2 irun +mt=lsf -access all

– bsub -n 2 irun +mt=4 -spectre_args “+diagnose” (over utilization of cores)

– bsub -n 4 irun +mt=1 (under utilization of lsf resources)


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AHDL Linter Checks

• Linter feature helps identify complex modeling issues,

could be used in block and SOC simulations

• Checks each line in behavioral model and suggests

– Avoid potential convergence or performance problems

– Improve model accuracy, reusability, and portability• static and dynamic lint checks

– static are performed at compiler stage

– dynamic during simulation for dynamic modeling issues

that may cause convergence or performancedegradation


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AHDL Linter Checks

• Command line use model – irun –spectre_args “-ahdllint=warn -ahdllint_maxwarn=10000”

– irun –spectre_args “-ahdllint -ahdllint_log=ahdllinter.log”

• Environment settings – setenv SPECTRE_DEFAULTS "-ahdllint -ahllint_maxwarn=10“

• Other useful options – -ahdllint_minstep=value , when time step imposed by filter or

function smaller than this value. Default = 1e-12

– -ahdllint_log=file , specify the log file name, default = irun.log


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AHDL Linter Checks

• Examples

– Static AHDL Linter Message• WARNING ( AHDLLINT-5008): "/home/andre/lab_ahdllinter/source/clk_gen.vams", line 26:Detected discrete expression on the right hand side of the a contribution statement. It is

recommended that you apply the transition function on discrete values by specifying the transiton

rise and fall time when the logic of discrete expression value changes

– Dynamic AHDL Linter Message• WARNING ( AHDLLINT-8006): "/home/andre/lab_ahdllinter/source/clk_gen.vams", line 29:

top.10._cds_internal_clock_gen_: Detected signal glitches/pulses in transition expr with pulse

width smaller than tr or tf.

– Suppress Messages• myoptions options warning_limit=0 warning_id=[AHDLLINT-8004 AHDLLINT-8005]

– AHDL help utility

• ahdlhelp 5012 – AHDLLINT-5012: Detected $abstime in an equality expression inside a conditional – example:

if ($abstime==50n) xval=2; – solution:

@(timer(50n)) xval=2;

– Reference: Virtuoso spectre circuit simulation and APS user guide :April 2014


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Simulation Diagnostics:+diagnose option

• IC 6.1.6 ISR8 with incisiv 14.1.x recommended

• If irun.log files shows femto and auto time step sizes, then you haveproblem. Use this option to figure out additional details

• To detect nodes which potentially could lead to convergence issuesor/and performance degradation

• Dump out the node limiting the time step during the simulation run

• log file contains pre and post transient simulation summary withsuggestions for speed up

• Use models – irun -spectre_args “+diagnose”

– ADE: Simulation Options->Additional Arguments field

– ADE: transient Options -> misc tab select annotate=steps

– +transteps command line equivalent of annotate=steps• Supported by AMS simulators from artisan 5.1 release

• Earlier options were to use convdbg=detailed debug=yes diagnose=yes(source link : solution ID 11804234)


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+diagnose Option

************************************************

Transient Analysis `tran': time = (0 s -> 10 us)************************************************…

tran: time = 751.5 ns (7.52 %), step = 3.333 ns (33.3 m%)Top 10 Solution Convergence failure counts accumulated from time = 0 sto time = 1.00151 us of analysis:

4 26.67 % I3.V2:p2 13.33 % I12.V_LOAD:p

…

Top 10 Residue Convergence failure counts accumulated from time = 0 sto time = 1.00151 us of analysis:

4 80.00 % I12.net019…

Top 10 LTE check failure counts accumulated from time = 0 s to time =1.00151 us of analysis:

2 100.00 % inp…

Top 7 step size limiting signals accumulated from time = 0 s to time =1.00151 us of analysis:

153 49.68 % inp…


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+diagnose Option

…

~~~~~~~~~~~~~~~~~

Diagnosis Summary~~~~~~~~~~~~~~~~~Number of Accepted steps in (1e-10 ~ 1e-9) : 7 ( 0.23 %)Number of Accepted steps in (1e-9 ~ 1e-8) : 3002 (99.77 %)…

Total Number of Accepted steps : 3009

Maximum time step = 3.333333e-09Minimum time step = 8.161593e-10

Number of steps bounded by devices = 2982

The top 1 devices bounded counts2982 : V2

Number of steps bounded by breakpoints = 1The top 1 breakpoint bounded counts

1 : V2…


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+diagnose Option

…

Maximum value achieved for any signal of each quantity:

I: I(I3.V2:p) = 5.716 mA

If your circuit contains signals of the same quantity that are vastlydifferent in size (such as high voltage circuitry combined with lowvoltage control circuitry), you should consider specifying`relref=alllocal' on the transient analysis statement.~~~~~~~~~~~~~~~~~…

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Post-Transient Simulation Summary~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Top 10 Solution Convergence failure counts accumulated from time = 0 sto time = 10 us of `tran' analysis

4 26.67 % I3.V2:p2 13.33 % I12.V_LOAD:p

...

...

Reference : cadence source link Solution ID: 20279078


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+diagnose Options enhanced featuressoon in AMS

Diagnose Graph

Starting from MMSIM14.1, you may use "+diagnose_start" and"+diagnose_end" command line options

%irun -spectre_args “+diagnose_start=3e-6 +diagnose_end=4e-6 “( note: Using "+diagnose_start=3u +diagnose_end=4u" above does not work (source ID : 20296798) )


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Warnminstep and d2aminstep options

• Warnminstep could be used with +diagnose to provide convergencerelated information for time step less than the time specified

• d2aminstep is the minimum step size that can be taken when there is aD2A event. If it is zero, simulator min step is chosen – Use the d2aminstep option on the tran statement to define a different

minimum time step for the Spectre analog solver

– Use simvision interactive browser, look for the time, simulation is at + sign,followed by number. If number changes, then issue with CM. change

d2aminstep – Sometimes you get very small time step in d2a and this could hang the

simulator

– You may set this value to 10% of rise time of fastest clock in the design

– ADE: Analyses->Choose->tran->options->additionalParams (solution ID:11433662)

– Larger d2aminstep (e.g.


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Pruning issues with AMS-APS

• Preserve_inst set to all versus set to none

– Circuit inventory doesn’t reflect correctly, careful

while comparing log files

– Values of options like rabsshort, rthresh changes not

necessary default – Assertion reports may have issues due to collapsed

devices

• Others

– Use of ams end view instead of spectre end viewresults in wrong nelist in some cases


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Profiler option• -profile does not provide +diagnose results

– irun -profile • Measures where CPU time spend during simulation

• Use -profile option to enable profiler

• When simulation exits, ncprof.out is created in netlist directory

• Header of profiler report provides hints on performance issues• Insufficient physical memory for the size of simulation• Low CPU utilization because of busy machine or I/O

• Profiler has 3 main sections• Mixed-signal simulation summary• Digital simulation profile reports• Analog simulation profile reports (dVar, cross, transition)

• Minimize the hits either by design change or proper partitioning orbetter models, leads to simulation speed improvement.

• Reference : Virtuoso AMS Designer Simulator User Guide


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Interface Elements (CMs)• Too many CMs could slow down simulation

– digital binding of gates inside analog schematic. Minimize#a2d/d2a

– Hierarchical net probes from digital stimulus block

• Tracing busy nets and optimization of IEs – +EU_EVENTS ncsim option which will print out all a2d and

d2a events including the names of the digital signals on d2aevents : irun +EU_EVENTS

– Use schematic->AMS->Display Partition to trace IEs, analognets, digital and mixed-signal nets

– Additional statistics in irun.log file**** AMSD: Mixed-Signal Activity Statistics ***

Number of A-to-D events: 1231Number of A-to-D events in IEs: 1231Number of D-to-A events: 229Number of D-to-A events in IEs: 229Number of VHDL-AMS Breaks: 0


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Digital Simulator centric options

• When Simulation hangs, use simvision interactive

session and look for the time, simulation is at + sign,followed by a number. If the number after + , is notchanging, then it is struck in loop in digital

– control-C in simvision console window. In the prompttype where, it will show module and line number

– Use Simulation cycle debugger (windows->tools->Simulation cycle debug )

• -GATELOOPWARN option which could detect zero-delay loop of gate level models and print details

– Zero delay loop among verilog and VHDL can bedetected


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Case study 1 : DAC

Analog top

Gate

level

digital

SV

stimulus

Incisiv 12.x -- elab internal error

Incisiv 13.x -- elab sv errors

Incisiv 14.x -- elab internal error

HED config

sv_error

Take -f sv

files

Wrapper

around sv

Eliminate sv

blocks and

identify issue

block

Unintended

Force in sv

Internal

error

resolved

Internal

error

resolved

Struck at

16us for

2 days

Simvision

interactive

A CM D

Digital

loop,

where

?analogwarnminstep

ESD blocks

Dummy it

Simulation

Runs


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Case study 2 : Servo design

Analog top

Design

with

va/vams

models

verilog

stimulus

With lotsof

includes

Incisiv 12.x -- Very slow sim phase

Incisiv 13.x -- Very slow sim phase

Compared to earlier similar design

HED config

Is similar

?

CBN vs UNL Major options ?

Relref -> sigGlobalcurrent probe

optimized

d2aminstep=2e-15

Not much

inference

May be

not an

issue

Still slow

?

Linter

static &

dynamic

Switches &

transition

filter

Sometest

vectors

conv.

issue

Sw_no

model

change

Profiler,

EU_EVENT

S

ESD blocks

Dummy it

Simulation

perforamnce

improves

Need a better exportcommand for creation of

standalone test cases

mix_top

• Relaxing relref -> sigglobal, preserve_inst =no

• Dummying non-critical ESD cells

• Tweaking behavioral models as per lintoutputs

• Transition filter in slow changing waveform inanother model

• Huge change in value of rout in one of switchmodel. Dynamic linter check to detect theproblem


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Conclusions

• Slowness in simulation and convergence could happen due

to various reasons.• Debugging these issues in AMS is always a challenge and

time consuming most of the times

• Options covered in this presentation, aid designer to

provide clues to improve the design, to minimize theseissues

• Assertions, device checking etc. do slow down thesimulation performance. Smart usage of these featuresrecommended.

• Please remove all these debug statements duringregressions runs, after design debugs

• Thank You.


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Acknowledgements

• TI AMS EDA Team

– Robert Stranghoener • Cadence R & D and AE

– Mike Womac

• TI DV teams

– Keith Brouse

or .


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AMS Modeling & Debugging cheat sheet

Use Resistive switches model in veriloga/ams

Use piecewise constant argument for transition

filter

Modeling Tips

Debug Options

irun –spectre_args “-ahdllint=warn -

ahdllint_maxwarn=10000”

LSF Options

ADE: Analyses->Choose->Options

ADE: Simulation->Options->AMS Simulator

bsub –n 2 irun -R suse11 +mt=lsf

irun –profile

irun –spectre_args “+diagnose”

irun +eu_events -gateloopwarn

@cross(V(in)-0.62,0,1p,0.01));

Use of cross () and above()

Check the partition in HED

Documents

Debugging Mixed Signal AMS