Xilinx Training

Xilinx Analog Mixed Signal Introductory Overview

Note: Agile Mixed Signal is Now Analog Mixed Signal

Welcome

This module introduces the Xilinx Agile Mixed Signal Solution – Enumerate the benefits of using the Xilinx Agile Mixed signal Solution

(AMS)– List out some features enabled by the Xilinx Agile Mixed Signal Solution

Identify the key elements that constitute the Xilinx AMS solution

Identify some key applications enabled by the Xilinx AMS solution

Why Analog Processing?

Analog-to-Digital Converters – Digitizing the Analog World

Digital Control&

Processing

AnalogTo

Digital

DigitalTo

Analog

Storage&

Memory

Networking&

Communications

101101010110....

101101010110....

Traditional FPGA Functionality:

Digital Interfacing, Control, & Processing

The Human Experience– Sound, Light, Touch, Smell, Taste

Monitor & Controlling Our World– Analog Sensors– Heat, Light, Pressure, Chemical

Mixed Signal Design Challenges

ADCAnalog Signal Conditioning

Measurement

DSP

Photo Sensor

RTD Sensor

RPM Sensor

Current & Voltage Sensor

FPGA or µP

XADC DSP

7 Series FPGA or Zynq EPP

Analog Sensors

Flexible Analog Interface• Configure analog inputs• ADC timing• Change at any time

Use Programmable Logic to Customize• Control logic• Signal processing• Calibration

Xilinx Agile Mixed Signal Solution

XADC is a high quality and flexible analog interface – Dual 12-bit, 1-Msps ADCs– On-chip sensors– 17 flexible analog inputs– Track and holds with programmable

signal conditioning

Agile Mixed Signal (AMS)– Using the FPGA programmable logic

to customize the XADC and replace other external analog functions; e.g., linearization, calibration, filtering, and DC balancing to improve data conversion resolution

AMS = Combination of Analog and Programmable Logic

Lowering System Cost

Significant cost and area savings by integrating common analog interface functionality

Integrates discrete ADC or complex analog subsystem – Discrete analog functions integrated – 12-bit analog front end covers a wide range of general-purpose analog applications

Analog Interfaces

Lower System Cost, Lower Board Cost, Reduced Design Complexity and Inventory Management

Unique Customization Flexible Analog with Programmable Logic

Customized analog beyond off-the-shelf products

– Implement simple analog monitoring or – Complex analog signal conditioning and processing

Lower Cost, Improved Reliability, and Customization with AMS

Enhanced Reliability, Safety, and Security

Unique on-chip thermal and supply monitoring enhances reliability

Enhance existing security features like AES– Use sensors to detect physical attack / tampering

Diagnostics for hardware debug and verification– ChipScope Pro tool support for monitoring thermal and

supply information

Monitoring On-Chip Where External Solutions Cannot

Secure On-Chip Monitoring

Easy Access for Debug

JTAGJTA

G

XADC Block Diagram

On-ChipSensors

On-chip sensorssupplies ±1%

temperature ±4°C

On-chip sensorssupplies ±1%

temperature ±4°C

MU

X

Status

Registers

Status

Registers

Control

Registers

Control

Registers

ADC resultsADC results

AnalogAnalog

ArbitratorArbitrator

DRPDRP

Dynamic reconfiguration port interface

Dynamic reconfiguration port interface

Define XADC operation;initialize

withattributes

Define XADC operation;initialize

withattributes

Interconnect

JTAG

DigitalDigital

2 x 12 Bits1 MS/s

2 x 12 Bits1 MS/s

ADC 1ADC 1

ADC 2ADC 2

2 x 12 bits1 MS/s

2 x 12 bits1 MS/s

T/HT/H

T/HT/H

Track & hold enables flexible analog inputs and increased throughput rate

Track & hold enables flexible analog inputs and increased throughput rate

DIF

FE

RE

NT

IAL

AN

AL

OG

IN

PU

TS

17 external analog inputssupport unipolar and

differential analog input signals

17 external analog inputssupport unipolar and

differential analog input signals

On-chip MUX supports up to 17 differential

analog input channels

On-chip MUX supports up to 17 differential

analog input channels

ALARMS

XADC Primitive

XADC block I/O

XADC attributes initialize the

XADC registers (settings)

XADC registers / settings can also be accessed at any time via the FPGA fabric

MU

X

7 Series XADC

On-ChipSensors

ADC 1

ADC 2T/H

T/H

1.25V

Re

gis

ters

Xilinx Analog-to-Digital Converter (XADC)Dual 12-bit, 1-MSPS ADCs with Flexible Analog Inputs

Application Specific or Custom Data Acquisition using FPGA Logic

Tightly coupled to programmable logic of FPGA via register-based interface

Easily Introduce Analog Signals into the Digital Verification

Add analog signals for MATLAB or real

measurement to digital simulation

Target Applications

Market Application AMS Function

Industrial

• Data Acquisition• PLC• Power Conversion• Motor Control• T&M• HMI• Legacy analog interface

Monitor voltage and current sensors for safety and control of power devices (e.g., motors, DC-DC converters). Power Self Test (POST) for T & M apps. Touch-based interface for HMI. 4-20mA loops.

Communications• System Management• Analog Control Functions• Anti Tamper

Monitor temperatures and power supplies for reliability & high availability. Also security and anti-tampering. Monitor and control for DC voltage trim—lasers, VCOs, RF PAs, etc.

Aerospace & Defense• Secure Communications• Munitions

Monitor on-chip temperature and power supplies for anti-tampering purposes (security). Motor control.

Consumer• Multi Function Printer• DSLR• Broadband Access

Monitor various sensors for temperature, humidity, light, accelerometer, etc. Motor control. Touch-based user interface.

Automotive• Infotainment• Instrument Cluster

Monitor voltages, currents, and various sensors—stepper motors, touch interface, safety.

Motor Control

Simultaneous Sampling of Ia & Ib• Accommodate current senor output unipolar / differential

• Synchronize ADC sampling to PWM

Custom Signal Processing

• Off load the MCU – Clarke & Park transforms in FPGA fabric

Resistive Touch Screen

True Differential Sampling / Unipolar Mode• Measure excitation voltage from digital output

• Measure touch voltage

Control & Processing• Touch algorithm implemented

in FPGA logic

Resistive Touch Screen or EPOS solution

Use one ADC required to implement the touch interface

Second ADC can be used to monitor on-chip temperature and voltage

EPOS

Touch Screen

Anti Tamper / Security

Custom Analog Sensor Compensation in the Digital Domain

Custom Logic• Linearization and calibration of sensors

Analog Inputs• Accommodate various sensor

types• Differential / unipolar / bipolar

16-bit Conversion• More precision for

digital correction

Implementing Sensor Compensation

Add customized algorithms to compensate for analog effects

– Component tolerances, non linear sensors, thermal drift, etc.

Enhance your data acquisition designs

– Compensation is typically done in software but now can be

added to the data acquisition sub system

– Analog designers can use tools like MATLAB / Simulink

software to develop compensation algorithms and

directly target FPGA implementation

• No FPGA design / HDL knowledge needed

Logic Cell Range 8K – 350K 70K – 480K 330K – 2,000K

Block RAM 19 Mb 34 Mb 85 Mb

DSP Slices 1,040 1,920 5,280

Peak DSP Perf. (symmetrical FIR)

1,129 GMACS 2,450 GMACs 6,737 GMACS

Transceivers 16 32 96

Transceiver Performance 6.6 Gb/s 12.5 Gb/s

12.5 Gb/s, 13.1 Gb/s, 28.05 Gb/s

Memory Performance 1,066 Mb/s 1,866 Mb/s 1,866 Mb/s

PCIe Interface Gen2x4 Gen2x8 Gen3x8

I/O Pins 600 500 1,200

I/O Voltages 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V

1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V

1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V

Lowest Power and Cost

Industry’s Best Price-Performance

Industry’s Highest System Performance

7 Series FPGAsFull Digital Customization

Maximum Capability

XADC-AXI IP for ZynQ-7000 EPP and MicroBlaze Processor

KC705 AMS Targeted Design Platform

AMS Targeted Design Platform– KC705 evaluation board– AMS FMC evaluation card– AMS Targeted Reference Design– ISE® 13.4 Design Suite– Documentation

Targeted Reference Design

Agile Mixed Signal (AMS) TechnologyFlexible Analog with Programmable Logic

Customized analog beyond off-the-shelf products– Custom monitoring– Complex analog data acquisition and processing

Significant cost and area savings by integrating analog functionality– Discrete analog functions integrated – 12-bit, 1-Msps ADC covers a wide range of monitoring and data acquisition

requirements

Enhanced reliability, safety, and security– Unique on-chip temperature & supply sensors– Detection of physical tamper

Lower Cost, Customization, and Enhanced Reliability

Where Can I Learn More?

Learn more at www.xilinx.com/AMS– Agile Mixed Signal white paper (WP392)– XADC User Guide (UG480)– Watch more videos of Xilinx AMS

Visit www.xilinx.com/innovation/7-series-fpgas.htm– Application examples – New 7 series documentation

Xilinx training courses– www.xilinx.com/training

• Xilinx tools and FPGA architecture courses• Hardware description language courses• 7 series design courses• Basic FPGA architecture, basic HDL coding techniques, and other free

Videos

Page 23

Trademark Information

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.