CoolRunner™-II Advanced Features - I. Quick Start Training Goals Be familiar with some of the special features of CR2 CPLDs and know which applications

CoolRunner™-II Advanced

Features - I

Quick Start Training

Goals

• Be familiar with some of the special features of CR2 CPLDs and know which applications can benefit from them

• Explore some solutions to special signaling and interface requirements


Agenda• Clock Divider

– Ultra low lag!

• Dual Edge Flip Flops– Increase PWM resolution– Binary to BCD converter– Double speed synchronous communication– Divide by 3,5,7– Increased timer resolution– Duty cycle trick

• Interfacing to 5V signals• Pseudo LVPECL Interface

– How to...


Clock Division

Global Clock

(GCK2)

ExternalSync

Reset

Clock Divide

By 2,4,6,…,16

DIV2

DIV4

DIV16

to FB 1

to FB n

Divide Select

• Gives solid clock division without using macrocells• Duty cycle improvement• Available in larger densities (128 macrocells and above)• Very low lag…typically 50ps!


DualEDGE Flops

• Available in all CoolRunner-II CPLDs• Useful in making sequential operations faster

PTCGCK0GCK1GCK2CLK CT

PTC

to I/OD/T/L Q

CE

T FFLatch

DualEDGE

D


PWM Controller

• Used to digitally control or modulate power density– Motor controllers– Light intensity– LCD contrast– Power conversion– Position indication– Analog signal generation

• Follow PWM output with low pass filter

50%

90%

10%


PWM Basics

• A higher frequency clock than the fundamental frequency of the PWM signal is required

• This clock is counted• Count value is compared to a value in a register

bank to determine high / low times • Output registered to avoid glitches• Minimum duty cycle width typically set by period

of input clock signal


PWM Block Diagram

Counter (CNT)

PWM RegisterPWM Value

Load

CNT < PWM?


CoolRunner-II Benefit:Increased Resolution

Clock

Traditional PLDs: Minimum resolution of pulse set by clock period

CoolRunner-II CPLDs provide twice the resolution due to dual edge flops….for the same clock rate!


Binary to BCD Converter• Application : Digital

Thermometer• Can implement with look up

table (Need memory)• Implement with sequential

conversion algorithm• 8 bits of data requires 8 clock

edges for full conversion• See XAPP029 for detail on

conversion


BIN2BCD : Single Edge

• Converting h63 to d99• 700ns conversion time with 10MHz clock


BIN2BCD : Dual Edge

• Converting h63 to d99• 350ns conversion time with 10MHz clock


Synchronous Serial

• Use dual edge capable flops for data transmission across serial interface

• Twice the data for the same amount of clock periods


Double Speed Synchronous Serial

16 bit data

System Clock

Double Rate Data

Isolation

nLOAD / SHIFT

16 bit data

Receive data valid

Ready to Receive

ACKBusy


Odd Clock Generation

• DualEDGE registers can be used in conjunction with the clock divider to create ‘odd’ sub-harmonic clocks

• Divide by 3, 5, 7 possible • No additional macrocells required to implement!• Useful for asynchronous communication (bit centering),

frequency synthesis, energy distribution for noise reduction


Odd Clock Generation

Look for customers doing UARTs, or clock management!

Q DClock

DividerCLK

DualEDGE

CLK / 6 CLK / 3

CLK

Clock


Increased Timer Resolution

• Ability to index counters on rising and falling edges allows for twice the measurement resolution for any given clock!

• For best accuracy, use 50% duty cycle clocks.

Gear Speed Measurement


Clock Duty Cycle Improvement• Many applications benefit from balanced (50%) duty cycle clocks.

• Consider using referenced inputs on CoolRunner-II devices for clock balancing. • Use with caution, as this reduces noise rejection

CRIIIN

REF

HSTL/SSTL Input


CoolRunner-II 5V Tolerance

• CoolRunner-II inputs only support up to 3.3V directly

• Input voltage tolerance determined by a couple of major factors:– Gate Oxide thickness– Transistor scale

• CoolRunner-II CPLDs use 70Å oxide thickness and 0.35u transistors on the I/Os


Gate Oxide Basics

• Thick Gate – Higher voltage tolerance– Slower speed

p-substraten well

p+ p+ n+ n+

s1 s2d1

gOxide

• Thin Gate– Lower voltage tolerance– Faster speed


Oxide Breakdown and Lifetime • Oxide can be stressed with too high of a field such that

charge ‘tunneling’ occurs.– Charge traps can begin to accumulate in the oxide– Enough charge traps accumulate, and the oxide breaks down

and conducts

• Rule of thumb for voltage vs. oxide thickness :– Do not exceed 6MV per cm of thickness

• cm = 10^8 Å , so 0.06V per Å

– 70Å thickness has a limit of ~ 4.2V• Data Sheet absolute max of 4.0V

– Higher voltages exponentially decrease lifetime


How to…• Simple R/D termination scheme works• Watch your trace length / impedance!• Resistor should be chosen to match with diode, driving

source, and required delay / rise time– Typical resistor values might be 100 to 1000 Ohms

• Pick your diode carefully….– Watch for junction capacitance– Use Fast Recovery type diodes– Forward voltage impacts limiting

• Tradeoff : Power consumption !


5V Input Implementation

• 1N4148 Diode : 4pf junction, 4ns recovery, Vf = 1.0V• All tests run with 3ns input edges

5V signal

Vtt

R


100 Ohm Resistor / Rise

Input : LVCMOS18No term (float)Vdde set to 1.8VDiode term to 1.8V


100 Ohm Resistor / Fall



1000 Ohm Resistor / Rise



1000 Ohm Resistor / Fall



Poor Diode Choice : MBR0520

100 OhmsInput : LVCMOS18No term (float)Vdde set to 1.8VDiode term to 1.8V170pf !!


“Sweet” Diode Choice : SD101AWS(Diodes Inc)

100 OhmsInput : LVCMOS18No term (float)Vdde set to 1.8VDiode term to 1.8V2pf !!!1 ns Trr !!!




3.64V





Termination Tips• Terminate Vtt to power plane, and/or use good decoupling

technique• Keep trace length short to minimize reflection• Match impedance when possible

– Edges slower than 5ns, ringing not generally a problem• Use low capacitance diodes, fast recovery• Watch current through limiting resistor and through diode• Use LVCMOS18 or LVCMOS25 input, no termination, and

terminate to 1.8V / 2.5V depending on diode/resistor/signal source


Driving 5V Logic• Most 5V logic has a Vil requirement of 2.4V• CoolRunner-II devices have p-channel pull up drivers in the

outputs. Outputs swing very close to the rail• ‘Cheat’ for more headroom by supplying the device with a 3.6V

Vccio level• The higher the drive to the downstream element, the better the low

power performance• Voh dependent on load

– 1 mA load results in Voh ~ 99% of Vccio– 5 mA load results in Voh ~ 94% of Vccio– 10mA : ~ 89% Vccio


On SemiconductorMC74VHC1GT50

• Logic Level translation• Vin max = 7.0V

– Independent of Vcc

• Idd @25°C = 1uA• Package SC-88A / SOT353 $0.19

– 2.2mm X 1.35 mm

• Package TSOP5 / SOT23 $0.13– 3.1mm X 2.7 mm

• 3.5ns Tpd

NC

IN A

GND

VCC

OUT Y


Source Follower• N chan mosfet• Source voltage limited to

Vgate - Threshold• Choose mosfet with

– threshold of 1.0V to 2.5V– low gate capacitance

• Ultra low power solution– Slow…. Maybe 25ns delay– Use Schmitt trigger

• Decouple gate to ground• May need series resistor on drain side

CPLD

5V

D S5V

Vgate - Vt


Pseudo LVPECL (LVP2ECL?)

• Customers have asked for some way to interface LVPECL input to CR2 parts.

• LVPECL is a differential / referenced signaling method used in high speed applications, notably clocks.

• Voltage swings:– Voh 2.5V– Vol 1.5V

• AC and DC termination methods exist• What to do????


Typical LVPECL DC Coupling

LVPECLDriver

LVPECLReceiver

Vcc

127Ω127Ω

82.5Ω 82.5Ω

Zo = 50Ω

Zo = 50Ω

Sig

!Sig

Sig

!Sig


CoolRunner-II Solution

SSTL3

Vref

Sig

2.0V

127Ω

82.5Ω

XC2C256

Zo = 50Ω

• Termination resistors for 50Ω traces• Tested CR2 parts using char board on bench

termination different, signaling 1.6V to 2.4V


Pseudo LVPECL Results


LVPECL Details….

• Match impedance to obtain LVPECL signal swings

• Single ended operation removes common mode rejection benefits of operation

• Turn off input pin termination…. ‘Float’ pin• Vref not to be used as a dynamic input


A Quick Overview / Summary…

• Keep in mind the special features of CoolRunner-II devices when designing.. Saves time, money, and improves performance– Clock Divider– DualEDGE registers– Schmitt triggers

• 5V signaling LVPECL capable with minimal external requirements

Documents

CoolRunner™-II Advanced Features - I. Quick Start Training Goals Be familiar with some of the special features of CR2 CPLDs and know which applications