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Computer Organization Lecture 7. ALU design MIPS data path. ALU design with LS181’s. Assume 12-bit computer Active high operands Must cascade three devices Carry out must drive next carry in Mode and select bused to all devices. One device. NOTE: Active low symbol provided. - PowerPoint PPT Presentation
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Fall 2006
Lillevik 333f06-l7 1University of Portland School of Engineering
EE 333
Computer OrganizationLecture 7
ALU designMIPS data path
Fall 2006
Lillevik 333f06-l7 2University of Portland School of Engineering
EE 333
ALU design with LS181’s
• Assume– 12-bit computer– Active high operands
• Must cascade three devices– Carry out must drive next carry in– Mode and select bused to all devices
Fall 2006
Lillevik 333f06-l7 3University of Portland School of Engineering
EE 333
One device
NOTE: Active low symbol
provided
Fall 2006
Lillevik 333f06-l7 4University of Portland School of Engineering
EE 333
ALU 12-bit design
Fall 2006
Lillevik 333f06-l7 5University of Portland School of Engineering
EE 333
Add operations
What is the propagation time?
Is it the same for all numbers?
NOTE: S = 9, M = 0
Fall 2006
Lillevik 333f06-l7 6University of Portland School of Engineering
EE 333
Or operations
What is (0x555) or’d (0xaaa)?
NOTE: S = e, M = 1
Fall 2006
Lillevik 333f06-l7 7University of Portland School of Engineering
EE 333
Project 2 overview
• Sixteen-bit ALU
• Use four LS181 plus some other logic
• Arithmetic: +, -
• Logical:– and, or– shift left, shift right
Fall 2006
Lillevik 333f06-l7 8University of Portland School of Engineering
EE 333
Project 2 hints
• Use four LS181’s ALU
• Design shifter circuits
• Use muxes to select between ALU and shifters
• Design combinational logic to control muxes: consider a ROM
Fall 2006
Lillevik 333f06-l7 9University of Portland School of Engineering
EE 333
ROM device
bit 0
bit 7
Fall 2006
Lillevik 333f06-l7 10University of Portland School of Engineering
EE 333
Project 2 questions?
Fall 2006
Lillevik 333f06-l7 11University of Portland School of Engineering
EE 333
Shifting operations
• Goal: shift n-bit number left and right• Definition: 1-bit shift
– Left: lsb = 0, else bitn = bitn-1
– Right: msb = 0, else bitn = bitn+1
• General function is to shifts n-bits
Fall 2006
Lillevik 333f06-l7 12University of Portland School of Engineering
EE 333
Shift left circuit
Could you design a right shifter?
Fall 2006
Lillevik 333f06-l7 13University of Portland School of Engineering
EE 333
Timing
What mathematical function does sll perform?
Fall 2006
Lillevik 333f06-l7 14University of Portland School of Engineering
EE 333
Major Computer Components
Five classic computer components
Fall 2006
Lillevik 333f06-l7 15University of Portland School of Engineering
EE 333
Computer Components
• Input: receives information from external world
• Output: transmits information to external world
• Memory: holds programs and data
• Data path: physical route that carries info
• Control: coordinates overall flow of infoDenoted Processor
Fall 2006
Lillevik 333f06-l7 16University of Portland School of Engineering
EE 333
MIPS datapath overview
• Instruction read from memory• Registers selected for operation• ALU performs function• Result written to register
Fall 2006
Lillevik 333f06-l7 17University of Portland School of Engineering
EE 333
Instruction fetch
• PC reset on power-up; e.g., 0x 0000 0000• PC clocked at some rate (~3.0 GHz today)• Instructions (usually) accessed sequentially
PC
Instruction
memory
Readaddress
Instruction
4
Add
32-bit number or instruction
Incremented by 4 for word alignment
Fall 2006
Lillevik 333f06-l7 18University of Portland School of Engineering
EE 333
Register file
• Contains– Thirty-two, one-word numbers or registers (32
by 32, D-type flip-flops)– Similar to a small memory
• Registers: denoted $0 - $31, alternate names too
• Operations– Read any two registers – Write to one register
Fall 2006
Lillevik 333f06-l7 19University of Portland School of Engineering
EE 333
Register file symbol
Two read ports, one write port
NOTE: Orange denotes control signal
32
32
32
Fall 2006
Lillevik 333f06-l7 20University of Portland School of Engineering
EE 333
R-format structure
• Instruction fields (rs, rt, rd) select registers and ALU operation (funct)
• Result written back into register file
rs
rt
rd 32
32
32
funct
Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R type op rs rt rd shamt funct
Fall 2006
Lillevik 333f06-l7 21University of Portland School of Engineering
EE 333
Find the registers and operation?Inst = 0x00430820
=0000 0000 0100 0011 0000 1000 0010 0000
$2
$3
$1
add
Fall 2006
Lillevik 333f06-l7 22University of Portland School of Engineering
EE 333
I-format structure: lw & sw
• Requirements– Calculate effective address (addition)– Perform load (read) or store (write)
• Components– Register file– ALU for effective address– Data memory
Fall 2006
Lillevik 333f06-l7 23University of Portland School of Engineering
EE 333
I-type EA review
• Examples– lw $t1, offset ($t2)– sw $t1, offset ($t2)
• Effective address (EA) calculation– adr = base + offset
– adr = $t2 + Instr15-0 32-bit added to 16-bit ??
• Register $t1 (destination/load, source/store)
Fall 2006
Lillevik 333f06-l7 24University of Portland School of Engineering
EE 333
Memory reference logic
Effective address = sum of (reg + immed)
5
32
32
32
3232
5
5
rs
rt
immed
add
Size 6 bits 5 bits 5 bits 16 bits
I type op rs rt address/immediate
Fall 2006
Lillevik 333f06-l7 25University of Portland School of Engineering
EE 333
Design sign extension?
Fall 2006
Lillevik 333f06-l7 26University of Portland School of Engineering
EE 333
Find the registers and immed?
5
32
32
32
3232
5
5
$2
$1
0x0064
add
Instr = 0x8c410064=1000 1100 0100 0001 0000 0000 0110 0100
Fall 2006
Lillevik 333f06-l7 27University of Portland School of Engineering
EE 333
I-format structure: beq
• Example: beq $t1, $t2, offset– If $t1=$t2, then EA = PC + offset branch taken
– If $t1$t2, then EA = PC branch not taken
• Branch address– PC must first be incremented– Offset is word-aligned or shifted left 2 bits
Conditional jump instruction
Fall 2006
Lillevik 333f06-l7 28University of Portland School of Engineering
EE 333
Beq instruction
• Requirements– Determine if two registers are equal (sub or
compare)– Calculate the branch/jump address
• Components– Register file– Adder to increment PC– ALU for branch address
Fall 2006
Lillevik 333f06-l7 29University of Portland School of Engineering
EE 333
Branching logic
ALU tests for zeroAdder determines branch address
rs
rt
immed
Size 6 bits 5 bits 5 bits 16 bits
I type op rs rt address/immediate
Fall 2006
Lillevik 333f06-l7 30University of Portland School of Engineering
EE 333
Find the regs & sign extend?
inst = 0x114cfff0
$0xa
$0xc
0xfff00001 0001 0100 1100 1111 1111 1111 0000
Fall 2006
Lillevik 333f06-l7 31University of Portland School of Engineering
EE 333
Fall 2006
Lillevik 333f06-l7 32University of Portland School of Engineering
EE 333
Find the registers and operation?Inst = 0x00430820
0000 0000 0100 0011 0000 1000 0010 0000
$2
$3
$1
addrs rt rd func
Fall 2006
Lillevik 333f06-l7 33University of Portland School of Engineering
EE 333
Design sign extention?
Fall 2006
Lillevik 333f06-l7 34University of Portland School of Engineering
EE 333
Find the registers and immed?
5
32
32
32
3232
5
5
$2
$1
0x0064
add
Instr = 0x8c410064
1000 1100 0100 0001 0000 0000 0110 0100
lw $1, 100($2)
rs rt immed
Fall 2006
Lillevik 333f06-l7 35University of Portland School of Engineering
EE 333
Find the regs and sign extend?
inst = 0x114cfff0
$10
$12
immed = -16
000100 01010 01100 1111 1111 1111 0000
inst = 0001 0001 0100 1100 1111 1111 1111 0000rs rt immed