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Computer Organization Lecture 19. Exam 2 results Project 4: Memory Microprogramming: R-type. Exam 2 statistics. From Lecture 12 & 17. MIPS controller. Outputs. Outputs. Inputs IR(31:25). Outputs. Inputs. NS Decoder. Output Decoder. Present State. Flip Flops. Combo logic. ROM. - PowerPoint PPT Presentation
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Fall 2006
Lillevik 333f06-l19 1University of Portland School of Engineering
EE 333
Computer OrganizationLecture 19
Exam 2 resultsProject 4: Memory
Microprogramming: R-type
Fall 2006
Lillevik 333f06-l19 2University of Portland School of Engineering
EE 333
Exam 2 statisticsProb Std Ave
1/10 2.3 7.7
2/10 2.7 7.8
3/10 0.7 9.8
4/10 3.0 6.4
5/10 1.9 8.8
6/10 1.2 9.6
7/10 2.2 8.7
8/10 3.7 2.2
9/10 2.2 8.3
10/10 2.2 8.5
Ave 12.9 77.8
Fall 2006
Lillevik 333f06-l19 3University of Portland School of Engineering
EE 333
MIPS controller
InputsIR(31:25)
Outputs
Outputs
From Lecture 12 & 17
Fall 2006
Lillevik 333f06-l19 4University of Portland School of Engineering
EE 333
FSM architecture
Present
State
NS
Decoder
Output
Decoder
Inputs Outputs
ROM Combo logicFlip Flops
Fall 2006
Lillevik 333f06-l19 5University of Portland School of Engineering
EE 333
Project 5: Memory
• Memory contains ROM and RAM– Size: 16K words– ROM: first 256 words– RAM: remaining 16K words– Not installed: 17K – 64K words
• Due: Wednesday, November 17
Fall 2006
Lillevik 333f06-l19 6University of Portland School of Engineering
EE 333
Requirements
Input Function
ADR Contains a 16-bit address to access the memory
Din Contains a 16-bit data to write into the memory
MEMwr When asserted, data is written to the memory
Output Function
Dout Contains 16-bit data read from the memory
Address Map
Inputs
Outputs
Address Memory
0x000 – 0x0ff ROM
0x100 – 0x3fff RAM
0x4000 – 0xffff No memory installed
Fall 2006
Lillevik 333f06-l19 7University of Portland School of Engineering
EE 333
MicroAsm
• Java application: MicroAsm.class, SavitchIn.class• Microinstruction: free format, no fixed fields
• Requires input file: text-only, file.upg
• Creates output file: file.txt• Errors: command line file name, file I/O,
unrecognizable token
• Execution: BlueJ or DOS command line
Fall 2006
Lillevik 333f06-l19 8University of Portland School of Engineering
EE 333
uProgram tokens
Token Value FunctionBranch 0000 0100 Branch the uPgm to the opcode (default is next address)
Rwr 0000 0400 Write to the REG file
Imm 0000 0800 uPgm controls ALU function (default is IR[3:0])
PCinc 0000 1000 Increment the PC
PCwr 0000 2000 Write to the PC
PCwrcond 0000 4000 Write to the PC if EQ is asserted
EPC 0000 8000 Select EPC for PC write
IoD 0001 0000 Select RALU for memory address (default is PC)
MEMwr 0002 0000 Write to the memory (default is to read)
IRwr 0004 0000 Write to the IR
MDRwr 0008 0000 Write to the MDR
Fall 2006
Lillevik 333f06-l19 9University of Portland School of Engineering
EE 333
uProgram tokens, continued.
Token Value Function SPCwr 0010 0000 Write to SPC register
PCsrc 0020 0000 PC write data is branch address (default is jump address)
ALUa-R0
ALUa-PC
0040 0000
0000 0000
First ALU argument is R0
First ALU argument is PC (default is PC)
ALUb-R1
ALUb-Ext
ALUb-Trnc
0000 0000
0080 0000
0100 0000
Second ALU argument is R1
Second ALU argument is Sign Extended offset
Second ALU argument is Truncated offset
REG-RALU
REG-MDR
0000 0000
0200 0000
REG write data is the RALU
REG write data is the MDR
Fall 2006
Lillevik 333f06-l19 10University of Portland School of Engineering
EE 333
uProgram tokens, continued.
Token Value Function REGfmt 0800 0000 Selects IR[10] for the REG destination (default is IR[9])
ALUOpadd
ALUOpsub
ALUOpand
ALUOpor
ALUOpsll
ALUOpsrl
0000 0000
1000 0000
2000 0000
3000 0000
8000 0000
9000 0000
ALU function is add
ALU function is subtract
ALU function is logical AND
ALU function is logical OR
ALU function is shift left logically
ALU function is shift right logically
Next
Return
uPC+1
00
Inserts uPC+1 into uPgm next address (default)
Inserts 00 into uPgm next address
Fall 2006
Lillevik 333f06-l19 11University of Portland School of Engineering
EE 333
MDP16 state diagram
ID
sllno
p
R-fmt
sw
srl lw
addi
beq j ori
subi
andi
IFReset
1- 3
add
itio
nal c
lock
s
2 clocks
Fall 2006
Lillevik 333f06-l19 12University of Portland School of Engineering
EE 333
IF/ID states
• Write instruction from memory into IR, Increment the program counter (clock 1)
• Determine optimistic branch address Dispatch to opcode (clock 2)
IRWr
PCinc
Alua-pc
Alub-ext
imm
aluopadd
branch
Fall 2006
Lillevik 333f06-l19 13University of Portland School of Engineering
EE 333
R-type microprogram
• Func bits (IR[3:0]) determine ALU operation (clock 3)
• Write result into register file (clock 4)
aluA_R0
aluB_R1
Rwr
reg_Ralu
Return
Fall 2006
Lillevik 333f06-l19 14University of Portland School of Engineering
EE 333
R-type microprogram
Fall 2006
Lillevik 333f06-l19 15University of Portland School of Engineering
EE 333
MDP16 state diagram
ID
sllno
p
R-fmt
sw
srl lw
addi
beq j ori
subi
andi
IFReset
Fall 2006
Lillevik 333f06-l19 16University of Portland School of Engineering
EE 333
Sll instruction
• ALU function is shift left logically
• Write result into register file
Fall 2006
Lillevik 333f06-l19 17University of Portland School of Engineering
EE 333
Sll EX state?
• Origin: 0x20
• Operation: clock 3– RALUout = A << 1
• Functional units– uPgm must control ALU function– ALU funct = shift left logically– ALU input
• R0
Fall 2006
Lillevik 333f06-l19 18University of Portland School of Engineering
EE 333
Sll WB state?
• Next: return to IF
• Operation: clock 4
– Reg [ IR(10)] = ALUout
• Functional units– Must write to reg file– Data comes from RALU– Use IR[10] as destination register
Fall 2006
Lillevik 333f06-l19 19University of Portland School of Engineering
EE 333
MDP16 state diagram
ID
sllno
p
R-fmt
sw
srl lw
addi
beq j ori
subi
andi
IFReset
Fall 2006
Lillevik 333f06-l19 20University of Portland School of Engineering
EE 333
Store instruction
• Find the effective address
• Write register contents to memory
Fall 2006
Lillevik 333f06-l19 21University of Portland School of Engineering
EE 333
Store EX state?
• Origin: 0x50
• Operation: clock 3
– ALUout = A + sign-extend (IR[0:9])
• Functional units– uPgm must control ALU function
– ALU funct = add
– ALU inputs• R0
• Sign-extended offset
Fall 2006
Lillevik 333f06-l19 22University of Portland School of Engineering
EE 333
Store MEM state?
• Next: return to IF
• Operation: clock 4
– Memory [ALUout] = B
• Functional units– RALU addresses memory– R1 written into memory
Fall 2006
Lillevik 333f06-l19 23University of Portland School of Engineering
EE 333
Completed Microcode ROM
Fall 2006
Lillevik 333f06-l19 24University of Portland School of Engineering
EE 333
Fall 2006
Lillevik 333f06-l19 25University of Portland School of Engineering
EE 333
Sll microprogram
• ALU function is shift left logically (clock 3)
• Write result into register file (clock 4)
Imm
aluA_R0
aluOpSll
Rwr
reg_Ralu
regFmt
Return
Fall 2006
Lillevik 333f06-l19 26University of Portland School of Engineering
EE 333
Sll microprogram
Fall 2006
Lillevik 333f06-l19 27University of Portland School of Engineering
EE 333
Store microprogram
• Find the effective address (clock 3)
• Write register contents to memory (clock 4)
Imm
aluA_R0
aluB_ext
aluOpAdd
IoD
MemWr
return
Fall 2006
Lillevik 333f06-l19 28University of Portland School of Engineering
EE 333
Store microprogram