Coincidence Detector on SOPC Coincidence Detector on SOPC Final Presentation Presenting: Roee Bar & Gabi Klein Instructor:Ina Rivkin Technion – Israel

Coincidence DetectorCoincidence Detectoron SOPCon SOPC

Final Presentation

Presenting: Presenting: Roee Bar & Gabi Roee Bar & Gabi KleinKlein

Instructor:Instructor: Ina RivkinIna Rivkin

Technion – Israel Institute of TechnologyDepartment of Electrical EngineeringHigh Speed Digital Systems Lab

Final Presentation Final Presentation

AgendaAgenda Project GoalsProject Goals Implementation MethodImplementation Method AlgorithmAlgorithm Technical DetailsTechnical Details Implementation LimitationsImplementation Limitations DCM CapabilitiesDCM Capabilities System DescriptionSystem Description ResultsResults AchievementsAchievements Future DevelopmentsFuture Developments


GoalsGoals

Additional Goals:Additional Goals:Create a Signal Generator, which will be Create a Signal Generator, which will be

used to test the detector. used to test the detector. Thoroughly understand the features and Thoroughly understand the features and

capabilities of the Digital Clock Manager capabilities of the Digital Clock Manager (DCM) on the Virtex II Pro.(DCM) on the Virtex II Pro.

Main Goal:

Detect two simultaneous events


Implementation MethodImplementation Method

The detector and the generator will be The detector and the generator will be implemented on the Virtex II Pro platform, implemented on the Virtex II Pro platform, using the Xilinx XUPV2P Development using the Xilinx XUPV2P Development Board. Board.

The detector unit will detect coincidence of The detector unit will detect coincidence of two events in a given timeframe.two events in a given timeframe.


ReminderReminder In reality, the probability of the two events In reality, the probability of the two events

occurring exactly at the same time is practically occurring exactly at the same time is practically zero. zero. Therefore, we have to define a Therefore, we have to define a timeframetimeframe T. T.

Two events occurring in this timeframe, are called Two events occurring in this timeframe, are called coincident eventscoincident events..

T


AlgorithmAlgorithm

Let’s examine a coincidence between two Let’s examine a coincidence between two signals:signals:

A

B

A XOR B

W

Declare coincidence if W<T.Declare coincidence if W<T.Target: Find out if W<T.Target: Find out if W<T.


AlgorithmAlgorithmLet’s examine the following circuit, where Let’s examine the following circuit, where

the clock cycle is T:the clock cycle is T:

2: W>T/21: 0<W<T0: W<T/2

We assume that if coincidence occurred W<T/2 else W>T. We assume that if coincidence occurred W<T/2 else W>T. If F<2 we declare coincidence.If F<2 we declare coincidence.

SRFF

A XOR B

CLOCK’

CLOCK

S

Clk

Q

S

Clk

Q

SRFF

FCounts the

number of ‘1’

A AND B

‘2’ 0

1


AlgorithmAlgorithmWe can improve resolution and detect We can improve resolution and detect

W<2T/N.W<2T/N.Let’s take N phase shifted clocks where Let’s take N phase shifted clocks where

the k-th clock is shifted by kT/N the k-th clock is shifted by kT/N

Then, we’ll connect all the SRFF outputs Then, we’ll connect all the SRFF outputs to a counter.to a counter.


AlgorithmAlgorithmS

Clk1

Q

A XOR B

S

Clk2

Q

S

Clk3

QS

In1

In2

In3

InN

Counts theNumber of ‘1’

inputs

With the result of F, we can determine the With the result of F, we can determine the signal pulse width range in resolution of 2T/N.signal pulse width range in resolution of 2T/N.

S

ClkN

Q

A AND B

‘N’

F F=k<N → (k-1)T/N<W<(k+1)T/N F=N → W>(N-1)T/N


Technical DetailsTechnical Details

System clock frequency: 100MHz.System clock frequency: 100MHz. We will use DCM to double the clock frequency We will use DCM to double the clock frequency

to 200Mhz.to 200Mhz. DCMs used for implementation – 3DCMs used for implementation – 3 Each DCM has 4 outputs, 4 evenly shifted Each DCM has 4 outputs, 4 evenly shifted

clocks, which gives us total of 12 shifted clocks.clocks, which gives us total of 12 shifted clocks. This gives ability to determine signal pulse This gives ability to determine signal pulse

width in resolution of 2T/N=832pSec.width in resolution of 2T/N=832pSec.


Implementation LimitationsImplementation Limitations In practice the coincidence detects correctly In practice the coincidence detects correctly

when W<T-d or W>T+d. When T-d<W<T+d when W<T-d or W>T+d. When T-d<W<T+d the detector output is not defined. In our case: the detector output is not defined. In our case: d=417ps, T=5ns.d=417ps, T=5ns.

In our implementation we do not report the In our implementation we do not report the pulse length but only report coincidence when pulse length but only report coincidence when W<T-d, or no-coincidence when W>T+d.W<T-d, or no-coincidence when W>T+d.

After each coincidence the signals should be After each coincidence the signals should be stable for 2 clock cycles (~20nSec).stable for 2 clock cycles (~20nSec).

Due to flip-flops metastability some signals Due to flip-flops metastability some signals might not be detected correctly.might not be detected correctly.


DCM CapabilitiesDCM Capabilities The main capability of a DCM is clock de-

skewing. Phase Shifting: Each DCM is capable of driving

the input clock in 4 different clock phases, separated by 90° each.

Frequency Synthesis: Input frequency multiplied by two, divided by an integer between 2 and 16, multiplied by M, divided by D. By using these methods, we are capable to create almost any frequency between 3MHz and 420 MHz.

DetectorDetector


The Detector unit consists of 3 Mini Detection blocks and a The Detector unit consists of 3 Mini Detection blocks and a ControllerController

ControllerController

Mini Detection Blocks with DCMMini Detection Blocks with DCM

DetectorDetector


Mini Detection Block

Mini Detection BlockDCMDCM

SRFFSRFF SRFFSRFF SRFFSRFF SRFFSRFF

Each Mini Detection Each Mini Detection block consists of 4 block consists of 4 SRFF which handle 4 SRFF which handle 4 timeframes.timeframes.

Signal GeneratorSignal Generator


The Signal Generator produces tests signals The Signal Generator produces tests signals for the Detector.for the Detector.

Each test consists of two time shifted signals.Each test consists of two time shifted signals.

Signal GeneratorSignal Generator


DCMDCM

ControllerControllerDCMDCM

LatchLatchLatchLatch

ResultsResults


When A XOR B pulse is detected by all When A XOR B pulse is detected by all detectors – there is no coincidence (Detected detectors – there is no coincidence (Detected output is low).output is low).

ResultsResults


When A XOR B pulse is not detected by all When A XOR B pulse is not detected by all detectors – there is a coincidence (Detected detectors – there is a coincidence (Detected output is high).output is high).


AchievementsAchievements

Studied ISE, ChipScope, HDL Designer, Precision and ModelSim.

DCM configuration and usage.Developed a method to detect coincidence

using digital components only. Implemented a Signal Generator to test

our Coincidence Detector.


Future DevelopmentFuture Development

When reporting a coincidence, also report the estimated pulse width.

Improving the Coincidence Detector precision by using higher clock frequency or using more DCM units.

Overcome the system metastability issue.


Documents

Coincidence Detector on SOPC Coincidence Detector on SOPC Final Presentation Presenting: Roee Bar & Gabi Klein Instructor:Ina Rivkin Technion – Israel