Coincidence Detector on SOPC Coincidence Detector on SOPC Spring Semester 2006 Midterm Presentation Presenting: Roee Bar & Gabi Klein Instructor:Ina Rivkin

Coincidence DetectorCoincidence Detectoron SOPCon SOPC

Spring Semester 2006 Midterm Presentation

Presenting: Presenting: Roee Bar & Gabi Roee Bar & Gabi KleinKlein

Instructor:Instructor: Ina RivkinIna Rivkin

Technion – Israel Institute of TechnologyDepartment of Electrical EngineeringHigh Speed Digital Systems Lab

Sunday, June 18, 2006Sunday, June 18, 2006 Midterm Presentation Midterm Presentation

AgendaAgenda Project GoalsProject Goals ImplementationImplementation AlgorithmAlgorithm Technical DetailsTechnical Details Implementation LimitationsImplementation Limitations Additional Technical IssuesAdditional Technical Issues Achieved So FarAchieved So Far ScheduleSchedule


ReminderReminder In reality, the probability of the two events In reality, the probability of the two events

occurring exactly at the same time is practically occurring exactly at the same time is practically zero. zero. Therefore, we have to define a Therefore, we have to define a timeframetimeframe T. T.

Two events occurring in this timeframe, are called Two events occurring in this timeframe, are called coincident eventscoincident events..

T


GoalsGoals

Additional Goals:Additional Goals:Create an event generator, which will be Create an event generator, which will be

used to test the detector. used to test the detector. Thoroughly understand and document the Thoroughly understand and document the

features and capabilities of the Digital features and capabilities of the Digital Clock Manager (DCM) on the Virtex II Pro.Clock Manager (DCM) on the Virtex II Pro.

Main Goal:

Detect two simultaneous events


ImplementationImplementation

The detector and the generator will be The detector and the generator will be implemented as a core on the Virtex II Pro implemented as a core on the Virtex II Pro platform, using the Xilinx XUPV2P platform, using the Xilinx XUPV2P Development Board. Development Board.

The core will detect coincidences of two The core will detect coincidences of two events in a given timeframe and count events in a given timeframe and count them.them.


AlgorithmAlgorithm

Let’s examine a coincidence between two Let’s examine a coincidence between two signals:signals:

A

B

A XOR B

W

Declare coincidence if TDeclare coincidence if T11<W<T<W<T22..

Target: Find out if TTarget: Find out if T11<W<T<W<T22..


AlgorithmAlgorithm

Let’s say W>T/2, where T is the clock Let’s say W>T/2, where T is the clock cycle time.cycle time.

1 :0>W<T0 :W<T/2 OR W>T

Under the premise that W>T/2, this circuit Under the premise that W>T/2, this circuit detects if W<T.detects if W<T.

SRFF

A XOR B

CLOCK’

CLOCK

S

Clk

Q

S

Clk

Q

SRFF

* Synchronous SRFF

F


AlgorithmAlgorithmWe can improve resolution and detect We can improve resolution and detect

T/N<W<2T/N.T/N<W<2T/N.Let’s take N phase shifted clocks where Let’s take N phase shifted clocks where

the k-th clock is shifted by kT/N the k-th clock is shifted by kT/N

Then, we’ll connect all the SRFF outputs Then, we’ll connect all the SRFF outputs to a counter.to a counter.


AlgorithmAlgorithmS

Clk1

Q

A XOR B

S

Clk2

Q

S

Clk3

QS

In1

In2

In3

InN

Counts theNumber of ‘1’

inputs S=1

S=2

S=3

.

.

S=k

S=N

<=

<=

<=

.

.

<=

<=

0>W<2T/N

T/N<W<3T/N

T/(2N)<W<4T/N

.

.

T/(K-1)<W<(K+1)T/N

W>T

With the result of S, we can determine the With the result of S, we can determine the signal pulse width range.signal pulse width range.

S

ClkN

Q


Technical DetailsTechnical Details

DCM maximum frequency – 450MHz, DCM maximum frequency – 450MHz, (Period: 2.3nSec)(Period: 2.3nSec)

DCMs available for implementation – 4DCMs available for implementation – 4Each DCM has an output, and a 180° Each DCM has an output, and a 180°

shifted output, which gives us total of 8 shifted output, which gives us total of 8 clocks.clocks.

Minimal coincidence that can be detected: Minimal coincidence that can be detected: 0.56nSec 0.56nSec (with slower clock frequency, 0.46nSec is also possible)(with slower clock frequency, 0.46nSec is also possible)


Implementation LimitationsImplementation Limitations

Forbidden: Signal A has a pulse, while Forbidden: Signal A has a pulse, while Signal B is constant (or vice versa).Signal B is constant (or vice versa).

After each detection, there will be 3 clock After each detection, there will be 3 clock cycles (~6.7nSec), in which, the detector cycles (~6.7nSec), in which, the detector will be unable to detect any coincidences will be unable to detect any coincidences (implementation restriction).(implementation restriction).


More Technical IssuesMore Technical Issues

How can we resolve metastability in the How can we resolve metastability in the SRFF, due to the input signal?SRFF, due to the input signal?

We can add another DFF before the We can add another DFF before the SRFF, which will be used as a SRFF, which will be used as a synchronizer to prevent metastability state.synchronizer to prevent metastability state.


Achieved so farAchieved so far

Studied EDK & HDL Designer.Studied EDK & HDL Designer.DCM configuration and usage.DCM configuration and usage.

Running sample applications on the Running sample applications on the Virtex2Pro processor.Virtex2Pro processor.

Implemented Event Generator.Implemented Event Generator.


Updated ScheduleUpdated Schedule

June-July – Detector implementationJune-July – Detector implementationAugust – Converting project implementation August – Converting project implementation

to User IPs, and attaching to PLB.to User IPs, and attaching to PLB.Till mid-September - Project verification and Till mid-September - Project verification and

finalizing documentation.finalizing documentation.

Documents

Coincidence Detector on SOPC Coincidence Detector on SOPC Spring Semester 2006 Midterm Presentation Presenting: Roee Bar & Gabi Klein Instructor:Ina Rivkin