Clock Board Test

and

Preliminary Acceptance Criteria

Ciemat (Madrid), April 2009

Juan de Vicente, Javier Castilla, Gustavo Martínez

Introduction

CB configurationJumper settings and power checkingFPGA configuration

CB testGeneral checksRevision of CBv1 testing (performed by hand) Improvements for CBv2 testing

– automation of some repetitive task

– adoption of a measureable acceptance criteria for CB production Checkout documentationFuture upgrade for Clock Transition Board testing

JP19

JP13

JP11

JP17JP6

JP8

JP12

JP10

JP5

JP3

JP15

JP4

JP9

JP1

JP2

Supply 3.3v

Gnd

CLK ref.

Prog. FPGA

Config. Clk aux

JP9

Prog. FPGA

Prog. FPGA

Gnd

Gnd

Gnd

Gnd

CLK ref.

CLK ref.

Gnd

Rst aux.

Gnd

JP7 Gnd

TOP view

1

1

1

1

1

1

1

CB configuration (Jumpers settings)

1

CB configuration

TP35 +VAC +15v

TP36 -VAC -15v

TP38 +5VA +5v

TP39 -5VA -5v

Analog Voltages

TP41 GND reference

Digital Voltages

TP42 GND reference

TP44 +5VIN +5v

TP43 +3.3VIN -3.3v

Power supply checking

FPGA configuration

Firmware• Load files DocDb#2420

• Source files DocDb#2299

CB configuration

CB test

General checks:

1. Clock channel chain (126 electronic chains)

2. Telemetry

3. Clock waveform

4. Front panel ports

Goals• Ensure the range ±10 volts for all clock channels (126)

• Detecting possible defective components, assembly faults, etc.

• Produce the calibration file

• To provide an acceptance criteria

Method• Calibration

To calculate calibration constants (coef1,coef2) for all clocks Visual inspection of the calibration file for prematurely anomalies detection Updating csv file with the calibration file

• Clock Channel histogram test Histogramming the differences between programmed voltages and measured

voltages Computing rms

1. Clock channel chain checking

Multimeter

Socket

Systran

Parallel port

Serial port

panDaemon

MEC

Computing calibration constants from data

by hand connection clock-multimeter by hand setting ±10 volts in DAC counts with MEC by hand readout of the multimeter

for each Clock DAC loop

CBv1 calibration review

1 Clock

CBv1

By hand procedure

1. Clock channel chain checking

Multimeter

Socket

Systran

Parallel port

Serial port

panDaemon

MEC

CBv1 calibration review

1 Clock

CBv1

1. Clock channel chain checking

Drawbacks of by hand process - 128 measurements by hand - Error prone

Computing calibration constants from data

by hand connection clock-multimeter by hand setting ±10 volts in DAC counts with MEC by hand readout of the multimeter

for each Clock DAC loop

By hand procedure

9CCDEmulator +Mux 135:1

Improving Clock Board Testing Setup for CBv2

MCBClockBoardV1/V2

PANPC

Systran Link

CTBV 1.1

160-pin cable

Mux9 CCDemulator

Out port(scope)

1 clockInputConnector

Out port(meter)135

clocks

Multimeter/ScopeTHS710

Clock output

Serial Port

Video

TDS5000Scope

Clock outputMonsoon crate

1

12

2

3

3

4

4

5

5

Parallel Port

MultimeterTHS730

Socket

Systran

1 Clock Parallel port

Serial port

panDaemon

MEC

Clock cable (135)

Parallel port

Serial port

Socket

CBv2

CBcalibration.exe

Automatic CB calibration

Mux

CCD emulator BOARD

selectClockFromParallelPort

setClock(±10 volts in DAC counts)

for each Clock DAC loop

readoutClockVoltageFromSerialPort

output: CBcalibration.csv

1. Clock channel chain checking

calibration file inspection

visual inspection of calibration file to detecting anomalous values

Anomalous value due todefective components

1. Clock channel chain checking

Goals• Once calibrated

Histogramming the differences between programmed voltages and measured voltages

Procedure• Measuring 9 points (±8,±6,±4,±2,0 volts) per clock DAC • 2 DAC per clock, 126 clocks -> 2268 DAC clock voltage measurements (9x2x126)

• Computing rms

Constraints• DAC resolution= 95 mV (+10 to -10 volts within operational DAC range: 22 to 233 DAC

counts)

• Multimeter resolution=10 mV• Electronic tolerances

Clock Channel histogram test

1. Clock channel chain checking

MultimeterTHS730

Socket

Systran

1 Clock

Parallel port

Serial port

panDaemon

MEC

Clock cable (135)

Parallel port

Serial port

Socket

Clock channel histogram test

CBv2

CBhistogram.exe

selectClockfromEmuBoard( )

setClock(±8, ±6, ±4,±2,0 volts )

for each Clock DAC loop

measureClockVoltage( )

output: CBhistogram.csvMux

CCD emulator BOARD

1. Clock channel chain checking

Result Histogram of differences between programmed voltages and

measured voltages Computing the rms of the differences (rms_clocks)

Clock channel histogram test

rms_clocks=73mV rms_clocks=258mV

okBad channel

1. Clock channel chain checking

rms_clocks<150mV

Acceptance criteria: Clock Channel rms (rms_clocks)

rms_clocks=73mV

1. Clock channel chain checking

Goals• Detecting possible defective components in telemetry channels• Computing rms

Method• Histogram

Measuring 9 points (± 8,±6,±4,±2,0) per clock DAC setting 756 DAC clock voltage measurements (42 clocks x 2 DACs x 9

settings) Computing rms

2. Telemetry channel checking

Socket

Systran

Parallel port

Serial port

panDaemon

MEC

CBv2

CBhistogram.exe

2. Telemetry channel checking

Telemetry channel histogram

setClock(±8, ±6,±4,±2,0 volts )

for each Clock DAC loop

getClockTel( )

output:CBhistogram_tel.csv

Socket

• Result Histogram of the differences of programmed voltage and measured

voltages in telemetry rms_tel

Telemetry channel histogram

Rms_tel=101 mV

ok Bad channel

Rms_tel=360mV

2. Telemetry channel checking

rms_tel<200mV

Acceptance criteria: Telemetry rms

rms=101 mV

ok

2. Telemetry channel checking

3. Clock waveform visualization

Procedure

• The output of the mux of the CCDemulation board is connected to the scope

• Initializing MEC in continuous mode: clocks running periodically• Running exploreSignals program

A flexible program for selecting any clock out of 135– By order, by name, by CCD, etc.

• Visualization of all clock waveforms at the scope

scope

Socket

Systran

1 Clock

Parallel port

Serial port

InitializationRun clocks periodically(Continuos mode)

Clock cable (135)

Parallel port

Clock waveform visualization

CBv2

loop

2. Waveform visualizationMEC CB

exploreSignals

Mux

CCD emulator BOARD

1. selectClock( )

4. Front panel checking

Procedure

• Clocks are programmed with incremental values according to their order in the clock frame.

• Then clocks are selected in order in the front panel and verified their values with the multimeter

scope

Socket

Systran1 Clock

Parallel port

Serial portpanDaemon

FrontPanel

Front panel check

CBv2

setClock(i) to a value

Voltage Level visualization

for each Clock loop

MEC CBfrontPanel

muxSlct(i)

Socket

Checkout documentation

CBv2.1#n

General checking

Jumper settings ok

Power ok

FPGA configuration ok

Clock channels rms_clock=80 mV histogram.csv

Telemetry rms_tel=120 mV histogram_tel.csv

Clock waveform ok

Front panel ok

Clock Transition board testing

Next CB testing setup upgrade:

• Including the new cable for testing CTBv2

• A verified CTB will be used for testing all CBv2.1

• On the opposite, a verified CB will be used for testing the rest of CTB

Conclusion

Setup for testing the Clock Board production almost ready at CIEMAT (Madrid)

• Automatic calibration procedure• Automatic clock channels verification• Automatic telemetry verification• Clock waveform verification• Front panel verification• Two measurable acceptance criteria:

clock channel rms telemetry rms

• Checkout documentation• Next upgrade for testing the CTB (requiring the new cable)