Assignment 3 -304,Dcs

8/4/2019 Assignment 3 -304,Dcs

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Annexure ll

Homework title/No: Assignment -3

Course Code: ECE-304

Course Instructor: Ms. Ritu

Date of Allotment: 07/04/10

Date of Submission: 22/04/10

Students Roll No: RH6802B54

Section No: H6802

Declaration:

I declare that this is my individual work. I have not copied fronany other students work or from any other sourse except where

due acknowledgement is made explicitly in the text , nor has any

part has been written from me by another person.

Students

Signature Ramjee prasad


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1. What is the purpose of low pass filter in BPSK

demodulator model? What determines its bandwidth?

Solution:

Block diagram of BPSK:

Binary output

The above circuit arrangement is for BPSK demodulator or BPSKreceiver. In this the LPF used is set at cut off frequency. And this

LPF blocks all the frequency components

Which are above c. it results in the output to appear in the form

of logic 1and logic 0. Their would be two outputs of balanced

modulator:

(1) 1/2 cos2ct/2

(2) 1/2+cos2ct/2

When the LPF comes in to role having cut-off frequency c then

the output becomes

1/2 volt i.e logic 1

BPF

Balance

d

LPF levelconverter

Coherent

carrier

recovery

Clock

recovery


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(2) 2 volt i.e logic 0

Bandwidth:

The bandwidth of bpsk is determined by the bit rate of the

system

Minimum nyquist bandwidth

0 1 0 1 0 1 0 1

0

Fundamental frequency = Fa = Fb/2

Output of modulator = sinat.sinct

= 2/2 sinat.sinct

=1/2[ cos 2 (fc-fa)t cos2(fc+fa)t]

Bandwidth = (fc+fa) - (fc-fa)

Upper band lower band

Bw = 2fa = 2(fb/2)

Bandwidth = fb


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Where fb = Bitrate

Q(2) Draw the DPSK modulator diagram and then determine

the output phase sequence for the following input bit

sequence : 00110011010101( assume reference bit=1).Solution:

DPSK modulator:

It is an alternate form of digital modulation where the binary input

information is contained in the difference between two signals. If

the data bit firstly with reference bit is same then the output is 1

otherwise 0.

XNOR gate

Data input

DPSK

Sinct

A B o/p

0 0 1

0 1 0

1 0 0

1 1 1

1-bit

delay

Balance

modulator


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0 0 1 1 0 0 1 1 0 1 0 1 0 1 0

0 0 0 0 0 0

1 1 1 1 1 1 1 1 1

0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 1

1

Q(3)Explain the significance of the I and Q channels in a

QPSK modulator.

Solution:

QPSK modulator:

In ouadrature phase shift keying (QPSK) two successive bits in the data

sequence are grouped together. The reduces the bit rates are or signalingrate and reduces the bit rate or signaling rate(i.e fb)and thus reduces the

bandwidth the channel. By this method the frequency of the carrier

needed is also reduced. Sin ct

I/P

O/P

Bitsplitter

I

Q

CARRIERGENERAT

-OR

BALANCE

MODULATO

R 1

90pha

se

Balanced

modulator

2

BPF

summe

BPF

BPF

clock divider


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Q I output phase o/p of the

summer

0 0 -135 Cosct +sin ct

0 1 -45 Cosct -sin ct

11 01 +135+45 sin ct- Cosct-sin ct- Cosct

PART- B

(4) For the QPSK demodulator, determine the I and Q bits for an

input signal ( -sinc t + cosc t).

Solution:

For the QPSK demodulator is product detector 1 (i- channel)

= cosct-sinct).sinct

= - sin2ct+ sinct. cosct

= -[1- cos2ct/2]+[2 sinct +cosct]= -1/2 + cos2ct/2+1/2[ sin(c+c)t+ sin(c+c)t]

= -1/2 + cos2ct/2+1/2sin2ct+0

When it passes through LPF,the final output comes as:


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o/p = -1/2v

logic 0

Product modulator 2(Qchannel)

= cosct (cosct-sinct)

= cos2ct sinct. cosct

= [1+cos2ct/2]- 1/2[ sin(c+c)t+ sin(c-c)t]

= 1/2+ cosct- sin2ct/2-0

When it passes through LPF the final o/p comes as:

o/p = 1/2v=logic 1

Q( 5): Which technique is more preferred OQPSK or QPSK? Give

reasons to support your answer .

Solution:

The offset QPSK technique is more preferred than the simple

QPSK technique.

In the QPSK technique when there is two bit change the phaseshift is more than 90 degree as given in the thruth table:

0 1 phase o/p

0 0 -135

0 1 -45

1 0 +135

1 1 +45


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Where QPSK eliminates the condition of two bit change to limit

the maximum phase shift to a value 90 degree.


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Assignment 3 -304,Dcs