Arch Book Solution Ch2 Sep

8/9/2019 Arch Book Solution Ch2 Sep

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Chapter 2

Digital Logic Basics

1


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2 Chapter 2

21 Implementation using NAND gates: We can write the XOR logical expression A B using

double negation as

A B

From this logical expression, we can derive the following NAND gate implementation:

A B

Figure 2.1: 2-input XOR gate using only NAND gates.

Implementation using NOR gates: We can write the XOR logical expression as

A B

From this logical expression, we can derive the following NOR gate implementation:

A B

Figure 2.2: 2-input XOR gate using only NOR gates.


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Chapter 2 3

22 Implementation using NAND gates: We can write the exclusive-NOR logical expression

A B using double negation as

A B

From this logical expression, we can derive the following NAND gate implementation:

A B


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Chapter 2 5

Similarly, we derive the following NOR implementation by modifying the logic circuit in Fig-

ure 2.2 by deleting the output inverter:

A B


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Chapter 2 7

24 By keeping one input at 0, we can turn an XOR gate into a buffer that passes input to output as

shown below:

AA

It is clear from this and the last exercise that by controlling one input (call it control input), we canturn an XOR gate into either an inverter or a buffer. If the control input is 1, the XOR gate actsas an inverter; if the control input is 0, it acts as a buffer.


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8 Chapter 2

25 We can write the AND logical expression (A B) using double negation as

A B

From this logical expression, we can derive the following implementation:

A

B


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10 Chapter 2

27 The two transistors are in series. V

is low only when both transistors are turned on. This

happens only when both V

and V

are high as shown below:

V

V

V

low low highlow high highhigh low highhigh high low

As in the text, when we interpret low as 0 and high as 1, it implements the NAND function.


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Chapter 2 11

28 In this example, the two transistors are in parallel. V

is low when any of the two transistors are

turned on. This happens when either V

or V

(or both) is high as shown below:

V

V

V

low low highlow high lowhigh low lowhigh high low

As in the text, when we interpret low as 0 and high as 1, it implements the NOR function.


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12 Chapter 2

29 We assume that input A has 50% weight. The truth table is shown below:

A B C F0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 11 1 0 11 1 1 1

We use the Karnaugh map to derive the simplied logical expression.

0

1

00 01 11 10

01

1 1 1 1

00A

A

BCBC

From this K-map, we get the following logical expression:

A + BC

The following logic circuit implements this function:

A

B

C


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14 Chapter 2

211 (a)

Let us start with

and show that it is equivalent to

.

x x

x x

x x x

x x

x x

(b) Let us start with and show that it is equivalent to (very similar to the last exercise).

x x

x x

x x x

x x

x x

(c) As in the previous examples, we start with the right hand side (0) and show that it is equivalent to

.

0 x

x

x x

x

x

(d) This is the dual of the last exercise.

1 x

x

x x

x

x


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Chapter 2 15

212 We have to show x y and x y .

x y x y x y

x y x y y x

x y y x

x y y x

x y y x

y


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16 Chapter 2

213 We have to show x y and x y .

x y x y

x y x y y x

x y x y x y

x y y y

x


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Chapter 2 17

214 AND version:

The truth table below veries the AND version.

A B C 0 0 0 1 10 0 1 1 10 1 0 1 10 1 1 1 11 0 0 1 11 0 1 1 11 1 0 1 11 1 1 0 0

OR version: The truth table below veries the OR version.

A B C 0 0 0 1 10 0 1 0 00 1 0 0 00 1 1 0 01 0 0 0 01 0 1 0 01 1 0 0 01 1 1 0 0


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18 Chapter 2

215 From the 3-input NAND gate shown in Figure 2.23 , we can see that each additional input needs

an inverter and a 2-input NAND gate. Since we implement the inverter with a 2-input NAND gateas well, we need two 2-input NAND gates for each additional input. Thus, for an input NANDgate, we need

2-input NAND gates. To build an 8-input NAND gate we need

gates

Since there are four gates in the 7400 chip, we need four 7400 chips.


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Chapter 2 19

216 (a)

x y (de Morgons law)

(b)

x y x y y

x x y y

x y x

x y

(c)

A A B B

B A


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20 Chapter 2

217 Truth table:

A B C F0 0 0 10 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0

Sum-of-products form:

B C

A

C

A B

Product-of-sums form:

A B A C B C


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Chapter 2 21

218 We start with the product-of-sums expression and derive the sum-of-products expression.

A B A C B C

A A A C A B B C A B C

B C A B A B C B C A B A C A C

B C A C A B


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Chapter 2 23

220 We start with the product-of-sum expression and derive the other expression.

A B C A B A C B C

A A B A C B B C A B A C B

A A B A C A B C A A B A A C A B C B

B C A B A B C A B B C A C A C

By observing that A B A B C B C A C is equivalent to (A B C), we derive the sum-of-products expression.


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24 Chapter 2

221 We start with the product-of-sums expression and derive the sum-of-products expression.

A B C A B C

A A A A B B A C C B C

B C A B A B B A B C A A C

C B A A B C


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Chapter 2 25

222 Replace the exercise in the book by the following:

Using Boolean algebra show that the following two expressions are equivalent:A C C A B A C B C D

A C C B C D

Solution:

A A B C C A C B C D

A B C C A C B C D

A A C C C B C D

A

C

A

C

C

A

C

A B C D A B C D

A C C B C D


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26 Chapter 2

223 The logic circuit is shown below:


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Chapter 2 27

224 We need a 7-input XOR gate to derive the parity bit. We can construct 1 7-input XOR using 2-input

XOR gates as shown below:

A0

A1

A2

A3

A4

A5

A6

P

We need to add an inverter at the output to generate odd parity bit.


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28 Chapter 2

225

A D A B D A A D B A B D

A A B D A D A B D

A D A B D

A A B D


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Chapter 2 29

226 The truth table is shown below:

A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 11 0 1 01 1 0 11 1 1 0

B

A

A B

B

A

B

A

Clearly, we just need one inverter to implement this simplied logical expression.


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30 Chapter 2


A B C D F0 0 0 0 10 0 0 1 00 0 1 0 00 0 1 1 00 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 11 0 0 1 0

1 0 1 0 01 0 1 1 01 1 0 0 11 1 0 1 01 1 1 0 01 1 1 1 0

From the following Karnaugh map

C D

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

00

01

11

10

00 01 11 10ABCD

we get the simplied logical expression as .We just need a single NOR gate to implement this.


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Chapter 2 31

228 The following table nds the prime implicants:

Column 1 Column 2 Column 3

B

A

B

A B

A

There is no need for Step 2. The simplied expression is .


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Chapter 2 33

B

A

C

D

BA

C

D


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34 Chapter 2


Column 1 Column 2

A

A

A

B D

B D

B C

B C

A D

A C

B C D

Step 2:

Primeimplicants

Input product terms

A B D B C A D A C B C D

A

A

B D

B C

The minimal expression is

A A B D B C A B C D


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Chapter 2 35


A B C D F0 0 0 0 00 0 0 1 00 0 1 0 10 0 1 1 00 1 0 0 10 1 0 1 10 1 1 0 00 1 1 1 01 0 0 0 0

1 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 11 1 0 1 01 1 1 0 11 1 1 1 0

From the following Karnaugh map

0

1

1

0

0

1

0

0

0

0

0

1

1

0

0

1

00

01

11

10

00 01 11 10ABCD

we derive the following simplied logic expression:

C A C D B A B C A D B A B

An implementation of this logic expression is shown below:


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36 Chapter 2

AB

CA

BD

BC

A

D


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Chapter 2 37


Column 1 Column 2

C B

B

B

A B

B D

A B

A C D

A B C

Step 2:

Primeimplicants

Input product terms

C B B D A B A C D A B C

B

B

A B

C

A C D

We derive the following simplied logic expression:

C A C D B A B C A D B A B

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Arch Book Solution Ch2 Sep