Arch Book Solution Ch9 Sep

8/9/2019 Arch Book Solution Ch9 Sep

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2 Chapter 9

91 Assembler directives provide information to the assembler that is useful during the assembly pro-

cess. These are not the processor instructions.


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Chapter 9 3

92 Both statements allocate two bytes of uninitialized contiguous storage. int1is byte size whereas

int2is word-size data.


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4 Chapter 9

93 The OFFSET directive gets the address at assembly time. Since the contents of SI are known

only at runtime, it does not make sense to use OFFSET directive here (we should use the leainstruction instead).


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Chapter 9 5

94 (a) 200 bytes (each word is initialized to 1)

(b) 25 bytes (%%$$$ pattern is repeated five times)(c) 100 bytes (1122211222112221122211222 pattern is repeated four times)

(d) 2 bytes (initialized to 2300)

(e) 2 bytes (initialized to 40000)

(f) 17 bytes (Finders fee is:,0)

(g) 24 bytes (string as given in the exercise)


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6 Chapter 9

95 Assemblers provide two directivesEQU and

to define constants, numeric as well as literal

constants. TheEQU directive can be used to define numeric constants and strings, whereas the

directive can be used to define numeric constants only. When using the EQU directive, the symbols

that have been assigned a value or a string cannot be reassigned another value or string in a given

source module. Such redefinitions are allowed by the = directive. These two directives can used

to define simple macros.

A more general definition of macros is facilitated with MACRO and ENDM directives. The directives

allow definition of macros that resemble procedures in the sense they can take parameters just like

the procedures.


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Chapter 9 7

96 Just as with procedures, using parameters with macros aids in writing more flexible and useful

macros. For example, the micromultAX_by_16 MACRO

sal AX,4

ENDM

always multiplies AX by 16. By using parameters, we can generalize this macro to operate on a

byte, word, or doubleword located either in a general-purpose register or memory. The modified

macro is

mult_by_16 MACRO operand

sal operand,4

ENDM


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8 Chapter 9

97 Addressing mode refers to specification of an operand. Several addressing modes are provided to

efficiently access various data structures supported by high-level languages.


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Chapter 9 9

98 Register addressing mode is the most efficient one as the required data are available in processor

registers. There is no need to access the memory for the operands.


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10 Chapter 9

99 No, we cannot use the immediate addressing mode with the inc instruction, as this instruction

requires only one operand. Immediate addressing is used to specify constant operands.


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Chapter 9 11

910 In the direct addressing mode, the address is contained in the instruction. On the other hand, the

indirect addressing mode uses a register to specify the required address.The directaddressing can be used to access simple variables. The main drawback of this addressing

mode is that it is not useful for accessing complex data structures such as arrays and records that

are used in high-level languages. The indirect addressing mode remedies this deficiency.


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12 Chapter 9

911 For 16-bit segments, only BX, BP, SI, and DI registers are allowed to hold the offset. By default,

effective address in registers BX, SI, or DI is taken as the offset value into the data segment (i.e.,relative to the DS segment register). On the other hand, for the BP register, the offset is used to

access a data item from the stack segment (i.e., relative to the SS segment register).


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14 Chapter 9

913 The firstxchgplaces the AX value in operand1. The thirdxchginstruction stores this value

back in AX.


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Chapter 9 15

914 Whether the assembler allows or not, the following instructions do not make sense:

(b), (c) different operand sizes(e) Both operands are in memory

(f) Cannot load a value into IP

(g), (h) Destination operand cannot be a constant

(k) xchgcannot have a constant as one of the operands

All others are valid.


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16 Chapter 9

915 (a) 00005571H

(b) 3534H(c) 00003001H

(d) 3539H

(e) 00000BB8H

(f) 94E0H

(g) 00060720H

(h) 094EH

(i) 00000181H

(j) D5CDH

(k) EF4CH

(l) F942H


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Chapter 9 17

916 (a) mov BX,1

(b) mov AX,10(c) mov AX,10

(d) mov BX,1


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18 Chapter 9

917 (a) Changes the sign of the number in AX i.e., converts the number in AX to negative value in 2s

complement representation(b) Same as (a)

(c) Multiplies contents of AL by 16 and stores the result in the DX register

(d) Multiplies contents of AL by 10 and stores the result in the DX register


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Chapter 9 19

918 You dont need the initial value of AX.

(a) FFH(b) 00H


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20 Chapter 9

919 Both inc and dec update the value by 1. Therefore, the value always goes through the zero state,

which can be detected by the zero flag.


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Chapter 9 21

920 The add instruction can be implemented usingclc andadc. For example, theadd instruction

add AX,BX

can be implemented as

clc

adc AX,BX


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22 Chapter 9

921 We show this by means of an example. The

adc AX,BX

instruction can be implemented by using addas

jnc skip

inc AX

skip:

add AX,BX


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Chapter 9 23

922 The following code fragment multiplies the number in AX by 12:

add AX,AX ; AX = 2*AXadd AX,AX ; AX = 4*AX

mov BX,AX ; BX = 4*AX

add AX,AX ; AX = 8*AX

add AX,BX ; AX = 12*AX


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24 Chapter 9

923 The neg instruction changes sign of a number (negative numbers are in 2s complement represen-

tation).


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Chapter 9 25

924 The following code implements theneg AXinstruction:

not AXadd AX,1

A better version is (though it does not use theadd instruction)

not AX

inc AX


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26 Chapter 9

925 We can implement logical and by first complementing each input, then applying the logical or op-

eration, and finally the logical not operation. Here is an example that implements and AL,BL.not AL

not BL

or AL,BL

not AL

Does it relate to the digital logic material? Certainly. We have used the de Morgans law from

Chapter 2 (see Table 2.4 on page 55).


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Chapter 9 29

928 The basic idea is to detect each bit and use either and or or instruction to change the bit. We illus-

trate this by means an example that complements one bit (the least significant bit). The followingcode complements the least significant bit in the AL register:

test AL,1

jz bit_is_0

bit_is_1:

and AL,0FEH

jmp skip1

bit_is_0:

or AL,1

skip1:

Using a loop and a shift instruction, we can complement the remaining bits.


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30 Chapter 9

929 shlcan be used but not shr because it does not copy the sign bit.


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Chapter 9 31

930 shlcan be used but not shr because it copies the sign bit.


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32 Chapter 9

931 The code is shown below:

mov DL,ALand DL,0FH ; lower order 4 bits of AL are in DL

and AH,0F0H

or DL,AH


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Chapter 9 33


mov DL,ALshl DL,4

shr AH,5

rcr DL,1

shr AH,1

rcr DL,1

shr AH,1

rcr DL,1

shr AH,1

rcr DL,1

You can also use a loop that iterate four times as shown below:

mov DL,ALshl DL,4

shr AH,4

mov CX,4

loop_back:

shr AH,1

rcr DL,1

loop loop_back


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34 Chapter 9

933 This can be done by usingxor instruction as shown below:

xor AL,55H


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Chapter 9 35


mov CX,4loop_back:

shr AL,1

jc shift_0

shift_1:

stc

jmp skip1

shift_0:

clc

skip1:

rcr AL,1

ror AL,1

loop loop_back

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Arch Book Solution Ch9 Sep