139

APPENDIX 1

A1.1 SIMULATION OF THE DESIGN USING MODELSIM 6.3

VERSION

ModelSim 6.3 is a UNIX, Linux, and Windows-based simulation

and debug environment which combines high performance with the most

powerful and intuitive GUI. Its salient features are;

It has the Unified Coverage Database (UCDB) facility which

is a central point for managing, merging, and viewing,

analyzing and reporting all coverage information.

Finite State Machine Coverage for both VHDL and Verilog

supported.

Code Coverage results can be reviewed post-simulation using

the graphical user environment.

SystemC is now supported for x86 Linux 64-bit platforms.

Figure A1.1 Modelsim process window

140

A1.2 SYNTHESIS AND IMPLEMENTATION OF THE DESIGN

USING XILINX ISE DESIGN SUITE 13.2 VERSION

Synthesis is a manner of verifying the digital design whether

suitable to adapt the specified hardware or not. There is an option of

Synthesis in process tab of Xilinx ISE which performs the operation of

synthesis as shown in Figure A5.1. The synthesis process is used for

optimizing the design architecture selected. A net-list is created during this

process and it is saved to an NGC file (Net-list file with constraint

information). After design synthesis, synthesis report is generated which gives

the information about how many logic blocks are used for the design and the

overall device utilization summary of the designed architecture. Synthesis

basically maps the behavioral design to gate level design. If any error occurs

in the design, it is clearly shown after the synthesis process by means of an

error report. The implementation process undertakes four key steps.

1. Translate – Interprets the design and runs a ‘design rule

check’.

2. Map – Calculates and allocates resources in the targeted

device.

3. Place and Route – Places the CLBs in a logical position and

utilizes the routing resources.

4. Configure – Creates a programming bit-stream.

141

Figure A1.2 Process window in Xilinx ISE 13.2

Before translating the design, User Constrained file (UCF) is

written, to assign pin configuration of the FPGA to the designed architecture.

Then Translate merges the UCF file and net-list generated after synthesis into

Xilinx design file. Mapping is done to fit the design into the available

resources of target device i.e. FPGA. Last step of Design Implementation is

Placing and Routing, which places the logic blocks of the design into FPGA

and route them together to occupy minimum area and efficient timing

constraints. This operation produces Native Circuit Description (NCD) output

file. It is also called bit file generation. After generating the programming file

using the “Generate Programming File” option in the process tab, the target

device (Xilinx FPGA) can be configured using the “Configure Target Device”

option.

142

A1.3 PROGRAMMING OF THE DESIGN USING DIGILENT

ADEPT SOFTWARE

The software used to configure the Xilinx FPGA device is

“DIGILENT ADEPT”. This tool initializes the scan chain, program FPGAs,

CPLDs, and PROMs, organize and keep track of the configuration files. The

purpose of this software is to transfer the data between system and onboard

FPGA, to read and write the specified registers, to load a stream of data the

register or read a stream of data from the register. Figure A6.1 shows the

front interface of DIGILENT ADEPT software tool .Other features of the

software are (i) Program Xilinx Platform Flash devices using .bit or .mcs files

(ii) Program Xilinx CoolRunner2 CPLDs using .jed files (iii) Program most

Spartan and Virtex series FPGAs with .bit files

Figure A1.3 Digilent Adept Process window

143

APPENDIX 2

A2.1 CAPABILITIES OF VHDL

This language can be used as an exchange medium between

chip vendors and CAD tool users. Different chip vendors can

provide VHDL descriptions of their components to system

designers.

The language can also be used as a communication medium

between CAD and Computer-Aided Engineering (CAE) tools.

The language supports hierarchy; that is, a digital system can

be modeled as a set of interconnected components; each

component, in turn, can be modeled as a set of interconnected

subcomponents.

It supports both synchronous and asynchronous timing

models.

The language is publicly available.

The language supports three basic different description styles:

structural flow, data flow, and behavioral flow and any

combination of these styles.

Test benches can be written using the same language to test

other VHDL models.

The model contains information about the design itself in

terms of user-defined attributes, such as total area and speed.

144

A2.2 VHDL CODING FOR CARRIER WAVE GENERATION IN

AMTCPWM STRATEGY

Library ieee,std;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity carrier_generation is

port(Clk50MHz,rst:in std_logic;carrier_peak_data:out

integer;referencecarrier:in integer);

end carrier_generation;

architecture rtl of carrier_generation is

signal positive_peak:integer:=2095000;--2097152; --

signal neagive_peak:integer:=0;

signal peak:integer:=0;--2095000;--positive_peak;

signal flag:std_logic:='1';

signal increment:integer:=314;--631;

signal increment1:integer;

signal counter:integer:=0;

signal incr:std_logic_vector(31 downto 0);

signal incre:std_logic_vector(11 downto 0);

begin

carrier_peak_data<=peak;

process(Clk50MHz)

begin

if Clk50MHz'event and Clk50MHz='1' then

if rst='1' then

peak<=positive_peak;

145

flag<='1';

else

if flag='1' then

if (peak+increment)>=referencecarrier then

flag<='0';

counter<=0;

peak<=peak-increment;

else

peak<=peak+increment;

counter<=counter+1;

end if;

else

if peak-increment<=0 then

flag<='1';

counter<=0;

peak<=peak+increment;

else

peak<=peak-increment;

counter<=counter+1;

end if;

end if;

end if;

end if;

end process;

process(clk50MHz)

begin

if Clk50MHz'event and Clk50MHz='1' then

if rst='1' then

increment<=314;

146

else

increment1<=referencecarrier*314;

incr<=conv_std_logic_vector(increment1,32);

incre<=incr(31 downto 20);

increment<=conv_integer(incre);

end if;

end if;

end process;

end rtl;

A2.3 VHDL CODING FOR CARRIER WAVE GENERATION IN

ISCPWM STRATEGY

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity referenceforcarrier_Wave_Generation is

port(clk300KHz:in std_logic;rst:in std_logic;

Sinphase:out std_logic_vector(21 downto 0) );

end referenceforcarrier_Wave_Generation;

architecture rtl of referenceforcarrier_Wave_Generation is

signal quadrant:std_logic:='0';

--signal Vm:integer:=1024; -- modulation index 1

signal sin0 :std_logic_vector(10 downto 0):=(others=>'0');

signal Sinphase1:std_logic_vector(10 downto 0):=(others=>'0');

signal address:integer:=0;

begin

process(clk300KHz,rst)

147

variable a:std_logic_vector(10 downto 0);

type memory_type is array(0 to 49)of std_logic_vector(10 downto 0);

variable memory:memory_type:=( "00000000000", "00000100000",

"00001000000", "00001100000", "00010000000", "00010100000",

"00010111111", "00011011111", "00011111110", "00100011101",

"00100111100", "00101011011", "00101111001", "00110010110",

"00110110100", "00111010001", "00111101101", "01000001001",

"01000100100", "01000111111", "01001011010","01001110011",

"01010001100", "01010100101", "01010111101", "01011010100",

"01011101010", "01100000000", "01100010101", "01100101001",

"01100111100", "01101001111", "01101100000", "01101110001",

"01110000001", "01110010000", "01110011110", "01110101011",

"01110111000", "01111000011", "01111001110", "01111010111",

"01111011111", "01111100111", "01111101101", "01111110011",

"01111110111", "01111111011", "01111111110", "01111111111" );

begin

if clk300KHz'event and clk300KHz='1' then

if rst='1' then

a:=(others=>'0');

a:=memory(0);

address<=0;

sin0<=(others=>'0');--offset;--+Vm*a;

Sinphase<=(others=>'0');

else

-----------------------------

case quadrant is

when '0'=>

if address=49 then

quadrant<='1';

a:=memory(address);

148

else

a:=memory(address);

address<=address+1;

end if;

sin0<=a;

when others=>

if address=0 then

quadrant<='0';

a:=memory(address);

else

a:=memory(address);

address<=address-1;

end if;

sin0<=a;

end case;

--Sinphase1<="01111111111"+("01111111111"-sin0);

Sinphase1<=("01111111111"-sin0);

Sinphase<='0'&Sinphase1&"0000000000";

end if;

end if;

end process;

end rtl;

A2.4 VHDL CODING FOR CARRIER WAVE GENERATION IN

AMISCPWM STRATEGY

library ieee;

use ieee.std_logic_1164.all;

149

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity SineInvertedcarrierGeneration is

port(clk:in std_logic;rst:in std_logic; Vm:in integer;

Sinphase0:out integer );

end SineInvertedcarrierGeneration;

architecture rtl of SineInvertedcarrierGeneration is

signal s:integer;

signal S0:std_logic_vector(7 downto 0):="10000000";

signal address0:integer:=0;

signal offset:integer:=1048576;

signal Sin0 :INTEGER:=1048576;

signal flag:std_logic:='1';

signal flag1: std_logic:='0';

signal Vm1:integer:=0;

signal a1:integer:=0;

begin

Sinphase0<=Sin0;

process(clk,rst)

function sine (angle:std_logic_vector(10 downto 0)) return std_logic_vector is

variable a:integer;

variable b:integer;

variable c:integer;

variable temp:std_logic_vector(10 downto 0):="00000000000";

variable add:integer:=0;

type memory_type is array(0 to 199)of integer;

--50 sine datas, sin(degree)*128

variable memory:memory_type:=

150

( 0, 32, 64, 96, 28, 160, 191, 223, 254, 285, 316, 347, 377,

406, 436, 465, 493, 521, 548, 575, 602, 627, 652, 677,

701, 724, 746, 768, 789, 809, 828, 847, 864, 881, 897,

912, 926, 939, 952, 963, 974, 983, 991, 999, 1005, 1011,

1015, 1019, 1022, 1023, 1023, 1023, 1021, 1019, 1015, 1011, 1005,

999, 991, 983, 973, 963, 951, 939, 926, 912, 896, 880,

864, 846, 827, 808, 788, 767, 745, 723, 700, 676, 651,

626, 601, 574, 547, 520, 492, 463, 434, 405, 375, 345,

315, 284, 253, 222, 190, 158, 127, 95, 63, 30, -1, -33, -65,

-97, -129, -161, -193, -224, -256, -287, -317, -348, -378, -408,

-437, -466, -494, -522, -549, -576, -603, -628, -653, -678, -702,

-725, -747, -769, -790, -810, -829, -847, -865, -882, -898, -913,

-927, -940, -952, -964, -974, -983, -992, -999, -1006, -1011, -1016,

-1019, -1022, -1023, -1023, -1023, -1021, -1019, -1015, -1011, -1005, -998,

-991, -982, -973, -962, -951, -938, -925, -911, -896, -880, -863,

-845, -827, -807, -787, -766, -744, -722, -699, -675, -650, );

begin

if clk'event and clk='1' then if rst='1' then

a:=memory(0); address0<=0; sin0<=0;--offset;--+Vm*a; flag<='1';

else -----------------------------

151

if flag='1' then if address0=0 then

a:=memory(address0); address0<=1; flag<='0';

else a:=memory(address0); address0<=address0-1; end if;

else if address0=49 then a:=memory(address0); address0<=48; flag<='1';

else a:=memory(address0); address0<=address0+1; end if; end if;

a1<=1023-a; Vm1<=Vm*a1; sin0<=(Vm*a1);

end if; end if; end process; end rtl;

A2.5 VHDL CODING FOR CARRIER WAVE GENERATION IN

RCPWM STRATEGY

Library ieee,std;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

152

entity carrier_generation is

port (Clk50MHz,rst:in std_logic;carrier_peak_data:out integer);

end carrier_generation;

architecture rtl of carrier_generation is

signal positive_peak:integer:=2095000;--2097152; --

signal neagive_peak:integer:=0;

signal peak:integer:=2095000;--positive_peak;

signal flag:std_logic:='0';

signal increment:integer:=251;--50 MHz clock to achive 3KHz

signal counter:integer:=0;

begin

carrier_peak_data<=peak;

process(Clk50MHz)

begin

if Clk50MHz'event and Clk50MHz='1' then

if rst='1' then

peak<=positive_peak;

flag<='0';

else

if flag='1' then

peak<=peak+increment;

counter<=counter+1;

if (peak+increment)>=positive_peak then

flag<='0';

counter<=0;

end if;

else

153

peak<=peak-increment;

counter<=counter+1;

if peak-increment<=0 then

flag<='1';

counter<=0;

end if;

end if;

-- carrier_peak_data<=neagive_peak;

-- end if;

end if;

end if;

end process;

end rtl;

154

APPENDIX 3

A3.1 XILINX SPARTAN 6 FPGA DEVELOPMENT BOARD

In this research work, all the modern PWM strategies are

implemented in the Xilinx SPARTAN 6 Family FPGA Device (XC6SLX25).

The architecture of this device is shown in Figure A3.1. The Spartan-6 LX45

is optimized for high-performance logic and offers:

6,822 slices, each containing four 6- input LUTs and eight

flip-flops

2.1Mbits of fast block RAM

Four clock tiles (eight DCMs & four PLLs)

Six phase-locked loops

58 DSP slices

500MHz+ clock speeds

155

Figure A 3.1 Xilinx SPARTAN 6 FPGA Device (XC6SLX25)

The Atlys Spartan 6 FPGA Development board is used for the

implementation purpose. The Atlys circuit board is a complete, ready-to-use

digital circuit development platform based on a Xilinx Spartan-6 LX45

FPGA, speed grade -3.

156

Figure A 3.2 Atlys Spartan 6 FPGA Development board

The large FPGA and on-board collection of high-end peripherals

including Gbit Ethernet, HDMI Video, 128MByte 16-bit DDR2 memory, and

USB and audio ports make the Atlys board an ideal host for a wide range of

digital systems, including embedded processor designs based on Xilinx’s

MicroBlaze. Atlys is compatible with all Xilinx CAD tools, including

ChipScope, EDK, and the free ISE WebPack™, so designs can be completed

at no extra cost.

A3.2 SINGLE PHASE VSI

A Hardware prototype of single phase VSI has been developed

using the MOSFET SL100 with a resistive load of 150 . The photo and the

internal circuit of the VSI prototype are shown in Figure A3.3 and Figure

A3.4 respectively.

157

Figure A3.3 Single phase VSI board

Figure A3.4 Circuit description for the single phase VSI