I Analysis of Power - Measurement, Simulation, and Composability

Kim Grüttner, Ralph Görgen

kim.gruettner@offis.de

OFFIS – Institute for Information TechnologyR&D Division TransportationHardware/Software Design Methodology Group

March 18th, 2016

IMPAC WorkshopDATE’16

Dresden, Germany

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 1 Power Management Features in Consumer Electronic DevicesMotivation

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 2 Mixed-Criticality & Low Power?Motivation

App.NApp.4

App.3App.2

App.1

Federated Architecture –Multiple interconnected

single-core Processors

App.2App.1

Integrated Architecture –Partitioned single-core

Processor

Integrated Architecture –MulticoreProcessor

App.2App.1 App.N

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 3 GoalMotivation

I Goal: Enable seamless specification, analysis, and verification of multipleapplications on complex platforms considering extra-functional properties

I The “extra-functional challenge”I Shared computing resources usually “only” cover functionality and timingI Sharing the same computing platform, multiple applications can interfere

through extra-functional properties (power, energy, temperature)

→ Attribution of platform resource usage (and its power)to current application for analysis/verification!

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 3 GoalMotivation

I Goal: Enable seamless specification, analysis, and verification of multipleapplications on complex platforms considering extra-functional properties

I The “extra-functional challenge”I Shared computing resources usually “only” cover functionality and timingI Sharing the same computing platform, multiple applications can interfere

through extra-functional properties (power, energy, temperature)

→ Attribution of platform resource usage (and its power)to current application for analysis/verification!

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 4 Outline

1 Scalable (System-Level) Power Model

2 Application on Multi-Rotor HW Platform

3 Temperature-Aware Virtual Prototyping

4 Conclusion

5 Discussion

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 5 OutlineScalable (System-Level) Power Model

1 Scalable (System-Level) Power ModelPower Measurement and EnergyDynamic powerStatic powerSystem-level Parameters

2 Application on Multi-Rotor HW Platform

3 Temperature-Aware Virtual Prototyping

4 Conclusion

5 Discussion

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 6 Power Measurement and EnergyScalable (System-Level) Power Model

Power: P = IL · VL [W ]

Energy: E = IL · VL ·∆t =∫ t1

t2p(t)dt [J]

Measurement:

A

IL

E VVL

(a)

A

IL

E V VL

(b)

(a) Ammeter measures current which flows into the voltmeter and load(b) Voltmeter measures voltage drop across the ammeter in addition to that dropping acrossthe load

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 7 Dynamic power consumptionScalable (System-Level) Power Model

I Dynamic power arises from switching of CMOS cellsand can be divided into:

I Short-circuit power is dissipated when PMOS and NMOS ofa CMOS are conductive at the same timeI Short-circuit power is expressed as

Psc = Isc · Vdd

I Switching power is dissipated when load capacitances arecharged and dischargedI Switching power is expressed as

Psw = 12 · α · Csw · f · V2

dd

I Dynamic power can be reduced byI reducing the switching activity (software triggered)I lowering supply voltage and/or clock frequency – Dynamic

Voltage and Frequency Scaling (DVFS)I switching off clock – clock gating

Vdd

Gnd

In Out

Isc short-circuit current

Vdd supply voltage

α switching activity

Csw switched capacitance

f clock frequency

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 7 Dynamic power consumptionScalable (System-Level) Power Model

I Dynamic power arises from switching of CMOS cellsand can be divided into:I Short-circuit power is dissipated when PMOS and NMOS of

a CMOS are conductive at the same timeI Short-circuit power is expressed as

Psc = Isc · Vdd

I Switching power is dissipated when load capacitances arecharged and dischargedI Switching power is expressed as

Psw = 12 · α · Csw · f · V2

dd

I Dynamic power can be reduced byI reducing the switching activity (software triggered)I lowering supply voltage and/or clock frequency – Dynamic

Voltage and Frequency Scaling (DVFS)I switching off clock – clock gating

Isc

Vdd

Gnd

In Out

Isc short-circuit current

Vdd supply voltage

α switching activity

Csw switched capacitance

f clock frequency

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 7 Dynamic power consumptionScalable (System-Level) Power Model

I Dynamic power arises from switching of CMOS cellsand can be divided into:I Short-circuit power is dissipated when PMOS and NMOS of

a CMOS are conductive at the same timeI Short-circuit power is expressed as

Psc = Isc · Vdd

I Switching power is dissipated when load capacitances arecharged and dischargedI Switching power is expressed as

Psw = 12 · α · Csw · f · V2

dd

I Dynamic power can be reduced byI reducing the switching activity (software triggered)I lowering supply voltage and/or clock frequency – Dynamic

Voltage and Frequency Scaling (DVFS)I switching off clock – clock gating

Isw

Isw

Vdd

Gnd

In Out

Isc short-circuit current

Vdd supply voltage

α switching activity

Csw switched capacitance

f clock frequency

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 7 Dynamic power consumptionScalable (System-Level) Power Model

I Dynamic power arises from switching of CMOS cellsand can be divided into:I Short-circuit power is dissipated when PMOS and NMOS of

a CMOS are conductive at the same timeI Short-circuit power is expressed as

Psc = Isc · Vdd

I Switching power is dissipated when load capacitances arecharged and dischargedI Switching power is expressed as

Psw = 12 · α · Csw · f · V2

dd

I Dynamic power can be reduced byI reducing the switching activity (software triggered)I lowering supply voltage and/or clock frequency – Dynamic

Voltage and Frequency Scaling (DVFS)I switching off clock – clock gating

Isc

Vdd

Gnd

In Out

Isw

Isw

Vdd

Gnd

In Out

Isc short-circuit current

Vdd supply voltage

α switching activity

Csw switched capacitance

f clock frequency

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 8 Static power consumptionScalable (System-Level) Power Model

I Static power arises from always present leakagecurrents in the transistors

I Static power is expressed as Pleak = Vdd · IleakI Vdd supply voltageI Ileak leakage current

I Ileak mainly depends on temperature and targettechnologyI Ileak = αp · e−βpVth/T , with

I αp and βp technology dependent constantsI Vth technology dependent threshold voltageI T is temperature in Kelvin

I If temperature is assumed to be static→ static powerdepends only on supply voltage (controlled by powermanager)

I Static power can be reduced by lowering supply voltageor by switching off components (power gating)

Gate DrainSource

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 8 Static power consumptionScalable (System-Level) Power Model

I Static power arises from always present leakagecurrents in the transistors

I Static power is expressed as Pleak = Vdd · IleakI Vdd supply voltageI Ileak leakage current

I Ileak mainly depends on temperature and targettechnologyI Ileak = αp · e−βpVth/T , with

I αp and βp technology dependent constantsI Vth technology dependent threshold voltageI T is temperature in Kelvin

I If temperature is assumed to be static→ static powerdepends only on supply voltage (controlled by powermanager)

I Static power can be reduced by lowering supply voltageor by switching off components (power gating)

Gate DrainSource

Isubth

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 8 Static power consumptionScalable (System-Level) Power Model

I Static power arises from always present leakagecurrents in the transistors

I Static power is expressed as Pleak = Vdd · IleakI Vdd supply voltageI Ileak leakage current

I Ileak mainly depends on temperature and targettechnologyI Ileak = αp · e−βpVth/T , with

I αp and βp technology dependent constantsI Vth technology dependent threshold voltageI T is temperature in Kelvin

I If temperature is assumed to be static→ static powerdepends only on supply voltage (controlled by powermanager)

I Static power can be reduced by lowering supply voltageor by switching off components (power gating)

Gate DrainSource

Isubth

Igate

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 8 Static power consumptionScalable (System-Level) Power Model

I Static power arises from always present leakagecurrents in the transistors

I Static power is expressed as Pleak = Vdd · IleakI Vdd supply voltageI Ileak leakage current

I Ileak mainly depends on temperature and targettechnologyI Ileak = αp · e−βpVth/T , with

I αp and βp technology dependent constantsI Vth technology dependent threshold voltageI T is temperature in Kelvin

I If temperature is assumed to be static→ static powerdepends only on supply voltage (controlled by powermanager)

I Static power can be reduced by lowering supply voltageor by switching off components (power gating)

Gate DrainSource

Isubth

IgateIjunction Ijunction

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 8 Static power consumptionScalable (System-Level) Power Model

I Static power arises from always present leakagecurrents in the transistors

I Static power is expressed as Pleak = Vdd · IleakI Vdd supply voltageI Ileak leakage current

I Ileak mainly depends on temperature and targettechnologyI Ileak = αp · e−βpVth/T , with

I αp and βp technology dependent constantsI Vth technology dependent threshold voltageI T is temperature in Kelvin

I If temperature is assumed to be static→ static powerdepends only on supply voltage (controlled by powermanager)

I Static power can be reduced by lowering supply voltageor by switching off components (power gating)

Gate DrainSource

Isubth

IgateIjunction Ijunction

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 8 Static power consumptionScalable (System-Level) Power Model

I Static power arises from always present leakagecurrents in the transistors

I Static power is expressed as Pleak = Vdd · IleakI Vdd supply voltageI Ileak leakage current

I Ileak mainly depends on temperature and targettechnologyI Ileak = αp · e−βpVth/T , with

I αp and βp technology dependent constantsI Vth technology dependent threshold voltageI T is temperature in Kelvin

I If temperature is assumed to be static→ static powerdepends only on supply voltage (controlled by powermanager)

I Static power can be reduced by lowering supply voltageor by switching off components (power gating)

Gate DrainSource

Isubth

IgateIjunction Ijunction

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 9 System-level ParametersScalable (System-Level) Power Model

Module

DynamicActivity

Dynamic power- Annotation- PSM

Static power- Leakage [W]

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 9 System-level ParametersScalable (System-Level) Power Model

Power DomainPower Domain

Module

Module

Power ModesSupply voltage [V]Clock frequency [Hz]

Switchedcapacitance [F]

Leakingconductance [G]Module

DynamicActivity

Dynamic power- Annotation- PSM

Static power- Leakage [W]

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 9 System-level ParametersScalable (System-Level) Power Model

Die

Power Domain

Module

DynamicActivity

Power Domain

Module

Module

Die

Position (x,y,z)

Geometry

Area [m²]Neighbourhood

Thermal- Ambient temperature [°C]- Module temperature [°C]

Power DomainPower Domain

Module

Module

Power ModesSupply voltage [V]Clock frequency [Hz]

Switchedcapacitance [F]

Leakingconductance [G]Module

DynamicActivity

Dynamic power- Annotation- PSM

Static power- Leakage [W]

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 9 System-level ParametersScalable (System-Level) Power Model

System

- Technology- Process Variation- IR Drop- … ??

Design param.

Die

Power Domain

Module

DynamicActivity

Power Domain

Module

Module

Die

Position (x,y,z)

Geometry

Area [m²]Neighbourhood

Thermal- Ambient temperature [°C]- Module temperature [°C]

Power DomainPower Domain

Module

Module

Power ModesSupply voltage [V]Clock frequency [Hz]

Switchedcapacitance [F]

Leakingconductance [G]Module

DynamicActivity

Dynamic power- Annotation- PSM

Static power- Leakage [W]

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 10 System-level ParametersScalable (System-Level) Power Model

I Building blocks for a flexible power modelI Design ParametersI Dynamic annotation sources

I Parameters and value sources attached tostructural elements (components / modules)I Parameters inherited from surrounding hierarchy,

if not in local scope

System

- Technology- Process Variation- IR Drop- … ??

Design param.

Die

Power Domain

Module

DynamicActivity

Power Domain

Module

Module

Die

Position (x,y,z)

Geometry

Area [m²]Neighbourhood

Thermal- Ambient temperature [°C]- Module temperature [°C]

Power DomainPower Domain

Module

Module

Power ModesSupply voltage [V]Clock frequency [Hz]

Switchedcapacitance [F]

Leakingconductance [G]Module

DynamicActivity

Dynamic power- Annotation- PSM

Static power- Leakage [W]

I Hierarchical (stream) processing [1] of derived values by subscribing to value sources,e.g.

P(t) = V 2ddf · C(t) + V 2

dd · G(ϑ(t))

C(t) average switching capacitance per cycle (dynamic annotation)G(ϑ(t)) leaking conductance (depending on temperature ϑ(t)) (dynamic)

Vdd , f supply voltage, frequency (static parameters)P(t) processed function for dynamic+static power dissipation

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 10 System-level ParametersScalable (System-Level) Power Model

I Building blocks for a flexible power modelI Design ParametersI Dynamic annotation sources

I Parameters and value sources attached tostructural elements (components / modules)I Parameters inherited from surrounding hierarchy,

if not in local scope

System

- Technology- Process Variation- IR Drop- … ??

Design param.

Die

Power Domain

Module

DynamicActivity

Power Domain

Module

Module

Die

Position (x,y,z)

Geometry

Area [m²]Neighbourhood

Thermal- Ambient temperature [°C]- Module temperature [°C]

Power DomainPower Domain

Module

Module

Power ModesSupply voltage [V]Clock frequency [Hz]

Switchedcapacitance [F]

Leakingconductance [G]Module

DynamicActivity

Dynamic power- Annotation- PSM

Static power- Leakage [W]

I Hierarchical (stream) processing [1] of derived values by subscribing to value sources,e.g.

P(t) = V 2ddf · C(t) + V 2

dd · G(ϑ(t))

C(t) average switching capacitance per cycle (dynamic annotation)G(ϑ(t)) leaking conductance (depending on temperature ϑ(t)) (dynamic)

Vdd , f supply voltage, frequency (static parameters)P(t) processed function for dynamic+static power dissipation

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 11 OutlineApplication on Multi-Rotor HW Platform

1 Scalable (System-Level) Power Model

2 Application on Multi-Rotor HW PlatformThe Multi-Rotor Mixed-Criticality SystemPower Model: HW ArchitecturePower Model: DiePower Model: Power IslandsPower Model: Components

3 Temperature-Aware Virtual Prototyping

4 Conclusion

5 Discussion

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 12 The Multi-Rotor Mixed-Criticality SystemApplication on Multi-Rotor HW Platform

Multi-Rotor System [2]

I Flight control algorithm and

I payload processing (video)

I on the same MPSoC (Xilinx Zynq-7000)

Mixed-Criticality System on a ChipI Flight control→ safety-critical

I Payload processing→ non-critical

Fd

Fa

Fc

Fb

Fgravity acceleration

z

xy

C

D

B

B

A

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 13 The Multi-Rotor Mixed-Criticality SystemApplication on Multi-Rotor HW Platform

Problem

I Mixed-Criticality system on a single chip.

I Logically separated safety and non-safetycritical functions.

I But both systems are electrically andthermally coupled.

QuestionsI Does the critical function alone ever violate

the thermal limit?

I Can the non-critical function use arbitraryprocessing resources?

I Is the chosen resource/powermanagement strategy sufficient?

<<component>>

Data Mining

<<component>>

Mission Data

Processing

<<HW resource>>

ARM9 MP Cortex

<<processing resource>>

A9 Core 1

<<processing resource>>

A9 Core 2

<<OS>>

Linux kernel

<<alloc>>

<<alloc>>

<<alloc>>

<<HW resource>>

Programming Logic

<<processing resource>>

MicroBlaze

<<alloc>>

<<component>>

Flight Control

<<alloc>>

<<processing resource>>

MicroBlaze

Safety-Critical Part

Mission-Critical Part

PPM decoding IP core

ARM9 MP Cortex

A9 Core 0

Programmable Logic

Camera SD-Card

Motor Drivers

DPRAM 1

Battery

Guards

LEDs/Pins/Buzzer

MPU9150

BMP085

RCReceiver

PPM IP

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

I2C IP

I2C IP

SPI IP

USB

Gimbal Wi-Fi

SDIO

MicroBlaze 1

Data Mining

AMBA Interconnect

DPRAM 2

I2C IP

GPIO

MicroBlaze 2

Flight Control

1

GPIO

UART IP

DDR-RAM

DDR L2 Cache

L1 Cache L1 Cache

AXI BusAXI Bus

I/D RAMI/D RAM

A9 Core

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 14 Power Model: HW ArchitectureApplication on Multi-Rotor HW Platform

Safety-Critical Part

Mission-Critical Part

PPM decoding IP core

ARM9 MP Cortex

A9 Core 0

Programmable Logic

Camera SD-Card

Motor Drivers

DPRAM 1

Battery

Guards

LEDs/Pins/Buzzer

MPU9150

BMP085

RCReceiver

PPM IP

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

I2C IP

I2C IP

SPI IP

USB

Gimbal Wi-Fi

SDIO

MicroBlaze 1

Data Mining

AMBA Interconnect

DPRAM 2

I2C IP

GPIO

MicroBlaze 2

Flight Control

1

GPIO

UART IP

DDR-RAM

DDR L2 Cache

L1 Cache L1 Cache

AXI BusAXI Bus

I/D RAMI/D RAM

A9 Core

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 15 Power Model: DieApplication on Multi-Rotor HW Platform

IP core

A9 Core 0

Camera SD-Card

Motor Drivers

Battery

Guards

LEDs/Pins/Buzzer

MPU9150

BMP085

RCReceiver

PPM IP

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

I2C IP

I2C IP

SPI IP

USB

Gimbal Wi-Fi

SDIO

AMBA Interconnect

DPRAM 2

I2C IP

GPIO

GPIO

UART IP

DDR-RAM

DDR L2 Cache

L1 Cache

1

L1 Cache

A9 Core

MicroBlaze 2

Flight Control

I/D RAM

AXI Bus

MicroBlaze

Data Mining

AXI Bus

I/D RAM

1DPRAM

1

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 16 Power Model: Power IslandsApplication on Multi-Rotor HW Platform

IP core

A9 Core 0

Programmable Logic

Camera SD-Card

Motor Drivers

Battery

Guards

LEDs/Pins/Buzzer

MPU9150

BMP085

RCReceiver

PPM IP

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

I2C IP

I2C IP

SPI IP

USB

Gimbal Wi-Fi

SDIO

AMBA Interconnect

DPRAM 2

I2C IP

GPIO

GPIO

UART IP

DDR-RAM

DDR L2 Cache

L1 Cache

1

L1 Cache

A9 Core

MicroBlaze 2

Flight Control

I/D RAM

AXI Bus

MicroBlaze

Data Mining

AXI Bus

I/D RAM

1DPRAM

1

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 17 Power Model: ComponentsApplication on Multi-Rotor HW Platform

IP core

A9 Core 0

Programmable Logic

Camera SD-Card

Motor Drivers

Battery

Guards

LEDs/Pins/Buzzer

MPU9150

BMP085

RCReceiver

PPM IP

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

I2C IP

I2C IP

SPI IP

USB

Gimbal Wi-Fi

SDIO

AMBA Interconnect

DPRAM 2

I2C IP

GPIO

GPIO

UART IP

DDR-RAM

DDR L2 Cache

L1 Cache

1

L1 Cache

A9 Core

MicroBlaze 2

Flight Control

I/D RAM

AXI Bus

MicroBlaze

Data Mining

AXI Bus

I/D RAM

1DPRAM

1

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 18 OutlineTemperature-Aware Virtual Prototyping

1 Scalable (System-Level) Power Model

2 Application on Multi-Rotor HW Platform

3 Temperature-Aware Virtual PrototypingGeneral overviewFloorplan & PowerThermal modeling and temperature analysisPackage modelFull chip thermal map over high-level floorplanExperiments

4 Conclusion

5 Discussion

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 19 Temperature-Aware Virtual PrototypingGeneral overview

© 2013-2016 CONTREX consortium

Flow overview1

TRACE

ANY OTHER

I/O DATA

TOOL

SoC platform

definition

SoC platform timing

& activity observation

Primary traces

Functio

n(t)

VDD(t) fclk(t)

C(t)

VDD(t)

C(t),

activity(t)

Application(s)Contract/

Property

Contract/

Property

satisfaction

monitoring

Function-

call(t)

fclk(t)

Executable SoC

model/

Virtual Platform

Stimuli

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 20 Temperature-Aware Virtual PrototypingGeneral overview

© 2013-2016 CONTREX consortium

Flow overview1

Component-

Level

Floorplan

Power mapper

Power Model

Power map

P(x,y,zi)

TRACE

ANY OTHER

I/O DATA

TOOL

SoC platform

definition

SoC platform timing

& activity observation

Primary traces

Functio

n(t)

VDD(t) fclk(t)

C(t)

VDD(t)

C(t),

activity(t)

Application(s)Contract/

Property

Contract/

Property

satisfaction

monitoring

Function-

call(t)

fclk(t)

Executable SoC

model/

Virtual Platform

Stimuli

Secondary traces

Pdyn(t)Ileak(t)

per comp. Pdyn(t)Pdyn(t)

per comp.

Ileak(t)

per comp.Ileak(t)

per comp.

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 21 Temperature-Aware Virtual PrototypingGeneral overview

© 2013-2016 CONTREX consortium

Flow overview1

Component-

Level

Floorplan

Power mapper

Power Model

Power map

P(x,y,zi)

SoC package

data

Thermal

modeler

TRACE

ANY OTHER

I/O DATA

TOOL

SoC platform

definition

SoC platform timing

& activity observation

Primary traces

Functio

n(t)

VDD(t) fclk(t)

C(t)

VDD(t)

C(t),

activity(t)

Application(s)

Thermal

model

Contract/

Property

Contract/

Property

satisfaction

monitoring

Function-

call(t)

fclk(t)

Executable SoC

model/

Virtual Platform

Stimuli

Secondary traces

Pdyn(t)Ileak(t)

per comp. Pdyn(t)Pdyn(t)

per comp.

Ileak(t)

per comp.Ileak(t)

per comp.

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 22 Temperature-Aware Virtual PrototypingGeneral overview

© 2013-2016 CONTREX consortium

Flow overview1

Component-

Level

Floorplan

Power mapper

Power Model Temperature

analysis

Power map

P(x,y,zi)

Temperature map

θ(x,y,zi)

SoC package

data

Thermal

modeler

TRACE

ANY OTHER

I/O DATA

TOOL

SoC platform

definition

SoC platform timing

& activity observation

Primary traces

Functio

n(t)

VDD(t) fclk(t)

C(t)

VDD(t)

C(t),

activity(t)

Application(s)

Thermal

model

Contract/

Property

Contract/

Property

satisfaction

monitoring

Secondary traces

Pdyn(t)Ileak(t)

per comp. Pdyn(t)Pdyn(t)

per comp.

Tertiary traces

Θ(t)Θ(t) per

comp.Θ(t) per

comp.

Function-

call(t)

Θ(t)

fclk(t)

Executable SoC

model/

Virtual Platform

Stimuli

Ileak(t)

per comp.Ileak(t)

per comp.

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 23 Temperature-Aware Virtual PrototypingFloorplan & Power

© 2013-2016 CONTREX consortium

Floorplan & Power2

Component-

Level

Floorplan

Power mapper

Total power map

P(x,y,zi)

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 24 Temperature-Aware Virtual PrototypingThermal modeling and temperature analysis

© 2013-2016 CONTREX consortium

Thermal modeling and temperature analysis1

Component-

Level

Floorplan

Power mapper

Temperature

analysis

Total power map

P(x,y,zi)

Temperature map

θ(x,y,zi)

SoC package

data

Thermal

modeler

Thermal

model

Physical parameters:

type of materials and positionsFloorplan and power

consumption

trPtrrktrt

rCr T ,,,

i i

ir

e

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 25 Temperature-Aware Virtual PrototypingPackage model

© 2013-2016 CONTREX consortium

Thermal modeling and temperature analysis1

Component-

Level

Floorplan

Power mapper

Temperature

analysis

Total power map

P(x,y,zi)

Temperature map

θ(x,y,zi)

SoC package

data

Thermal

modeler

Thermal

model

Physical parameters:

type of materials and positionsFloorplan and power

consumption

trPtrrktrt

rCr T ,,,

i i

ir

e

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 26 Temperature-Aware Virtual PrototypingPackage model

© 2013-2016 CONTREX consortium

1

3

4

2

5

6

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 27 Temperature-Aware Virtual PrototypingFull chip thermal map over high-level floorplan

© 2013-2016 CONTREX consortium

Full chip thermal map over high-level

floorplan

6

Temperature

analysis

Total power map

Ptot(x,y,zi)

Temperature map

θ(x,y,zi)

Thermal

model

Component-

Level

Floorplan

Power mapper

SoC package

data

Thermal

modeler

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 28 Temperature-Aware Virtual PrototypingFull chip thermal map over high-level floorplan

© 2013-2016 CONTREX consortium

Full chip thermal map over high-level

floorplan

6

Temperature

analysis

Total power map

Ptot(x,y,zi)

Temperature map

θ(x,y,zi)

Thermal

model

Θ(t)Θ(t) per

comp.Θ(t) per

comp.

Component-

Level

Floorplan

Power mapper

SoC package

data

Thermal

modeler

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 29 Temperature-Aware Virtual PrototypingExperiment 1: Flight Control Only

0 100 200 300 400 500 60025

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80Power and Temperature Development of Zynq platform

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pera

ture

[ o C

]

ARM1ARM2MB1MB2

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0.5

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er [W

]

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0.5

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MB1&2

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 30 Temperature-Aware Virtual PrototypingExperiment 2: Flight Control and Video Processing

0 100 200 300 400 500 60025

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80Power and Temperature Development of Zynq platform

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ture

[ o C

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MB1&2

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 31 Temperature-Aware Virtual PrototypingExperiment 3: Flight Control and Video Processing with power management

0 100 200 300 400 500 60025

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80Power and Temperature Development of Zynq platform

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0.5

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MB1&2

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 32 OutlineConclusion

1 Scalable (System-Level) Power Model

2 Application on Multi-Rotor HW Platform

3 Temperature-Aware Virtual Prototyping

4 Conclusion

5 Discussion

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 33 Conclusion

I Considering extra-functional properties is increasingly important right from the beginningin the design flowI Uncovers cause-effect relationships: function→ activity→ power consumption→ temperatureI Enables analysis of the effectiveness and optimization potentials of resource & power management

I Mixed-criticality and extra-functional propertiesI Integration of multiple applications on the same (multi-core) platformI Enable analysis and validation/verification of power and temperature requirements with

application-level granularity

I Introduction of resource or power management in mixed-criticality systems may lead tocriticalitiy level inheritanceI Application of resource or power management on a non-critical functionI If this is required to keep safety-critical function in a safe state (e.g. under defined temperature

threshold)I Then non-critical function and resource or power management inherits safety-critical level

→ Resource or power management shall be considered at highest criticality level

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 33 Conclusion

I Considering extra-functional properties is increasingly important right from the beginningin the design flowI Uncovers cause-effect relationships: function→ activity→ power consumption→ temperatureI Enables analysis of the effectiveness and optimization potentials of resource & power management

I Mixed-criticality and extra-functional propertiesI Integration of multiple applications on the same (multi-core) platformI Enable analysis and validation/verification of power and temperature requirements with

application-level granularity

I Introduction of resource or power management in mixed-criticality systems may lead tocriticalitiy level inheritanceI Application of resource or power management on a non-critical functionI If this is required to keep safety-critical function in a safe state (e.g. under defined temperature

threshold)I Then non-critical function and resource or power management inherits safety-critical level

→ Resource or power management shall be considered at highest criticality level

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 33 Conclusion

I Considering extra-functional properties is increasingly important right from the beginningin the design flowI Uncovers cause-effect relationships: function→ activity→ power consumption→ temperatureI Enables analysis of the effectiveness and optimization potentials of resource & power management

I Mixed-criticality and extra-functional propertiesI Integration of multiple applications on the same (multi-core) platformI Enable analysis and validation/verification of power and temperature requirements with

application-level granularity

I Introduction of resource or power management in mixed-criticality systems may lead tocriticalitiy level inheritanceI Application of resource or power management on a non-critical functionI If this is required to keep safety-critical function in a safe state (e.g. under defined temperature

threshold)I Then non-critical function and resource or power management inherits safety-critical level

→ Resource or power management shall be considered at highest criticality level

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 34 OutlineDiscussion

1 Scalable (System-Level) Power Model

2 Application on Multi-Rotor HW Platform

3 Temperature-Aware Virtual Prototyping

4 Conclusion

5 Discussion

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

neededI Usage of predictable and functionally intrusive power/thermal management: switch off applications or

change modesI . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

neededI Usage of predictable and functionally intrusive power/thermal management: switch off applications or

change modesI . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?

I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

neededI Usage of predictable and functionally intrusive power/thermal management: switch off applications or

change modesI . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?

I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

neededI Usage of predictable and functionally intrusive power/thermal management: switch off applications or

change modesI . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task execution

I Usage of predictable and functionally non-intrusive power management: turn off components when notneeded

I Usage of predictable and functionally intrusive power/thermal management: switch off applications orchange modes

I . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

needed

I Usage of predictable and functionally intrusive power/thermal management: switch off applications orchange modes

I . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

neededI Usage of predictable and functionally intrusive power/thermal management: switch off applications or

change modes

I . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

neededI Usage of predictable and functionally intrusive power/thermal management: switch off applications or

change modesI . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 35 Discussion

I Temperature is not composable: interference over time and space

I Power is not composable as well: interference over time and space due to thermal inducedleakage power P(t) = V 2

ddf · C(t) + V 2dd · G(ϑ(t))

I What can be done?I Freeze it! -> Not realistic?I Layout and mapping decisions: consider temporal and spatial properties during partition/task executionI Usage of predictable and functionally non-intrusive power management: turn off components when not

neededI Usage of predictable and functionally intrusive power/thermal management: switch off applications or

change modesI . . .

I In mixed-criticality systems energy becomes an equally important resource as time [3]!

I Temporal and spatial segregation becomes necessary

I Realizable through HW design considerations and power/thermal management at highest criticalitylevel [4]→ http://www.safepower-project.eu/

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 36 That’s all, folks. . .

Thank you! Any questions?<kim.gruettner@offis.de>

http://contrex.offis.de

http://www.safepower-project.eu

This work has been partially supported by the FP7European Integrated Projects CONTREX funded by theEuropean Commission under Grant Agreements 611146.

The SafePower project and the research leading tothese results has received funding from the EuropeanCommunity’s H2020 program [H2020-ICT-2015] underGrant Agreement 687902.

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016

I 37 References

[1] Philipp A. Hartmann, Kim Grüttner, and Wolfgang Nebel. “Advanced SystemC Tracing and Analysis Framework forExtra-Functional Properties”. English. In: Applied Reconfigurable Computing. Ed. by Kentaro Sano et al. Vol. 9040.Lecture Notes in Computer Science. Springer International Publishing, 2015, pp. 141–152. ISBN: 978-3-319-16213-3.DOI: 10.1007/978-3-319-16214-0_12. URL: http://dx.doi.org/10.1007/978-3-319-16214-0_12.

[2] H. Schlender et al. “Teaching Mixed-Criticality: Multi-Rotor Flight Control and Payload Processing on a Single Chip”. In:Proceedings of the WESE’15: Workshop on Embedded and Cyber-Physical Systems Education. WESE’15. Amsterdam,Netherlands: ACM, 2015, 9:1–9:8. ISBN: 978-1-4503-3897-4. DOI: 10.1145/2832920.2832929. URL:http://doi.acm.org/10.1145/2832920.2832929.

[3] Marcus Völp, Marcus Hähnel, and Adam Lackorzynski. “Has energy surpassed timeliness? Schedulingenergy-constrained mixed-criticality systems”. In: 20th IEEE Real-Time and Embedded Technology and ApplicationsSymposium, RTAS 2014, Berlin, Germany, April 15-17, 2014. IEEE, 2014, pp. 275–284. ISBN: 978-1-4799-4691-4. DOI:10.1109/RTAS.2014.6926009. URL: http://dx.doi.org/10.1109/RTAS.2014.6926009.

[4] Andrew Nelson, Anca Mariana Molnos, and Kees Goossens. “Composable power management with energy and powerbudgets per application”. In: 2011 International Conference on Embedded Computer Systems: Architectures, Modeling,and Simulation, SAMOS XI, Samos, Greece, July 18-21, 2011. Ed. by Luigi Carro and Andy D. Pimentel. IEEE, 2011,pp. 396–403. ISBN: 978-1-4577-0802-2. DOI: 10.1109/SAMOS.2011.6045490. URL:http://dx.doi.org/10.1109/SAMOS.2011.6045490.

I OFFIS – Institute for Information Technology Kim Grüttner, Ralph Görgen March 18th, 2016