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Copyright Agrawal & Srivaths, 2Copyright Agrawal & Srivaths, 2007007
Low-Power Design and Test, Lecture 2Low-Power Design and Test, Lecture 2 11
Low-Power Design and Low-Power Design and TestTest
Dynamic and Static Power in Dynamic and Static Power in CMOSCMOS
Vishwani D. AgrawalVishwani D. AgrawalAuburn University, USAAuburn University, [email protected]@eng.auburn.edu
Srivaths RaviSrivaths RaviTexas Instruments IndiaTexas Instruments India
[email protected]@ti.com
Hyderabad, July 30-31, 2007http://www.eng.auburn.edu/~vagrawal/hyd.html
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 2
Components of PowerComponents of Power
DynamicDynamic Signal Signal
transitionstransitions Logic activityLogic activity GlitchesGlitches
Short-circuitShort-circuit StaticStatic
LeakageLeakage
Ptotal = Pdyn + Pstat
Ptran + Psc + Pstat
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 3
Power of a Transition: Power of a Transition: PPtrantran
VVDDDD
GroundGround
CL
Ron
R = large
vi (t) vo(t) ic(t)
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 4
Charging of a CapacitorCharging of a Capacitor
V C
R
i(t) v(t)
Charge on capacitor, q(t) = C v(t)
Current, i(t) = dq(t)/dt = C dv(t)/dt
t = 0
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 5
i(t) = C dv(t)/dt = [V – v(t)] /R dv(t) V – v(t) ─── = ───── dt RC
dv(t) dt∫ ───── = ∫ ──── V – v(t) RC
-t ln [V – v(t)] = ── + A
RC
Initial condition, t = 0, v(t) = 0 → A = ln V -t
v(t) = V [1 – exp(───)]
RC
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 6
-t v(t) = V [1 – exp( ── )]
RC
dv(t) V -ti(t) = C ─── = ── exp( ── )
dt R RC
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 7
Total Energy Per Charging Total Energy Per Charging Transition from Power SupplyTransition from Power Supply
∞ ∞ V2 -tEtrans = ∫ V i(t) dt = ∫ ── exp( ── ) dt
0 0 R RC
= CV2
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 8
Energy Dissipated per Transition Energy Dissipated per Transition in Resistancein Resistance
∞ V2 ∞ -2tR ∫ i2(t) dt = R ── ∫ exp( ── ) dt 0 R2 0 RC
1= ─ CV2
2
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 9
Energy Stored in Charged Energy Stored in Charged Capacitor Capacitor
∞ ∞ -t V -t∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt0 0 RC R RC
1 = ─ CV2
2
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 10
Transition PowerTransition Power Gate output rising transitionGate output rising transition
Energy dissipated in pMOS transistor = Energy dissipated in pMOS transistor = CV CV 22/2/2 Energy stored in capacitor = Energy stored in capacitor = CV CV 22/2/2
Gate output falling transitionGate output falling transition Energy dissipated in nMOS transistor = Energy dissipated in nMOS transistor = CV CV 22/2/2
Energy dissipated per transition = Energy dissipated per transition = CV CV 22/2/2 Power dissipation:Power dissipation:
Ptrans = Etrans α fck = α fck CV2/2
α = activity factor
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 11
Components of PowerComponents of Power
DynamicDynamic Signal Signal
transitionstransitions Logic activityLogic activity GlitchesGlitches
Short-circuitShort-circuit StaticStatic
LeakageLeakage
Ptotal = Pdyn + Pstat
Ptran + Psc + Pstat
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 12
Short Circuit Power of a Short Circuit Power of a Transition: Transition: PPscsc
VVDDDD
GroundGround
CL
vi (t) vo(t) isc(t)
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 13
Short Circuit Current, Short Circuit Current, iiscsc((tt))
Time (ns)0 1
Isc
Volt
VDD
isc(t)
0
Vi (t)Vo(t)
VDD - VTp
VTn
tB tE
Iscmaxf
p-transistor starts conducting
n-transistor cuts-off
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 14
Peak Short Circuit CurrentPeak Short Circuit Current
Increases with the size (or gain, Increases with the size (or gain, ββ) of ) of transistorstransistors
Decreases with load capacitance, Decreases with load capacitance, CCLL
Largest when Largest when CCL L = 0= 0 Reference: M. A. Ortega and J. Figueras, Reference: M. A. Ortega and J. Figueras,
“Short Circuit Power Modeling in “Short Circuit Power Modeling in Submicron CMOS,” Submicron CMOS,” PATMOS PATMOS ’96, Aug. ’96, Aug. 1996, pp. 147-166.1996, pp. 147-166.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 15
Short-Circuit Energy per Short-Circuit Energy per TransitionTransition
EEscf scf == ∫∫tBtB
ttE E VVDDDD i iscsc((tt))dt dt
== ((ttEE – t – tBB)) I Iscmaxf scmaxf VVDD DD / / 22
EEscfscf == ttff ((VVDD DD - - ||VVTpTp|| - V- VTnTn)) I Iscmaxf scmaxf / / 22
EEscrscr == ttrr ((VVDD DD - - ||VVTpTp|| - V - VTnTn)) I Iscmaxr scmaxr / / 22
EEscfscf = = EEscrscr == 0,0, when V when VDDDD = |= |VVTpTp|| ++ V VTnTn
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 16
Short-Circuit EnergyShort-Circuit Energy
Increases with rise and fall times of Increases with rise and fall times of inputinput
Decreases for larger output load Decreases for larger output load capacitancecapacitance
Decreases and eventually becomes Decreases and eventually becomes zero when zero when VVDDDD is scaled down but the is scaled down but the
threshold voltages are not scaled threshold voltages are not scaled downdown
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 17
Short-Circuit Power Short-Circuit Power CalculationCalculation
Assume equal rise and fall timesAssume equal rise and fall times Model input-output capacitive coupling Model input-output capacitive coupling
(Miller capacitance)(Miller capacitance) Use a spice model for transistorsUse a spice model for transistors
T. Sakurai and A. Newton, “Alpha-power T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to Law MOSFET model and Its Application to a CMOS Inverter,” a CMOS Inverter,” IEEE J. Solid State IEEE J. Solid State CircuitsCircuits, vol. 25, April 1990, pp. 584-594., vol. 25, April 1990, pp. 584-594.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 18
Short Circuit PowerShort Circuit Power
Psc = α fck Esc
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 19
PPscsc, Rise Time and , Rise Time and CapacitanceCapacitance
VVDDDD
GroundGround
CL
Ron
R = large
vi (t) vo(t) ic(t)+isc(t)
tftr vo(t)───
R↑
vo(t)
VVDDDD
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 20
iiscsc, Rise Time and , Rise Time and CapacitanceCapacitance
-tVDD[1- exp(─────)]
vo(t) R↓(t) CIsc(t) = ──── = ──────────────
R↑(t) R↑(t)
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 21
iiscmaxscmax, Rise Time and Capacitance, Rise Time and Capacitance
Small C Large C
tf
1────R↑(t)
iscmax
vo(t) vo(t)
i
t
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 22
PPscsc, Rise Times, Capacitance, Rise Times, Capacitance For given input rise and fall times For given input rise and fall times
short circuit power decreases as short circuit power decreases as output capacitance increases.output capacitance increases.
Short circuit power increases with Short circuit power increases with increase of input rise and fall times.increase of input rise and fall times.
Short circuit power is reduced if Short circuit power is reduced if output rise and fall times are smaller output rise and fall times are smaller than the input rise and fall times.than the input rise and fall times.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 23
Summary: Short-Circuit Summary: Short-Circuit PowerPower
Short-circuit power is consumed by each Short-circuit power is consumed by each transition (increases with input transition transition (increases with input transition time).time).
Reduction requires that gate output Reduction requires that gate output transition should not be faster than the input transition should not be faster than the input transition (faster gates can consume more transition (faster gates can consume more short-circuit power).short-circuit power).
Increasing the output load capacitance Increasing the output load capacitance reduces short-circuit power.reduces short-circuit power.
Scaling down of supply voltage with respect Scaling down of supply voltage with respect to threshold voltages reduces short-circuit to threshold voltages reduces short-circuit power; completely eliminated when power; completely eliminated when VVDD DD ≤ |≤ |VVtptp|+|+VVtntn . .
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 24
Components of PowerComponents of Power
DynamicDynamic Signal transitionsSignal transitions
Logic activityLogic activity GlitchesGlitches
Short-circuitShort-circuit StaticStatic
LeakageLeakage
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 25
Leakage PowerLeakage Power
IG
ID
Isub
IPT
IGIDL
n+ n+
GroundVDD
RDrainSource
Gate
Bulk Si (p)
nMOS Transistor
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 26
Leakage Current Leakage Current ComponentsComponents Subthreshold conduction, Subthreshold conduction, IIsubsub
Reverse bias pn junction conduction, Reverse bias pn junction conduction, IIDD Gate induced drain leakage, Gate induced drain leakage, IIGIDLGIDL due to due to
tunneling at the gate-drain overlaptunneling at the gate-drain overlap Drain source punchthrough, Drain source punchthrough, IIPTPT due to due to
short channel and high drain-source short channel and high drain-source voltagevoltage
Gate tunneling, Gate tunneling, IIGG through thin oxide; through thin oxide;
may become significant with scalingmay become significant with scaling
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 27
Subthreshold CurrentSubthreshold Current
Isub = μ0 Cox (W/L) Vt2 exp{(VGS –VTH ) / nVt }
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel lengthW: gate widthVt = kT/q: thermal voltage
n: a technology parameter
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 28
IIDSDS for Short Channel Devicefor Short Channel Device
Isub= μ0 Cox(W/L)Vt2 exp{(VGS –VTH + ηVDS)/nVt}
VDS = drain to source voltage
η: a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 29
Increased Subthreshold LeakageIncreased Subthreshold Leakage
0 VTH’ VTH
Log
(Dra
in c
urre
nt)
Gate voltage
Scaled device
Ic
Isub
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 30
Summary: Leakage PowerSummary: Leakage Power Leakage power as a fraction of the total power Leakage power as a fraction of the total power
increases as clock frequency drops. increases as clock frequency drops. Turning Turning supply off in unused parts can save powersupply off in unused parts can save power..
For a gate it is a small fraction of the total For a gate it is a small fraction of the total power; it can be significant for very large power; it can be significant for very large circuits.circuits.
Scaling down features requires lowering the Scaling down features requires lowering the threshold voltage, which increases leakage threshold voltage, which increases leakage power; roughly doubles with each shrinking.power; roughly doubles with each shrinking.
Multiple-threshold devices are used to reduce Multiple-threshold devices are used to reduce leakage power.leakage power.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 31
Technology ScalingTechnology Scaling
Scaling down 0.7 micron by factors 2 Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron and 4 leads to 0.35 and 0.17 micron technologiestechnologies
Constant electric field assumedConstant electric field assumed
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 32
Constant Electric Field Constant Electric Field ScalingScaling
B. Davari, R. H. Dennard and G. G. B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Shahidi, “CMOS Scaling for High Performance and Low Power—The Performance and Low Power—The Next Ten Years,” Next Ten Years,” Proc. IEEEProc. IEEE, April , April 1995, pp. 595-606.1995, pp. 595-606.
Other forms of scaling are referred to Other forms of scaling are referred to as constant-voltage and quasi-as constant-voltage and quasi-constant-voltage.constant-voltage.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 33
Bulk nMOSFETBulk nMOSFET
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 34
Technology ScalingTechnology Scaling A scaling factor (A scaling factor (S S ) reduces device dimensions ) reduces device dimensions
as 1/as 1/SS.. Successive generations of technology have Successive generations of technology have
used a scaling used a scaling S S = = √2√2, doubling the number of , doubling the number of transistors per unit area. This produced 0.25transistors per unit area. This produced 0.25μμ, , 0.180.18μμ, 0.13, 0.13μμ, 90nm and 65nm technologies, , 90nm and 65nm technologies, continuing on to 45nm and 30nm.continuing on to 45nm and 30nm.
A 5% gate shrink (A 5% gate shrink (SS = 1.05) is commonly = 1.05) is commonly applied to boost speed as the process matures.applied to boost speed as the process matures.
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston:Pearson Addison-Wesley, 2005, Section 4.9.1.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 35
Constant Electric Field Constant Electric Field ScalingScaling
Device ParameterDevice Parameter ScalingScaling
Length, Length, LL 1/1/SS
Width, Width, WW 1/1/SS
Gate oxide thickness, Gate oxide thickness, ttoxox 1/1/SS
Supply voltage, Supply voltage, VVDDDD 1/1/SS
Threshold voltages, Threshold voltages, VVtntn, V, Vtptp 1/1/SS
Substrate doping, Substrate doping, NNAA SS
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 36
Constant Electric Field Scaling Constant Electric Field Scaling (Cont.)(Cont.)
Device CharacteristicDevice Characteristic ScalinScalingg
ββ W / W / ((L tL toxox)) SS
Current, Current, IIdsds ββ ((VVDDDD – V – Vt t ) ) 22 1/1/SS
Resistance, Resistance, RR VVDD DD / I/ Idsds 11
Gate capacitance, Gate capacitance, CC W L / tW L / toxox 1/1/SS
Gate delay, Gate delay, ττ RCRC 1/1/SS
Clock frequency, Clock frequency, ff 11/ / ττ SS
Dynamic power per gate,Dynamic power per gate, P P CV CV 2 2 ff 1/1/S S 22
Chip area,Chip area, A A 1/1/S S 22
Power densityPower density P/AP/A 11
Current densityCurrent density IIds ds /A/A SS
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 37
Problem: A Design ExampleProblem: A Design Example A battery-operated 65nm digital CMOS device is A battery-operated 65nm digital CMOS device is
found to consume equal amounts (found to consume equal amounts (P P ) of dynamic ) of dynamic power and leakage power while the short-circuit power and leakage power while the short-circuit power is negligible. The energy consumed by a power is negligible. The energy consumed by a computing task, that takes computing task, that takes TT seconds, is 2 seconds, is 2PTPT. .
Compare two power reduction strategies for Compare two power reduction strategies for extending the battery life:extending the battery life:
A.A. Clock frequency is reduced to half, keeping all other Clock frequency is reduced to half, keeping all other parameters constant.parameters constant.
B.B. Supply voltage is reduced to half. This slows the gates Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the leakage current is held unchanged by modifying the design of transistors.design of transistors.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 38
Solution: Part A. Clock Solution: Part A. Clock Frequency ReductionFrequency Reduction
Reducing the clock frequency will reduce Reducing the clock frequency will reduce dynamic power to dynamic power to P P / 2, keep the static / 2, keep the static power the same as power the same as PP, and double the , and double the execution time of the task. execution time of the task.
Energy consumption for the task will be,Energy consumption for the task will be,
Energy = (Energy = (P P / 2 + / 2 + P P ) 2) 2TT = 3 = 3PTPT
which is greater than the original which is greater than the original 22PT.PT.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 39
Solution: Part B. Supply Voltage Solution: Part B. Supply Voltage ReductionReduction
When the supply voltage and clock frequency When the supply voltage and clock frequency are reduced to half their values, dynamic are reduced to half their values, dynamic power is reduced to power is reduced to P P / 8 and static power to / 8 and static power to P P / 2. The time of task is doubled and the / 2. The time of task is doubled and the total energy consumption is,total energy consumption is,
Energy = (Energy = (P P / 8 + / 8 + P P / 2) 2/ 2) 2TT = 5 = 5PT PT / 4 =1.25/ 4 =1.25PTPT The voltage reduction strategy reduces The voltage reduction strategy reduces
energy consumption while a simple energy consumption while a simple frequency reduction consumes more energy.frequency reduction consumes more energy.