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8/8/2019 Low Power Cmos Circuit Design 1
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BYC.RADHIKA
09VL03F
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IntroductionFactors of power dissipation in cmos
Techniques to reduce powerdissipationAdvantages
DisadvantagesConclusion
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INTRODUCTIONINTRODUCTION
Need for low power VLSI design Scale of integration
Density Operating frequency Demand for portable electronic
devices
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Charging and discharging
capacitanceShort circuit currentLeakage current
Static current
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Power dissipated per clockcycle=cl*v Power dissipated by multiple
capacitors=ctotal*v*f
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SHORT CIRCUIT CURRENT OF ANINVERTER:
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Large output capacitanceLess short circuit current andhigh total current
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As slope increases current envelopwidth and peak increasesHigh input slope better
performance
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Parasitic effect of bulk of cmosCurrent equation: Ir=Is(exp(v/vth)-1)
Order of pA/mDynamic current per an inverter :in order of A
Depends on temperature , junctionarea
REVERSE BIASED PN JUNCTION
CURRENT:
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SUBTHRESHOLD CHANNEL LEAKAGE
CURRENT:VGS
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Limiting factor in low voltage andlow power chip designIsub=I0*exp((vgs-vth)/(vth))Depends on Vgs,Vds,temperature
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Peudo NMOS logicEfficient area usageTrade off between power and
area
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Reduce switching voltage P=CVfNoise immunity
Reduce capacitance(possible atmaterial , physical design , circuittechniques)
Reduce switching frequencyAlternate logic implementationCoding methods , counting
sequence , data representation
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For dynamic power reductionSame as area reductionSmall size gates
GainFor leakage power reductionVaries with Vth , channel length
Depends on logic stateTrade off for speed