Teehology for the 1000

ma EngineerA technical journal published by theRCA Technical Excellence Center 0 13 Roszel Road 0 P. 0. Box 432 0 Princeton, NJ 08540-0432 ID Tacnet: 226-3090

RCA Engineer Staff

Tom King Editor

Mike Lynch Associate Editor

Louise Carr Art Editor

Rosemarie Cruz Editorial Assistant/Composition Specialist

Maria Pragliola Secretary

Editorial Advisory Board

Tony Bianculli Manager, Engineering Information, TechnicalExcellence Center 0 Jay Brandinger Staff Vice -President,Engineering, Electronic Products and Technology 0 FrankBurris Director, Technical Excellence Center 0 JimCarnes Division Vice -President, Engineering, ConsumerElectronics 0 John Christopher Vice -President, Technical

Operations, RCA Americom 0 Jim Feller Division Vice -President, Technology, Aerospace and Defense 0 MahlonFisher Division Vice -President, Engineering, Video Component &Display Division 0 Larry Gallace Division Vice -President,Product Assurance and Environmental Engineering, Solid StateDivision 0 Arch Luther Senior Staff Scientist, RCALaboratories 0 Bill Webster Vice -President and SeniorTechnical Advisor, Electronic Products and Technology

Consulting Editors

Ed Burke Administrator, Marketing Information and Commun-ications, Aerospace and Defense 0 Walt Dennen Manager,Naval Systems Department Communications and Information,Missile and Surface Radar 0 John Phillips Director, BusinessDevelopment and Services, RCA Service Company

LELIWI Engineer

Cover design and illustration by John Duffy,Advanced Technology Laboratories

Our cover, we believe, aptly characterizes the subject matterof the articles in this issue-simplicity, power, and elegance.

0 To serve as a medium of interchange of technicalinformation among various groups at RCA 0 To create acommunity of engineering interest within the company bystressing the interrelated nature of all contributions 0 Todisseminate to RCA engineers technical information ofprofessional value 0 To publish in an appropriate mannerimportant technical developments at RCA, and the role of theengineer 0 To help publicize engineering achievements in amanner that will promote the interests and reputation of RCAin the engineering field 0 To provide a convenient means bywhich the RCA engineer may review professional work beforeassociates and engineering management 0 To announceoutstanding and unusual achievements of RCA engineers ina manner most likely to enhance their prestige andprofessional status.

Technology for future -generation defense systems

To a technologist concernedwith electronics in its broadestsense, today's environmentpresents more challenges andis more exciting than hasbeen the case for a long time.This situation is a result, inpart, of recent major advancesin computer power, speed,and cost reduction. In parallelwith this, the DoD has takenon a technologically veryaggressive strategy to

accelerate the rate of advancement. The examples are clear.The VHSIC (Very High Speed Integrated Circuits) program is

providing computers on a single chip with clock cycle times of40 nanoseconds or less. The DARPA (Defense AdvancedResearch Project Agency) -sponsored gallium arsenide (GaAs)program is attempting to lower this by another order ofmagnitude. The potential for this performance at the devicelevel has made possible whole new concepts in computersystems. The Strategic Computer Initiative (SCI) routinely talksabout computers that operate at about one GFLOPS (109floating point operations per second). The Japanese FifthGeneration Computer program has similar objectives. BothSCI and Fifth Generation programs involve new architecturesand computing concepts. The advanced signal and dataprocessors from these programs will support new strategicsystems requirements. The Strategic Defense Initiative, forexample, will need computing power orders of magnitudebeyond what is commonly available today. Radar systems thathave to deal with Stealth technology will need super -robustsignal processors. Spaceborne sensors at all wavelengthsfrom radar through the visible spectrum bring with themmassive system signal processing requirements. The imagerydata from such sensors will require huge data link bandwidthcapabilities and signal processors that have yet to bedeveloped for near real-time operations.

The advanced computer capabilities also enable an entirelynew class of "intelligent" systems. Computing machines andsystems of the future will have the power to mimic human -likeattributes to better interface with the human operator and torelieve the human of burdensome tasks. This general conceptis viewed by many as "artificial intelligence." Current applica-tions include vision systems for object/target recognition,expert systems that capture and exploit expert knowledge,speech recognition and natural language machine processing,and advanced tactile sensors for robotic systems.

The conclusion is clear: There are numerous high -potential opportunities for the application of electronicstechnology to defense systems over the next several years.

The Advanced Technology Laboratories (ATL) has a historyof providing applications of new electronics technology to theAerospace and Defense businesses of RCA. A few notable

examples from the recent past are narrowband and widebandvoice terminals for secure communications, high-speed andhigh -capacity optical storage systems in a jukeboxconfiguration, and the ATMAC special-purposemicroprocessor for signal processing. Similar activity iscontinuing today. In fact, the range of technologies beingexplored and developed in ATL today is broader than everbefore.

ATL's current programs range from the development ofadvanced microelectronic devices to architectural conceptsthat are critical for high-level systems. The programsrepresent a good match with the challenges and opportunitiespresented by today's environment. From a system complexityperspective, the highest level is intelligent or "human -like"machine interfaces. To address this level, ATL programs existin digital image processing for vision systems, imageunderstanding and target classification; in speech recognitionfor speaker verification, word cueing, and improved man -machine interfaces; in artificial intelligence for expert systems,natural language processing, and data fusion in support ofcommand and control requirements; and in robotics tointegrate vision, speech, Al, and tactile -sensors to supportautonomous space -based maintenance requirements Onelevel down in complexity is advanced computer concepts forsignal and data processing. To address this level, ATLprograms exist in advanced signal processing architecture tosupport radar, sonar, and image processing; in softwareengineering to support parallel processing needs andsoftware development tools; in microprocessor/chiparchitecture to support custom VLSI system needs; and inoptical storage to provide online storage systems forsupercomputer systems. Finally, at the lowest level ofcomplexity, there are programs in device technology. ATL isinvolved with VLSI design and related CAD tools to enable thedevelopment of the large VHSIC-class devices; with IRCCDsto build sensor subsystems for trackers, physical security, and .surveillance; with laser diodes to build optically -activatedswitches and high -efficiency spaceborne laser sources; andwith both silicon (CMOS) and GaAs technology for high-speedand radiation -hardened applications.

The articles in this issue represent a cross section of ATLprograms, from device technology to examples of intelligentsystems. They reflect the confidence and competence withwhich ATL and other RCA business units are responding tothe challenges of today's environment.

Ronald A. AndrewsStaff Vice PresidentAdvanced Technology Laboratories

speech recognition

MiCEM EngineerVol. 31 INo. Jan. I Feb. 1986

4 Acoustic phonetic techniques for future automatic speechrecognition systemsD.E. Graff 1T.E. Lynch

sensors 11 Advanced technology for future imaging sensorsF.B. Warren

image technology 18 Automatic classification of ship targetsF.C. Luce W.B.1 Schaming

laser technology 24 Laser development and applicationsD. Wille IA. Rosen

robotics 29 Advanced robotics projects at ATL for remote servicingP.B. Pierson

mail processing 35 Advanced technology for mail processing in the 1990sF. Alexander IR. McClain IC. Tsikos B. Siryj 1R.M. Carrell

optical recording 46 Optical storage for high performance applications-the late 1980sand beyondW.P. Altman 1G.M. Claffie 1M.L. Levene

software 56 Verlangen: Formally verifying system designsD.E. Britton

61 Ada software development toolsG.W. Mebus L.T. Armstrong 1H. Rosenthal

65 Leonardo: Design environment of the 1990sE.J. Conklin

68 Artificial intelligence applicationsJ.A. Adams 1M. Gale 1J.W. Dempsey 1G.W. Kaizar N. Straguzzi

microelectronics 76 The design and construction of a GaAs technology demonstrationmicroprocessorW.A. Helbig 1R.H. Schellack 1R.M. Zieger

81 A new methodology reduces design time for very large application -specific integrated circuits (ASICs)A. Feller

departments Patents, 86 I Pen and Podium, 871News and Highlights, 88Copyright © 1986 RCA CorporationAll rights reserved

in this issue . . .

technology for the 1990s

Graff/Lynch: "Our primary effort is to develop acoustic -phonetictechniques that will permit the probabilistic segmentation of an inpututterance into its constituent phones."

Warren: "RCA has been a leader in CCD technology for the pastdecade, and this leadership has enabled unique contributions to bothvisible and IR sensors."

Luce/Schaming: "The final goal of the project is to produce "flyable"hardware including an infrared sensor that will automatically detect andclassify a target and make several tactical decisions in flight."

Wille/Rosen: "The pumping mechanism ensures that there are moreatoms in the higher energy state than in the lower energy state, so gainoccurs."

Pierson: "To increase the capabilites of distant robotic servicingsystems, we must develop predictive feedback techniques or give therobot increased autonomy."

Alexander et al.: "The apparent ease with which humans interpretthe many elements of a scene conceals the great complexity of theprocesses involved."

Altman/Claffie/Levene: " . the Space Station, to be launched inthe early 1990s, is expected to generate 1 terabyte of data per day atdata rates that can exceed 1 gigabit per second."

Britton: "Verlangen is appropriate for many kinds of computersystems, including distributed systems, communications networks, andoperating systems."

Mebus/Armstrong/Rosenthal: "As far as the DoD is concerned, theAda language is definitely the software systems language of the future."

Conklin: "Because a team of experts usually develops these systems,we will exploit the team approach to maximize the advantages it offersin design efficiency and quality."

Adams et al.: "Computer -based expert systems provide the meansto capture such diagnostic expertise from a few human experts, andthen to make this knowledge available to others who have lessexperience."

4

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11 [Fact 1 and Fact 2 and Not Fact 31 then .Conclusion A

Helbig /Schellack/Zieger: "Improvements with GaAs processingtechnology are occurring at a rate that is three times what occurred insilicon processing during the 1970s and early 1980s."

Feller: "Current design VLSI methodologies, based on past LSI oreven MSI design approaches, are responsible for excessively longdesign times."

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D.E. Graff T.E. Lynch

Acoustic phonetic techniques for future automaticspeech recognition systems

The closer we look at automatic speech recognition systems,the more we realize just how complex the human interpretationand filtering system is.

Ideally, an automatic speech recogni-tion system (ASR) should respond toany spoken word from any speaker.However, despite active research inindustry and academia over the past 30years, this goal does not seem achievablein the near future.

Most current ASR systems, afterbeing "trained" by the intended user,can recognize only a limited number ofwords (fewer than 300) spoken in isola-tion. Unfortunately, the techniques usedin these primitive ASR systems havelimited potential. We must develop newtechniques before automatic speech rec-ognition can become a viable technol-ogy.

Abstract: At RCA's AdvancedTechnology Laboratories, we are

pursuing fundamental research inautomatic speech recognition (ASR),concentrating on acoustic phonetics.We are also particularly concerned withdeveloping techniques that can be usedin future ASR systems. Our research isperformed in conjuntion with theUniversity of Pennsylvania LinguisticsLaboratory under an Air Forcecontract (F30602 -84-C-0065). Thiseffort parallels the current DARPAASR work, although the two programsare not directly connected.01986 RCA Corporation.Final Manuscript received November 20, 1985Reprint RE -31-1-1

Scope of the ASR problem

To achieve an ideal ASR system fromcurrent technology, we need to extendthe state-of-the-art in several directions.Some of them are depicted in Fig. 1.

First, the system must becomespeaker -independent. At present, mostcurrent systems can handle one speakerat a time, and that speaker must providetraining models for each word that is tobe recognized. This training process isvery time consuming and tedious. Whenseveral thousand words are to be recog-nized, the task is prohibitive.

On the other hand, a speaker -independent system could handle anyspeaker, and thus we could bypass thetraining process for each individualspeaker. To achieve good performance,the system should be made aware of thespeaker's voice characteristics (averagepitch, vowel patterns, etc.), but it canlearn these characteristics much fasterfrom estimates than by training eachword model separately. Also, a speaker -independent system could adapt to aspeaker over time.

Next, we must extend the vocabulary

Fig. 1. Three dimensions of automatic speech recognition complexity. The solid circlesrepresent existing technology

4 RCA Engineer 31-1 Jan / Feb 1986

from current limitations to a size suit-able for the desired task. For instance, avoice input typewriter ("talking type-writer," or "talkwriter") would need avocabulary of several thousand words,whereas a fighter cockpit function mayrequire only a few hundred.

Most current ASR systems representeach word in the vocabulary as anacoustic model of the entire word. Forvocabularies of several thousand words,the storage and pattern -matching com-putation requirements become prohibi-tive. English words can be separatedinto a finite number of smaller units,called phonemes (see Fig. 2). We couldmodel each word as its phoneme string,with some rules for phoneme interac-tions both within words and at wordboundaries (co -articulation).

Thus, a more reasonable approach isfirst to model the "phones" acousticallyand then to model each word as thecomposite of its phones, with acousticrules at phone boundaries. (A phone isthe acoustic realization of the pho-neme).

Third, we must extend the speechstyle that the ASR system requires fromwords spoken in isolation (discretespeech) to words spoken more naturally(connected speech). However, it maynot be possible to handle totally "natu-ral" speech (How 'bout dem Dawgs?),and we may require some degree of care-ful articulation by the speaker.

Restricted grammar is a related topic.Currently, most ASR systems requirethe user to speak within a constrainedsyntax (see Fig. 3). The alternative is toallow conventional spoken Englishgrammar. However, such an unre-stricted syntax requires an artificialintelligence (AI) interpreter to interpretthe message, and is not a major focus ofour effort. Figure 4 depicts some formsof speech that could be used as input toan ASR system. Other factors thataffect ASR include noise, channel, andhuman factors, but these too are not ofprimary concern in our research.

ATL ASR research

RCA's Advanced Technology Laborato-ries (ATL) is engaged in fundamentalresearch focused on developing future,speaker -independent connected -speech(SICS) ASR systems with a medium tolarge vocabulary (greater than 200words). Our primary effort is to developacoustic -phonetic techniques that will

PHONEMES

SONORANTS

OBSTRUENTS

(TURBULENCE EXCITATION AT VOCALTRACT OBSTRUCTION)

VOWELS VOICED

WHISPERFRONT MID BACK STOPS AFFRICATES FRICATIVES

I (BT)T)I

BAI(BM

T)a ((BET)

all (BAT)

) (BIRD)

a (BUT)

u (BOAT)U (FOOT'o(BOAT)

a (HOT)

./ (BOUGHT)

b.d.g dz (JOURNAL) V (VOICE)

(T(THEN)-Z (ZOO)

(AZURE)

h

DIPTHONGS

FRONT GLIDING BACK GLIDING UNVOICED

STOPS AFFRICATES FRICATIVESal (BUY)

)I (BOY)

el (BAY)

aU (HOW)

oU (BOW)

ill (YOU)

p.t.k ti (CATCH) F (FINE)

0 (THIN)

S (SEE)

(SHUN)CONSONANTAL SONORANTS

LIQUIDS GLIDES NASALS

Fi,e y (1E7)w (WERE)

m.n

g (RING)

Fig. 2. The phonemes of American English. Glides, liquids, and nasals are produced withsome vocal tract obstruction, but are generated by vocal cord vibrations. Voiced fricativescombine vocal cord (glottalic) and obstruent (turbulence) excitations.

A SIMPLE STAMP VENDING VOCABULARY (CONSTRAINED) SYNTAX

"CENT"

"DOLLAR" "STAMPS"

A "TWENTY", "THIRTY", .., "NINETY" 35 WORD VOCABULARYB "TEN," "ELEVEN", . , "NINETEEN"

e.g."PLEASE GIVE ME TWENTY-FIVE FIFTEEN CENT STAMPS"

-PLEASE"

Fig. 3. A simple stamp -vending vocabulary with constrained syntax.

Discrete (words spoken in isolation)"Give" (pause) "me" (pause) "twenty" (pause) ...

Connected (no pause, but words articulated as if in isolation)"Give me twenty-five fifteen -cent stamps"

Continuous (words run together with coarticulation, but carefully spoken)"Give me twenty-five fifteen -cent stamps"

Continuous/Loose Syntax (syntax constraints removed)"I want twenty-five of those fifteen cent postage stamps"

Natural Speech"How bou' givin' me a cuppla doz twenny cen' stamps"

Fig. 4. The progression from discrete speech to natural speech.

permit the probabilistic segmentation ofan input utterance into its constituentphones. We have also directed someeffort to developing recognition algo-rithms for determinating the originalword sequence from the segmentedphones. We are not concerned with howthe resulting word sequence is inter-preted, leaving such problems to futureAI work.

Will true speaker -independent auto-matic speech recognition ever become aviable technology? Certainly that ques-tion clouds all work being done in thisfield. For instance, in some urban dia-lects of the Great Lakes region, theword "locks" is pronounced identicallyto a Philadelphia area "lax." Thus, noASR system could distinguish betweenthe two words absolutely without con -

Graff (Lynch : Acoustic phonetic techniques for future automatic speech recognition systems 5

EPARAMETERXTRACTION

SPEECH /AD.

A

V

PARAMETEREXTRACTOR

/ACOUSTICPHONETICKNOWLEDGE

40.1PARAMETERS/-00-

CONTROL MODULES

DATA FILES

-COMPUTATION MODULES

-KNOWLEDGE BASES

PHONESEGMENTATIONDISCRIMINATION

SEGMENTERDISCRIMINATOR

/LANGUAGE\

MODEL

/NETWORKNE TWORK

/CONSEQUENCEMODEL

COMPARATOR

IRECOGNITION/CANDIDATES

DECISION

/ ACTION /

Fig. 5. Phonetic recognition system.

text or speaker -dependent information.Furthermore, we do not find it desir-

able to handicap system performance soseverely when it is relatively easy toinform the system about the speaker'svowel characteristics and other dialect(or ideolect) information.

Thus, we focused our acoustic -phonetic research on finding speaker -independent speech attributes and asmall set of parameters that can be easilyadjusted to an individual speaker.Whether we achieve true speaker -independent ASR or not, whatever welearn in this area can be applied tospeaker -independent and speaker -adaptive systems.

ASR model

Figure 5 depicts our automatic speechrecognition system model, which con-sists of four modules: parameter extrac-tion, phone segmentation/discrimin-ation, word string recognition, and rec-ognition decision.

Parameter extraction processes inputspeech to produce parameters thatlocally characterize the incoming utter-ance. In human hearing, the cochlea(part of the inner ear) does the first stage

of parameter extraction. This stage con-sists (roughly) of a time series of spectralamplitude information derived from afilter bank (the basilar membrane,which is part of the cochlea).

Our parameter extraction consistsprimarily of a time series of spectralamplitude information that we obtainedfrom a "critical -band" filter bank (arough approximation of the basilarmembrane), and more direct informa-tion about peaks in the spectrum (for-mants). The novelty of our parameterextraction is that we do the analysis in apitch -synchronous manner, which isdescribed in the next section.

Phone segmentation/discriminationuses the parameter array to segment (intime) the incoming utterance intophones and then identify each phone(phone discrimination). Segmentationand discrimination are done on a proba-bilistic basis. For instance, if we find astop consonant but cannot absolutelydetermine if it is to be a /p/, /t/, or /k/,then we maintain the three candidates aswell as their relative likelihoods.

Word string recognition takes theprobabilistic output of the phonesegmenter/discriminator and, workingfrom the language model (vocabulary

and syntax), recovers the likely recon-structed word strings. We have devel-oped an algorithm to do this recognitionusing the probabilistic output of thephone segmenter/discriminator asinput.

Finally, the consequence model isused to decide if the resulting wordstring makes sense and if the likelihoodof a correct recognition is enough totake action or should be verified. Thisfalls in the realm of AI or operationsresearch, and again is not one of ourfocuses.

Note that our model has three know-ledge bases that contain:

o Acoustic/phonetic information (usedin the phone segmentation/discrimi-nation process).

o Language information (vocabularyand syntax models used in wordstring recognition).

o A consequence model (used in decid-ing what to do after recognition).

Further, most modules are interactive.To resolve a word -recognition ambi-guity, the recognition module couldrequest a more careful analysis from thesegmentation/discrimination modulethat could, in turn, request finer param-

6 RCA Engineer 31-1 Jan. / Feb. 1986

BROADFILTERBANK

100-5000 Hz

3000-5000 Hz

1850-3000 Hz

300-1850 Hz

100-300 Hz

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inulintilluilintnimiumlitmintiminikinnii Himiniiiimillinimlionimillionimmuilmilmil:ninepowilimunitimailliiilimilimmillithiroilinniinjoinoulintioullonimlimintiliii

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lonoloomoluotoonlolnhomettillimteeeltammellieste..1.1.meelunm..6.1.m.loneentelrenorleo nmoubee llllll hoe

4 5 6`E' 'M' 'G'

Fig. 6. Filter bank structure of the utterance "J -R -E -M -G."

eter extraction over a segment of theinput speech. Thus, as Fig. 5 shows,lines of control lead right -to -left andlines of data flow left -to -right; so wecan use both top -down and bottom -upprocessing. In particular, blackboardparadigms and other AI decision tech-niques fit in this model.

Parameter extraction

We generate speech sounds either byperiodic vibrations of the vocal cords(sonorants: vowels, nasals, glides, etc.)or by turbulence near an obstruction inthe vocal tract (obstruents: /5/, If/, /p/,etc.). The sonorants include vowels(beet, bat), dipthongs (boy), glides (we),liquids (red, led), and nasals (bean,beam). The obstruents include stops(beet, peat), fricatives (seat), affricates(cheat), and whisper (heat). Figure 2contains a complete list of these speechsounds.

The obstruents, created by turbu-lence, are noiselike and have their prin-cipal frequency components in theupper frequency range (greater than2000 Hz). They can change rapidly in

time (stop releases), and therefore arebest analyzed with a small time window(less than 5 milliseconds) spectral analy-sis that is computed frequently (at leastevery 5 milliseconds). Thus, in obstru-ent regions, our spectral analysis is doneusing 5 -millisecond effective time win-dows that are computed every 5 milli-seconds.

The sonorants are more difficult totreat, because the results of the spec-trum analysis depend on the position ofthe spectral -analysis window withrespect to the pitch pulse. The classicalway around this problem is to adopt awide window (20 to 30 milliseconds)that will contain several pitch pulses andthen smooth the effects of the individualpitch pulses.

Our approach is to adopt a very nar-row window (5 -millisecond effectivewidth) and place it the window directlyover the pitch pulse for each pitchperiod. This requires a reliable pitchtracker that can accurately locate thepitch -pulse for each vocal cord vibra-tion. Our pitch tracker has proven to beremarkably robust and the resultingspectral analysis tracks the spectral

movement very finely and with excellentstability, considering the short analysiswindows involved.

Figures 6 through 8 illustrate ourparameter extraction. The utterance inFigs. 6 and 7 is the sequence of letters,"J -R -E -M -G." Figure 6 presents theenergy structure over several energybands, and Fig. 7 indicates the formantstructures, computed in a pitch -synchronous manner. Formants corres-pond to the passbands in the vocal tract(viewing the vocal tract as a bandpassfilter). Notice that the formants occur invoiced regions and that the lowest twoformants characterize the vowel beingspoken. In particular, the formant pat-terns in "E" and "G" are roughly thesame because they represent the "ee"sound. Figure 8 shows the formant pat-tern for the word "are". Notice the for-mant movements.

Phone segmentation/discrimination

Ideally, a phone segmentation/discrimi-nation module would decode an input -utterance waveform into its underlyingphonemes. Then, with some clever

Graff ILynch: Acoustic phonetic techniques for future automatic speech recognition systems 7

SPECTRALPEAKS(KHz)

ENERGY

WAVEFORM

1)

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I 110111

5 KHz

4 KHz

3 KHz

- 2 KHz

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, V \ /1\7 100 MS

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dmomohelowilen ,,,,,,

'R'3 4

'E'

olonmeolitm.Ammiel. .1116mmelem ,,,,, 6.mllemmiltmmA

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Fig. 7. Formant structure of the utterance "J -R -E -M -G." Note the clear formant structure inthe vocalic regions.

SPECTRALPEAKS(KHz)

ENERGY

WAVEFORM

6

51111111111-1

4 I

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F1/F2

MUM' J

F5

F2

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Fl

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Fig. 8. Formant structure for the word "are." Note the f 1 /f2 merger diverging into a f2/f3merger as the low back vowel (ah) makes the transition to the retroflexed liquid &I

string-matching and a good dictionary,it could recover the underlying message(although it might not be able to distin-guish "six sheep" from "sick sheep").

However, even humans are not ableto decipher absolutely the phonetic con-tent of things they hear. Therefore, weneeded a hierarchical, probabilisticmodel for a speech understanding/decoding technique. Some acousticevents, such as silence or strong vowels,can be distinguished reliably and canserve as "islands of certainty" aroundwhich segmentation proceeds.

In our system, we initially segmentthe utterance into regions: stronglyvoiced (sonorant), strongly unvoiced(silence, frication), and intermediate(devoiced sonorants, voiced fricatives,or transitions). In the strongly voicedregions, we find likely strong vowelregions. In the strongly unvoicedregions, we differentiate silence fromfrication. We then subdivide the regionsuntil all segment candidates in theincoming utterance are labeled.

Discrimination then attempts toassign a phone label to each segment.

8 RCA Engineer 31-1 Jan. / Feb. 1986

For instance, if we determined a seg-ment to be a stop, then discriminationwould try to assign (/b/, /d/, /g/, /p/,/t/, /k/, or "flap") to the segment.

As mentioned previously, humans arecertainly not totally accurate in thephone segmentation/discriminationtask. In fact, our colleagues at the Uni-versity of Pennsylvania Linguistics Lab-oratory are currently measuring justhow well humans do certain phonesegmentation/discrimination tasks.This suggests that if we try phonesegmentation/discrimination, the re-sulting output should not be a linearsequence of labels, but rather a transi-tion network of phone labels and transi-tion probabilities. Figure 9 depicts a typ-ical local output.

Word string recognition

Even when given a linear sequence ofdecoded phone segment labels, extract-ing the underlying word string sequenceis difficult because of input errors insegmentation and labeling. Also, thesame word may be produced in severaldifferent ways and adjacent words caninteract acoustically at their boundaries(co -articulation).

For example, a southern speaker maysay "farm" either in the standard man-ner (with an /r/), or as "fahm," or any-thing in between. A common exampleof co -articulation is the conjunction ofthe words "did" and "you" to form"dija."

In our research, we have developed arecognition algorithm that permits com-paring probabilistic input transition net-works with statistically derived refer-ence transition networks. This algor-ithm incorporates compensations forsegmentation/discrimination "errors,"multiple pronunciations, and co -articulation. Like dynamic program-ming and string matching, our al-gorithm has a computational complex-ity that is roughly linear in relation tovocabulary size and grammatical com-plexity. Moreoever, our algorithm is anextension of dynamic programming andstring matching; it incorporates thesestrategies as special cases. However, anexposition on these topics is not possiblehere, so anyone interested in furtherinformation should contact the authors.

Current efforts

Figure 10 shows the acoustic/phoneticresearch modules being investigated

INPUT WORD: "CAN'T"

POSSIBLE INTERPRETATIONS: CAN'T 8000 LIKELIHOODCAT 10,0CAMP 1000

TRANSITION NETWORK:

/k/0

/ae/ '78 /n/ /1/

/m/ /p/0

0

Fig. 9. Construction of a probabilistic transition network from a probabilistic segmenter/discriminator.

DATABASECOLLECTION

DATABASE MANAGEMENTSYSTEM

DATABASEENTRY

PITCH EPOCHTRACKING

VOWELSPOTTING

PARAMETER

EXTRACTION

FORMANTTRACKING

SEGMENTATION PHONETIC VOWELCLASSIFICATION

I

PHONEMIC VOWELCLASSIFICATION

NASALCLASSIFICATION

GLIDE/LIQUID/FRICATIVECLASSIFICATION

STOPCLASSIFICATION

Fig. 10. Acoustic/phonetic research modules.

under the SICS contract. In our currentefforts we have identified stop discrimi-nation and vowel assignment as the twomost difficult acoustic -phonetic prob-lems in speaker -independent automaticspeech recognition.

Of these, stop discrimination is the

the most difficult acoustic problembecause no known reliably computablestatistics exist that will absolutely (oreven reasonably) discriminate amongstops. Through our robust, small time -window spectral analysis, we hope thatnew statistics will become computable

Graff/Lynch: Acoustic phonetic techniques for future automatic speech recognition systems 9

Thomas Lynch is a Senior Member of theEngineering Staff in ATL's Speech TechnologyLaboratory. He is working on the development ofadvanced speech recognition systems.Previously, he was involved with secure speechtransmission and modem softwaredevelopment. Prior to joining RCA in 1981, Dr.Lynch was at Verbex, where he concentratedhis efforts on automated recognition ofcontinuous speech. He received a PhD inMathematics from Massachusetts Institute ofTechnology and a BS in Mathematics from theUniversity of Georgia.

Lynch (left) and Graff.

David Graff is a Member of the EngineeringStaff at RCAs Advanced TechnologyLaboratories. He joined the Speech Processinggroup in 1983, participating immediately in theSpeaker -Independent Connected -Speech (SICS)program. He is currently working toward a PhDin Linguistics at the University of Pennsylvania,with a focus on change and variation inAmerican dialects. He received his BA inLinguistics from Pitzer College.Contact him at.Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6613

and allow more robust discriminationthan has been available.

Phonemic vowel assignment, whichmust be treated separately from the esti-mation of acoustic vowel quality, repre-sents the most difficult task speakerindependence faces. This results fromtwo essential facts about dialect varia-tion, already established by work at theUniversity of Pennsylvania.

First, dialects differ about where par-ticular vowels are located in the pho-netic space defined by the positions ofthe first two formants. (Consider theprevious example where "locks," aspronunced by some speakers in theGreat Lakes region, sounds like "lax"as pronounced by a Midlands speaker,or like a Bostonian's "larks"). Second,dialects differ in how many vowel pho-nemes are pronounced differently, as

well as how phonemes are distributed inthe vocabulary.

Most southerners do not differenti-ate "pin" and "pen" or "mint" and"meant," while the country seemsevenly divided between those who pro-nounce "cot" and "caught" or "hawk"and "hock" differently and those whodo not. In addition, those who do havethe latter distinction may differ in howthey apply it. For Bostonians, "bomb"has the vowel of "hawk," but for NewYorkers, it has the vowel of "hock".

We will examine this problem withspecial emphasis on how to encode aperson's vowel characteristics to permitbetter recogniton by an ASR system.

In parallel, the University of Pennsyl-vania Linguistics Laboratory will con-tinue to do research in human percep-tion, especially human capability

relating to stop discrimination and dia-lects. Their work on the human capacityto do segmentation and discriminationprovides useful information for devel-oping of automatic techniques.

SummaryAt ATL we are in the midst of a two-year project to do fundamental researchon topics relating to automatic speechrecognition. While we have done somework in recognition algorithms, our pri-mary emphasis has been on the develop-ment of new acoustic/phonetic tech-niques. Progress to date has been veryencouraging, although the ultimate use-fulness of our research may be severalyears away.

10 RCA Engineer 31-1 Jan. / Feb. 1986

F.B. Warren

Advanced technology for future imaging sensors

RCA's unique approach to building infrared sensors has apromising future.

A method for electronically shifting ormultiplexing signals in two dimensionsis essential for practical operation of alarge array of individual detectors. Atpresent, only silicon -based multiplexers,such as the silicon charge -coupleddevice (CCD), can do this.

Because silicon is sensitive to visibleradiation, a multiplexed visible imagercan be monolithic. In this case, siliconphotosites produce charge as a result ofincident photons, and we can transferthis charge down a line of CCD elementswith little distortion. This creates a visi-ble imager that is a mosaic of discretelyaddressable picture elements.

For the infrared bands, sensors previ-ously consisted of sheets of IR detectorsbonded onto CCD multiplexers so theCCD storage wells can collect the detec-tor output charge. This creates a hybridsensor chip. To store a signal, CCDsintegrate the output current of a photo -site or detector. Thus, all multiplexedimager arrays are integrating sensors.RCA now uses a monolithic approachto sensor construction, described in thisarticle.

RCA has been a leader in CCD tech-nology for the past decade, and this

Abstract: RCA has developed uniquesensors that will solve future imagingproblems in terrestrial and spaceapplications. The major uniquenessand benefit of RCA's approach is thedevelopment of monolithic siliconsensors. This is the only technologythat currently can achieve the largemultidetector focal planes needed in thefuture.©1986 RCA Corporation.Final Manuscript received November 20. 1985Reprint RE -31-1-2

leadership has enabled unique contribu-tions to both visible and IR sensors.

Visible CCD technology

A recent RCA advance is the fabricationof a large, linear visible array (VIS/NIR) for the Multi -Spectral LinearArray (MLA) effort funded by NASA'sGoddard Space Flight Center. MLAtechnology will be used in earth resourcework, such as future LANDSAT mis-sions. Present earth -satellite sensors forthis purpose use a small number ofdetectors that are mechanically scannedorthogonal to the path of the satellite'smotion.

RCA has constructed a large, hybrid,visible focal plane that contains fourlines of 5120 picture elements (pixels)each. (The focal plane combines mono-lithic line -imager chips with hybrid elec-tronic components that are placeddirectly on the focal plane.) This pixeldensity allows us to image the earth'ssurface from the "pushbroom" scanthat the satellite's motion produces; wedo not need an additional mechanicalscan across track. As a result, each ele-ment dwells on a scene pixel 400 timeslonger than the sensors now in use.

This focal plane was fabricated as acombined effort by Advanced Technol-ogy Laboratories (ATL), RCA Labora-tories, and New Products Division.RCA offered two advantages over com-peting CCD technologies: the high per-formance provided by a proprietaryCCD thinning process, and integralspectral filters in the visible spectrum.

The VIS/NIR chip-a frame -transferimager-uses buried -channel, three-phase polysilicon gate technology likethe RCA 605 CCD imager." To obtain

Night imagery from RCA's 160x 244 IRCCDarray (reproduced from a television monitor).Note the heat pattern on the cart hood andthe thermal reflection of the exhaust systemon the road.

exceptionally high photosensitivity andresolution (inherently limited by thepixel structure), we used a 10 -micro-meter silicon substrate illuminatedthrough the unstructured rear side of thedevice. We cannot do this with the otherCCD technologies that do not featurethinned devices, because visible lightdoes not penetrate silicon that is thickerthan a few micrometers. These technol-ogies force us to use front -side illumina-tion, which degrades the image partlybecause polysilicon gate features on thefront side of the CCD scatter the signal.

An important and unique feature ofthe VIS/NIR design concept is the inte-gral sensor/filter approach. The set ofMLA optical filters now being pro-duced has 70, 80, 40, and 140 -nano-meter' passbands. Their design, whichrequires high in -band and low out -of-

band transmissivity between 0.4 and 1.0micrometers, was carried out at RCALaboratories using a computerizedmodeling technology.°

To determine how many layers wouldprovide the desired slope for each side ofa wide bandpass filter, we started withan existing catalog of quarter -wave-length stacks. The stacks had alternat-ing high and low indexes of refraction

RCA Engineer 31-1 Jan / Feb. 1986 11

Electro-optical sensors

The optical spectrum has four majoratmospheric windows, and the atmo-sphere is opaque to electromagneticradiation outside them. The visiblespectrum lies within the most famil-iar window, followed by the short-wave -infrared (SWIR), mid -infrared(mid-IR), and thermal -infrared (TIR)windows. These mid-IR and TIRwindow regions are classicallycalled the "infrared" bands, or the 3-

5 micrometer and 8-12 micrometerbands, respectively. Fig. 1 showsatmospheric transmission over a 20 -km horizontal path under typicalconditions. We can see similar trans-mission for vertical paths fromground to space.

While all objects with tempera-tures above absolute zero radiateenergy at all wavelengths, we can-not detect enough self -emissionfrom a room -temperature object inthe visible and SWIR bands. There-fore, we use these bands only toobserve sources at elevated temper-atures, or objects that reflect illumi-nation from those sources. However;

SOLAR SPECTRUMPEAKS

AMBIENT EARTH BACKGROUNDSELF EMISSION

PEAKS

f VISIBLE

SWIR 3-5 um////

812OPAQUE Pm

100

80

60

40

20

06A

0 2 4 10 12 14

WAVELENGTH (MM

Fig. 1. Typical atmospheric transmission at optical wavelengths, along a sea -level horizontalpath.

we can use the two infrared (IR)bands to detect self -emitted energyfrom bodies that are near room

temperature. This is the basis forinfrared sensors that "see in thedark."

and were from one to 20 layers thickbetween X = 0.40 to X = 1.0 micro-meters. To adjust the wavelength of thefilter, we changed the thickness of thelayers by successively altering the wave-length at which the layers are calculated.We added layers to match the stacks tothe substrate and to each other.

Figure 2a illustrates a 12 -layer stack at0.38 micrometers; the first layer has aneighth -wavelength high index of refrac-tion for matching to glass. Fig. 2b repre-sents a 13 -layer stack at 0.605 micro-meters. When we superimpose the twostacks, we obtain a bandpass filter ofour blue filter design.

However, from the diagram we cansee that the transmission increasesmarkedly beyond about 0.60 microme-ters. If we need further blocking, wemust add stacks that will transmit in thefilter region and reject anything past0.68 micrometers. Adding anotherstack (Fig. 2c) at 0.80 micrometers willthen lower the transmissivity out toabout 0.90 micrometers. In this way, we

can get blocking to a desired wavelengthon both sides of a filter. All this pro-vided the starting point for the MLAdesign.

To complete the design, we used anRCA -developed computer program,Synthesis and Monitoring of OpticalInterference Coatings. We made manyiterations to minimize the number oflayers required, to use primarilyquarter -wavelength layers (for ease ofmonitoring), and to satisfy the finalspecifications. Where difficulties indirection arose, an RCA -developedoptimization program guided us.

VIS/NIR chips were integrated into ahybrid focal plane that had five sensorchips, physically abutted, giving us fourlines of 5120 pixels each'. The mechani-cal alignment and placement of thesechips was very demanding. For exam-ple, no more than two 15 -micrometerpixels could be lost in an abutmentseam. SWIR devices were placed in asimilar focal plane containing two linesof 2560 elements each.

Both focal planes (Fig. 3) are beingdelivered to NASA Goddard.

Infrared CCD technology

RCA has extended its expertise in visibleCCD technology to the development ofinfrared CCDs (IRCCDs). We are usingthe metal-silicide Schottky barrier detec-tor approach that was encouraged andfunded by Dr. Freeman Shepherd ofRome Air Development Center (Hans-com AFB)." A detailed description ofthe physics involved with Schottky bar-rier detectors is beyond the scope of thisarticle, but a brief explanation is possi-ble.

When deposited directly onto sili-con,' a metal, such as platinum, forms ametal-silicide (PtSi) layer. This layer is aphotodiode that is sensitive to IR radia-tion.

If we arrange the architecture of aCCD sensor chip properly, we canconfigure many of these photodiodes tofeed a signal directly into multiplexed

12 RCA Engineer 31-1 Jan. / Feb. 1986

12 LAYERS AT 0.38 -rn

L

1.0

0.8

Fn. 0.6

Z 0.44

0.2

000.4 0.5 0.6 0.7 0.8

LOW BAND EDGE ) IN ,,rn

1

(A)

0.9 10

10

0.8

10 0.6

4 0.4

0.2

00

13 LAYERS AT 0.605 .mANTI I 1 I

1 1 i

0.4 0.5 0.6 0.71 IN

LONG ) BAND EDGE

(B)

10

0.8

6

0.0

9 LAYERS AT 0.8 ),

I 1

0.8 0.9 1.0 0.4 0.5 0.6 0.7 0.8 0.9 1 0

IN rn

Fig. 2. Filter stack technology: interference filter transmissivity versus wavelength for a numberof alternating high and low refractive index layers.

(CIOUT OF BANDSUPPRESSION

5 BUTTED DEVICES

4 SPECTRAL BANDS(INTEGRAL FILTERS)

5,120 PIXELS PERBAND

ONLY 30,,m(2 PIXEL) LOSSAT SEAM

3,,m MISALIGNMENT

5,,m PLANARITYDEVIATION (Z)

SWIRHYBRID

5 BUTTED DEVICES

2 SPECTRAL BANDS

2.560 DETECTORSPER BAND

ONLY 60,,m(2 DETECTOR) LOSSAT SEAM

5,.m MISALIGNMENT

5.m PLANARITYDEVIATION (Z)

Fig. 3. Hybrid focal plane arrays.

BeO SUBSTRATE WITH

. KINEMATIC MOUNT

PRECISION ULTRASONICALLY MACHINEDOPTICAL APERTURE (1/2)

(a) VIS/NIR HYBRID

THICK FILM ON SILICONSUBSTRATE ALL MATERIALS MATCHED

TO SILICON CTE

(b) SVVIR HYBRID

5 CCD s WITH FILTER

20 JFETS

30 RESISTORS

50 CAPACITORS

240 WIRE BONDS

5 IRCCD s

20 JFETS

30 RESISTORS

70 CAPACITORS

245 WIREBONDS

Warren: Advanced technology for future imaging sensors 13

Important difference

The two IR bands have major differ-ences that become important whenwe consider technologies that arecompetitive with RCAs. Backgroundscenes near 300K (27°C) ambienttemperature have peak emission at10 micrometers, the center of the 8-12 micrometer band. As a conse-quence, the 8-12 micrometer bandcontains about 20 times more signalenergy from an ambient scene thanthe 3-5 micrometer band. However,because of the physical advantagesof 3-5 micrometer sensor technolo-gies and the reduced scene clutterin the mid-IR region, the 3-5 micro-meter region has equal or superiorperformance for some IR sensorapplications.

The tradeoff between the 3-5micrometer and 8-12 micrometerbands for a given applicationrequires a complex analysis, andslight variations of basicassumptions strongly influence theresults of that analysis.

Although the choice between the3-5 micrometer or 8-12 micrometerbands is often controversial, somegeneral -use trends have beenestablished. We often use the 8-12micrometer band to observeambient scenes passively, and

detect specific objects (targets)along lengthy horizontal paths(particularly where we expect highhumidity). A typical application is anIR imager for piloting a vehicle.

The 3-5 micrometer band is oftenused to observe or detect sceneobjects, such as vehicles or aircraft,that have slightly elevatedtemperatures.

However, a good 3-5 micrometerimager can compete with an 8-12micrometer imager in observingambient scenes, and 3-5micrometer imaging systems areusually less expensive thancomparable 8-12 micrometersystems.

Sensor characteristics varywidely for different requirements atthe four atmospheric windows.

Visible technology is the mostmature for two reasons: need andavailability. The need is obviousbecause our only source of naturalillumination peaks in the visibleregion. Imaging sensors-such asthe human eye, television, and filmcameras- were developed earlierthan IR imagers because detectionof visible photons is easier.

In a relatively stablematerial-such as silicon-thatcan be operated at roomtemperature, a visible photon has

enough energy to excite a signalelectron across the energy gap(move it from the valence band intothe conduction band). The weakerIR photon can only dislodge themore loosely held electrons from aless -stable material (lower energygap). However, the material mustthen be cooled to prevent theexcessive signal noise that arisesbecause the thermal agitationreleases random electrons.

Visible imagers such astelevision vidicons and film are, ineffect, X -Y addressable because wecan correlate the image signalstored in each physical location ofthe two-dimensional sensor surfacewith the location of the externalscene object that is imaged onto it.These X -Y locations are analog innature, with no crisp or quantizedboundaries between adjacentscene locations. Such imagingsensors are feasible in the visibleand near -infrared spectrumbecause photon energies exist inthis region.

However, no mid-IR or TIRvidicon or film exists (except thepyroelectric vidicon, which is anonquantum imaging IR sensor withlow sensitivity and low generalperformance). The IR-sensitivematerials can operate viably only as

CCD storage wells. The result is a one- ortwo-dimensional matrix of multiplexeddetector elements that exhibit very high -response uniformity and excellent pic-ture quality. For Schottky barrierIRCCDs we have measured a 0.5 percenttotal rms response nonuniformity over39,000 array -detector cells (160 x 244configuration). The hybrid imager tech-nologies, indium antinomide (InSb) andmercury cadmium/telluride (HgCdTe),exhibit response nonuniformities of 5 to50 percent over much smaller arrays.'

We have constructed multiplexedfocal plane arrays (FPAs) with hybridtechnologies and with IRCCDs. Ouremphasis has been on area arrays ratherthan line arrays, although both havebeen successfully fabricated. While wehave demonstrated the principle of largestaring FPAs, affordability remainsquestionable. The leading technology inthis area is HgCdTe.

About a decade ago, this country

selected HgCdTe as its strategic detectormaterial because HgCdTe detectors canbe tailored to respond in the SWIR, 3-5micrometer, or 8-12 micrometer spectralregions. They also exhibit high quantumefficiency. Since then, more than one-half billion dollars in developmentalfunding has been expended. This invest-ment has created a marketing interestthat has led to consistently optimisticpredictions of future cost and perform-ance. However, HgCdTe FPAs still areprohibitively expensive for two majorreasons:

1. The hybrid (non -monolithic) natureof the FPA sensor chip adds cost andreduces yield.

2. The photovoltaic HgCdTe materialnecessary for FPAs has not yet beendeveloped to its cost and performancepotential.

Although the older photoconductivesingle -element HgCdTe detectors are

now manufactured with only occasionalproduction problems, photovoltaicHgCdTe has poor noise performanceand does not respond across the entire 8-12 micrometer band. However, manymilitary applications prefer operation at8-12 micrometers, and HgCdTe remainsthe most promising material for thisspectral region.

RCA's monolithic Schottky barriertechnology can also operate in severalIR regions. Figure 4 shows the cutoffwavelengths and operating temperaturerequirements for Schottky barrier detec-tors formed with various metals. Whileiridium silicide shows some promise ofresponding in the 8-12 micrometerregion, not enough work has been donewith this material to show overall feasi-bility.

RCA has concentrated on palladiumsilicide (PdSi) for the SWIR region,' andplatinum silicide (PtSi) for the 3-5micrometer band.' Figure 5 plots the

14 RCA Engineer 31-1 Jan. / Feb. 1986

discrete detectors. Early IR imagersscanned a single small detectorover the entire scene in a raster toform an image. This is analogous tothe scanned, single electron beamthat "reads" a television vidicon.However, each small area of thevidicon constantly collects sceneenergy, while the single -scanningdetector sees each small elementof the scene for a very short time.

When we deal with discretedetector elements, we can improvethem proportionally to the squareroot of the number of detectors usedto observe a given scene. (Eachdetector increases its elemental -dwell time as the overall number ofdetectors increases.)

The ultimate IR imager would bethe discrete detector equivalent of avidicon. Many small detectorelements, in a two-dimensional X -Ymatrix, are electronicallymultiplexed to form the image froma single serial -data stream. Thiseliminates mechanical scanningand excessive numbers of signalchannels for handling the individualdetectors. Many attempts are beingmade to achieve such an IR sensor,while also making it reliable andaffordable.

measured responsivity (amps per wattof incident scene radiation) versus wave-length for typical palladium and plati-num devices. The graph also showsquantum efficiency (output electronsper input photon). Although platinum'sperformance is superior to palladium'sat all wavelengths, palladium is some-times preferred for the SWIR bandbecause of its relaxed cooling require-ments.

However, the responsivity and quan-tum efficiency shown in Fig. 5 do notentirely define detector performance.We must also consider detector noise,because the signal-to-noise ratio that wecan obtain for a particular scene objectis the real measure of a detector's per-formance.

Although the quantum efficiency ofSchottky barrier detectors is roughly tentimes less than that of the hybrid tech-nologies, the Schottky barrier also con-tributes much less detector noise.

12.0

10 0

IrSo8.0

PIS]6.0

S. Pt&

4.0

Nom,WSi2

TiSo2

2.025 50 75 100 125 150

MAXIMUM OPERATING TEMPERATURE (X)175 200

Fig. 4. Schottky barrier detector cutoff wavelengths and operating temperature requirements.

013

10

-210

-310

-410

2 3 4

WAVELENGTH ( A. m)

5 6

Fig. 5. Responsivity of typical palladium and platinum devices.

The most common parameter forevaluating an IR detector's signal-to-noise performance is specific detectivity,or D*, which is roughly equivalent toresponsivity divided by internal detectornoise. It is a figure of merit; high D*indicates good performance.

Figure 6 shows D* for Schottky bar-rier platinum silicide (PtSi) and indiumantimonide (InSb) as a function of spec-tral wavelength. InSb, a classicalhybrid -detector material used for FPAs

TBB 1000 CDapt 1.25 Cm

d 15.8 cm

SCHOTTKY-BARRIER RESPONSIVITv

R 41-MS)1-24-

DEVICE 11 Z-75C1 44.1°01!. MS 0.200eV

DEVICE 11 G-551,! MS 0.337eVC1 19.1.13

PtSi

- Pd2So

that operate in the 3-5 micrometerregion, is a better behaved material thanHgCdTe and has good credibility as a 3-5 micrometer sensor. However, Fig. 6indicates that PtSi is competitive withInSb.

RCA has fabricated monolithic FPAsthat have more resolution than has beenachieved with any other technology usedfor commercial or tactical military appli-cations. Figure 7 displays a chronologyof this development, culminating in the

Warren: Advanced technology for future imaging sensors 15

present 160 x 244 -pixel IRCCD.8At this point, we should summarize

the advantages that IRCCD technologyoffers.

Performance-The IRCCD's 99.5 -percent rms element -to -elementresponse uniformity is unique. It con-tributes to an overall system perfor-

1410

1310

1210

1110

1010

910

2

mance that is competitive with, andsometimes superior to, other detectortechnologies.

Producibility-The monolithic sili-con IRCCD is the only existing IRFPA that offers real production econ-omy. We can produce it on existingvisible-CCD production lines. Some

3 4

WAVELENGTH (it m)

Fig. 6. D * comparison between PtSi SBD and lnSb detectors.

5 6

15

ARRAY 10

SIZE(mm)

5 25 X 50(RADC)

160 X 244 (RADC)

32 X 64(RADC)

64 X 1 28(RCA)

64 X 1 2 8(RADC)

01977 1978 1979 1980 1981 1982 1983 1984

Fig. 7. History of the development of Schottky barrier focal plane arrays.

hybrid technologies could be pro-duced in moderate quantities, but atten to twenty times the cost. Hybridtechnologies that operate in the 8-12micrometer region cannot honestlybe considered producible in highquantity (50,000 per year), or even inmoderate quantities.

Cost-The fundamental productioncost of an IRCCD is not appreciablydifferent from that of a visible CCDimager. The cost may even be lessbecause military applications allowelectronic -blemish correction andimage compensation beyond what isusually feasible in a commercial cam-era. We incur a significant portion ofproduction cost by testing to militaryspecifications. Equivalent develop-mental hybrid FPAs are 100 timesmore expensive than the developmen-tal IRCCDs that RCA is producingnow.

Although the government's prior tech-nology commitment and resulting aero-space marketing thrust have favored theHgCdTe FPA, the government infraredbusiness is a large area, and some signif-icant niches are available to RCA.

RCA imager business development

RCA has a long history of developingimaging sensors, with emphasis on tele-vision technologies. The visible andinfrared CCD devices encourage simi-liar development for future applica-tions.

Table I outlines RCA's present con-tract involvement in imager technolo-gies and describes Government and aer-ospace programs where ATL has aprime or major supporting role. Thetotal value of the efforts represented inthe table is approximately 7 million dol-lars. The table does not include pro-grams that RCA's Astro-Electronics andAutomated Systems Divisions and RCALaboratories have pursued indepen-dently.

Recently, major ATL proposals weresubmitted to the Navy and other gov-ernment agencies for extensive contractsbased on IRCCD imagers. The generalmarket for IRCCD and CCD imagersincludes missile seekers, night -visionsensors, aircraft -tail warners (forapproach of tactical anti-aircraft mis-siles), earth -resources sensors, strategicearth -observation sensors (especiallyfor Strategic Defense Initiative pro -

16 RCA Engineer 31-1 Jan. / Feb. 1986

grams), and night sights (for tacticalanti -armor missiles).

RCA can anticipate more govern-ment and aerospace contracts thanthose listed in Table I, which will con-tinue the evolution of an interesting anduseful technology.

ReferencesI. J.R. Tower, et al., "Performance of 4 x 5120 Ele-

ment Visible and 2 x 2560 Element ShortwaveInfrared Multispectral Focal Planes," SPIEConf., San Diego Ca., August 1985.

2. E.D. Savoye et al., "High Sensitivity CCD Imag-ers for Television," SPIE Vol. 501, pp. 32-39,1984.

3. H. Elabd, A.D. Cope, F.V. Shallcross, W.F.Kosonocky, P.A. Levine, and D.M Hoffman,"4 x 1024 CCD Array for Remote Sensing Appli-cations," Journal of Imaging Technology, Vol. II,No. 6, October 1985, pp. 198-204.

4. W.M. Kramer and D.M. Hoffman, "Design andManufacture of a Filter Module for a Multispec-tral Detector Array," Electronic Imaging Conf.,Boston, Mass., Sept. 1985.

5. F.D. Shepherd and A.C. Yang, "Silicon SchottkyRetinas for Infrared Imaging," 1973 Int. ElectronDevices Meeting, Tech. Dig., pp. 310-313.

6. F.D. Shepherd, "Recent Advances in PlatinumSilicide Infrared Focal Plane Arrays," 1984IEDM, San Francisco, Ca., December 9-12, 1984,pp. 370-372.

7. H. Elabd and W.F. Kosonocky, "Theory and Mea-surements of Photoresponse of Thin Film Pd2Si andPtSi Schottky -Barrier Detectors with Optical Cav-ity," RCA Review, Vol. 43, December 1982, pp. 569-589.

8. W.F. Kosonocky, F.V. Shallcross, T.S. Villani, andJ.V. Groppe, "160 x 244 Element PtSi Schottky -Barrier IR-CCD Image Sensor," IEEE Transac-tions on Electron Devices, Vol. ED -32, No. 8,August 1985, pp. 1564-1573.

9. J.R. Tower, L.E. Pellon, B.M. McCarthy, H.Elabd, A.G. Moldovan, W.F. Kosonocky, J.E.Kalshoven, D. Tom, "Shortwave Infrared 512 x 2Line Sensor for Earth Resources Applications,"IEEE Transactions on Electron Devices, Vol. ED -32, No. 8, August 1985, pp. 1574-1583.

Table I. Major ATL program

PROGRAM CUSTOMER DESCRIPTION

Tankbreaker ASD/DARPA

VIS/N/R NASA

SWIR NASA

IRCCD cameras various (aerospaceprime contractors)

Shuttle camera Astro/NASA

Lockheed

FOG -M (fiber optic Army (MICOM)guided missile)

Navy (NRL)

Laser beamcontrol

Staringmeasurementssensor

Applies area -array IRCCD to imaging military targets(tanks) for autonomous detection and guidance ofman -portable anti-tank missile.

Use multispectral visible-CCD line imagers forearth -resources surveillance (LANDSAT).

Use multispectral IRCCD line imagers forearth -resources surveillance (LANDSAT) in the SWIRspectral region.

Deliver 160x244 pixel IRCCD cameras and 64x128pixel IRCCD sensors for testbed evaluation systems.

Deploy a 160x244 pixel IRCCD camera for aDecember 1985 shuttle experiment.

Develop IRCCD sensing of a large space -based laserbeam profile for feedback laser control.

Develop an IRCCD missile -seeker imager for targetdetection and guidance via a fiber-optic link.

Assess the infrared clutter background for futureIRCCD application in air defense.

Frank Warren is Manager of ATL's DeviceTechnology Laboratory. He is responsible for

development, and solid-state laser systemdevelopment. He has managed programs todevelop visible and infrared sensor arrays forspaceborne applications, EO surveillancetechniques for MX missile system physicalsecurity, and an IRCCD intrusion detectionsystem for perimeter surveillance. He is currentlydirecting the development and production ofIRCCD cameras custom designed for a widerange of applications. Frank received a BSEdegree from the University of Central Florida.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253.6501

Warren: Advanced technology for future imaging sensors 17

F.C. Luce W.B. Schaming

Automatic classification of ship targets

Engineers at ATL have developed a user-friendly, flexiblesoftware system for classifying infrared images of ships.

The Advanced Anti -Ship TargetingDevelopment (AATD) program startedin 1983 under the auspices of the NavalWeapons Center (NWC), China Lake,California, and is divided into severalphases. The current phase calls fordeveloping software that automaticallyclassifies thermal infrared images ofships. The final goal of the project is toproduce "flyable" hardware includingan infrared sensor that will automati-cally detect and classify a target andmake several tactical decisions in flight.

Abstract: Through IR&D projectsand contracts with the Naval WeaponsCenter, the Image TechnologyLaboratory has developed a softwaresystem for automatic targetclassification of ship imagery. Thesystem includes modules for targetdetection, segmentation, featureextraction, classification, andreport/display products. Developedfrom a large infrared image database,the system can receive and process animage (or images) and produceclassification results and associatedconfidence levels along with otheroptional outputs (e.g., totalclassification results and image displayproducts). This article documents thedevelopment of the AdvancedAnti -Ship Targeting Development(AATD) software and summarizes itscurrent capabilities and the resultsachieved to date.

©1986 RCA Corporation.Final Manuscript received November 20. 1985Reprint RE -31.1.3

Background

Over the past two years, we have devel-oped software for the current phasebased on infrared image data that NWCsupplied. The data were originally col-lected on videotape on -board an aircraftand later digitized by NWC and an inde-pendent contractor. During this phase,the procedure has been to receive one setof data for developing software andtraining a classifier, followed severalmonths later by a set of testing data. Weused the testing data to evaluate thedevelopment to date, as well as revealproblems with the software (or thedata). The Naval Weapons Center iscurrently comparing various systemsdeveloped by several contractors.

The data from each successive evalua-tion was concatenated to form an imagedatabase. At the conclusion of thisphase, the database contained over10,000 images, consisting of 10 sub-classes of ships at various distances andaspect angles. Each image of the data-base has a corresponding ground -truthrecord. The ground -truth informationincludes the correct ship classificationfor each image, the distance from thesensor to the target (the range), theaspect angle of the sensor with respect tothe bow of the ship, the relative intensityof the target, and a sensor flag that iden-tifies the particular sensor used in datacollection.

The final delivered software systemhas a user-friendly interface that allowseasy access and analysis. The interfaceprompts the user for the informationrequired to run each module of the soft-ware and has logical default values.

Although the system is designed to exe-cute a standard algorithm set, it is alsoflexible enough to allow various proces-sing options and combinations of dataand classifier designs.

The AATD software

Although the system's modules weredeveloped separately, they were inte-grated to run under a main driver rou-tine. The detection module has twoalgorithm options, one based on histo-gram thresholding of the image dataand the other on multifeature histo-grams and Bayesian decision rules. Thesegmentation module uses the detectionoutput and the multifeature Bayesianapproach to segment the target into asilhouette that is passed to the featureextraction routine. The feature extrac-tor collects various features from the sil-houette including geometry, texture,entropy, and height above water. Thefeatures for a given target are passed tothe classification module that contains astatistical tree classifier. The report anddisplay module reports the results for agiven target and summarizes the resultsfor a set of targets. As an option, it willdisplay intermediate image products ona display processor.

The input to the software is one ormore thermal infrared images that con-tain potential targets and the answers toa series of questions about the data andprocessing to be performed (Fig. 1). Theimage data and the correspondingground -truth data can be on tape ordisk, but must be in the specified formatthat NWC established. The software

18 RCA Engineer 31-1 Jan. / Feb. 1986

prompts the user for the location of thedata (is it on tape or disk), the names ofthe data and ground -truth files, and thename of a file that contains the classifi-cation tree. The remaining prompts arefor processing and output options.

Detection-first algorithm

The detection algorithm locates anobject in the image that is most likely thetarget. To do this, it uses a histogramthresholding process. The thresholdused is based upon the shape of the his-togram, the intensity of the target (is thetarget black or white) and the target/background contrast. Although selec-tion of the threshold is somewhat adap-tive, the adaptivity is limited.

To start the process, the detectionmodule reads the black/white hot flagfrom the ground -truth label and uses itto control initialization. If the flag has azero value (white is hot), the thresholdparameters are set for the bright end ofthe histogram. If the flag has a value ofone (black is hot), the parameters are setfor the dark end of the histogram.

Next, the histogram storage area iscleared and the 8 -bit intensity histogramis computed for the image. The intensityII that corresponds to the peak of thehistogram is located (see Fig. 2). Inten-sity 12 that corresponds to the Nth per-centile on the distribution function isalso located; in Fig. 2, /2 is at the 95thpercentile. The threshold T is computedas the average of II and 12, and the inputimage is then divided into a binaryimage based on the threshold at inten-sity T.

If black is hot, all pixels that have anintensity less than T are set to one. Ifwhite is hot, all pixels that have an inten-sity greater than T are set to one. Allclusters of pixels in this binary image arelocated and are then thinned based onthe size of the expected target as dictatedby the range estimate. (A cluster is aconnected set of pixels.)

Next, the detection module evaluatesthe results, modifies the thresholds, ifnecessary, and constructs a rectanglearound the target region.

If a target is found, the maximum andminimum x and y coordinates thatdefine a rectangle around the target arestored along with the size of the area. Ifthe detection process did not find anobject, it sets the area to zero and setsthe maximum and minimum x and ycoordinates to out-of-bounds values.

Would you like the program to run a self test [y/N]: nWhat is the test number (i3) : 4

What is the input image data -set ID number (i3) : 45

DEFAULT OPTIONS

- Detection, Segmentation, and Classificationperformed

- Detection Algorithm I will be used- Segmented output will NOT be generated- Feature file will NOT be generated- Classification results NOT displayed on- Input and Output assumed to be on DISK- NWCPRG is NOT executed- DEFTREE.dat is assumed to be the tree file- The Debug option is NOT specified

will be

terminal

Use default options [Y/n] : n

Is Detection and Segmentation required [Y/n] : y

Use Detection Alg. I or Detection Alg. II [ONE/two] (al) : oneSave segmented output [N/y] : n

Save Feature file [N/y] : n

Is Classification Desired [Y/n] : yLog Classifier results to terminal [y/N]: yIs input image on tape or disk [D/t] : d

Output report file on disk or tape [D/t] : d

Is the Display program (NWCPRG) required [N/y] : n

Read in a new classifier tree [N/y] : yIs Debug option required [N/y] : n

Sequence number of the 1st image to process (i4)[1]: 1

How many images should be processed (i4) [1]: 1

The interval between the images (i4) [1] : 1

Enter name of classifier tree [DEFTREE] (a8): newtree

Fig. 1. Sample session of the AATD user interface. The system's requests also identifyacceptable user responses.

Fig. 2. Example histogram of a hot target in a colder background. (White is hot.)

Detection-second algorithm

The second detection algorithm was pri-marily devised for use with syntheticimagery where the performance of the

first algorithm was questionable. Spe-cifically, synthetic images that containedrandom noise in the background alongwith a gray target would fail in the

Luce/Schaming: Automatic classification of ship targets 19

64 LINES

256 SAMPLES

TX TY11, 1

DX1 DY1

DX2, DY2

TX2 TY2

FX2 FY2

TX1 = DX1 - 10 TX = DX + 10

TY1 = DY1 - 5 TY2 = DY2 + 5

F = DX., 30 FX2 = DX2 + 30

F = DYi - 15 FY2 = DY2 + 15

DX1 DY = MINX, MINY

DX2, DY2 = MAXX, MAXY

Fig. 3. Target and frame regions defined for the segmentation process.

FEATURE EXTRACTION

BASED ON SILHOUETTES

1 I 2 1 3 I 4 5 I 6

GEMOMETRICTEXTUREENTROPYHEIGHT ABOVE WATER

Fig. 4. Sample silhouette that shows the six equal lengths along the orientation axis in whichthe classification features are computed.

histogram-thresholding method. There-fore, we adapted the segmentationalgorithm (described in the next section)to perform two-dimensional histogramthresholding, using intensity and edgeinformation to detect targets.

The output from the second detectionalgorithm is the same as the first. Itpasses target coordinates to the segmen-tation routine.

Segmentation

If the area of the target located in thedetection process is zero (no object was

detected), the system bypasses segmen-tation processing.

If a target had been found in detec-tion, then the system defines target andframe regions (Fig. 3). To define the tar-get region, it adds ten pixels to both endsof the detected region and five lines tothe top and bottom of the region, toallow for inaccuracies in the detectionoutput. To define the outside bounds ofa frame region, the system adds 30 pix-els to both ends of the detected regionand 15 lines to the top and bottom of thedetected region.

For segmentation purposes, then, thetarget lies inside the rectangle defined by

coordinates TX,, TY, and ( TX2, TY2).The area between this rectangle and theframe rectangle defined by the coordi-nates (FXb FYI) and (FX2, FY2) will beused to estimate the statistics of the localbackground.

The system generates an edge imageusing the absolute -value approximationin the Sobel -edge operator. The originalintensity data and the edge magnitudedata are used to generate two-dimen-sional feature histograms from the pix-els contained within the target windowand the pixels contained within theframe region. These two joint distribu-tions are used to generate a Bayesian-decision rule that indicates whether apixel is to be called target or back-ground, depending on the joint occur-rence of intensity and edge magnitudeassociated with the pixel.

Then, the system uses the decisionrule to classify all pixels within the targetwindow as either target or background.It sets target pixels to one and backgroundpixels to zero. The target pixels are againgrouped by clusters and the largest clusteris preserved as the target. All pixels thatare not part of the largest cluster are set tozero. This represents the segmented targetused for classification.

Feature extraction

The feature -extraction algorithm com-putes the set of features that the classi-fier module requires and uses the seg-mented target silhouette generatedduring segmentation. Figure 4 shows anidealized ship silhouette from which fea-tures are to be extracted and lists thegeneral types of features that will becomputed.

The silhouette is divided into six equallengths along the orientation axis. Manyfeatures are computed individuallywithin these six regions to providerelative -position information about thesuperstructure. In reality, superstructurefeatures are computed with respect to amensuration line that passes through thehighest point in the silhouette ratherthan from the bottom of the object.This eliminates some of the discrepan-cies that may occur because of segmen-tation irregularities at the water line.

The original set of features evaluatedin the classifier -design process included71 different measures, but this set hasbeen trimmed to 43. The general charac-teristics of the current feature set arelisted in Table I.

20 RCA Engineer 31-1 Jan. / Feb. 1986

Classification

To evaluate the features computed in thefeature -extraction module, the classifi-cation algorithm passes them through abinary tree classifier. The exact structureof the binary -tree is based on the charac-teristics of the training dataset.

We developed an example of a binarytree (Fig. 5) by analyzing a trainingimage -data set we received in the earlystages of the program. At each node inthe tree, a subset of the computed fea-tures will be used to decide whether toproceed down the left or right branchfrom the node being examined. Todetermine the decision rule at each node(as well as the tree structure), we ana-lyzed the training data features byclasses or subclasses, and found a modelor function that will differentiatebetween two groups.

The function of this algorithm and itsinput/output requirements are welldefined, even though the exact treestructure is not. The only required inputis the feature set that is passed from thefeature extraction program, and theoutput is the set of decision levelsrequired to generate a report file.

To create the tree structure, we used aclassification algorithm that yields abinary -decision rule. The first decision,or node, is selected by using availabletraining data, separating the data intotwo groups using a classifier, finding the"best" binary split among the classes(or combinations of classes), and thenapplying the decision functions. Thesetwo groups are then analyzed for thenext "best" split among the classes, andeach is divided by the decision function.The process continues until terminalnode conditions exist (we reach the bot-tom of the tree).

We selected linear discriminant analy-sis (LDA) as the classification schemefor this project because it is easy toimplement and has relatively high per-formance. The goal in LDA is to findclassification functions (linear combi-nations of the original variables) thatbest characterize the differencesbetween groups. In this case, the groupsare subclasses or combinations of sub-classes. We can structure other classifi-cation schemes-such as minimum dis-tance, nearest neighbor, quadratic, andBayes-to produce similar binary treesthat can be readily adapted for use in theclassification algorithm.

To improve classification perfor-mance, we concentrated on the imagery program.

Table I. General characteristics of classification features

Featurenumber Description

1-810-1724-26

Features derived from length, area, height, perimeter

Eight directional probabilities

h7, h8, h9 = (h1+h6/2), (h2+h5/2), (h3+h4/2) respectivelySix average height above water features, hl-h6 (The ship isdivided equally into 6 vertical sections along the length of thesilhouette)

27, 28 (h7/h8), (h8/h9)

30, 33, 34 Three superstructure entropy features

42-44 Texture features, analogous to Features 24-26

45, 46

48, 50

58, 59

62

65

66-6869

71

Texture features, analogous to Features 27, 28

Divide Features 42, 44 by total superstructure texture(To make scale and rotation invariant)

Texture features: analogous to Features 43, 44 but are computedwith different formula

Linear combinations of two texture features (Feature 57/Feature 59)Note: Feature 57 is analogous to Feature 42 but computed withdifferent formula

Texture: analogous to Feature 50 but computed with differentformula

Silhouette moments M10, M01, M11

Total superstructure entropy

Total superstructure textures for Features 51-56

Fig. 5. Sample decision -tree structure developed during the early stages of the AATD

Luce/Schaming: Automatic classification of ship targets 21

IMAGE ID 1.750 SC =

ASPECT INDICATOR 1

DETECTION (1) / NO DETECTION

205

(2) : 1

RANGE

CONFIDENCE

52 Kilofeet

93.78

TARGET (1) / NO TARGET (2) 1 CONFIDENCE 100.00FOE (1) / FRIEND (2) 2 CONFIDENCE 100.00COMBATANT (1) / NON-COMBATANT (2): 1 CONFIDENCE 100.00

1st CHOICE CLASS 2 CONFIDENCE 91.342nd CHOICE CLASS 3 CONFIDENCE 6.693rd CHOICE CLASS 4 CONFIDENCE 1.97

1st CHOICE SUB -CLASS 205 CONFIDENCE 90.942nd CHOICE SUB -CLASS 301 CONFIDENCE 6.693rd CHOICE SUB -CLASS 401 CONFIDENCE 1.97

Fig. 6. Sample output of the AATD software for a single image.

that contained side -views of the targetbut refused to classify head-on targets.Therefore, we added one node to the topof the tree for determining favorableand unfavorable aspects. We divided thetraining data into two classes (head-onand side -view) and again used LDA tofind the best classification function toseparate the two groups.

Likewise, because many classifica-tion errors were caused by poor segmen-tation, we added nodes near the top ofthe tree to screen -out the poorly seg-mented samples. All segmented trainingdata was viewed and labeled as goodsegmentation, over -segmented, orunder -segmented. Again, we used LDAto find discriminating functions to

Table II. Self -test classification results.

seperate the poor segmentations fromthe good. The poorly segmented sam-ples were classified as refusals, and thegood samples continued down the treeto be classified into a class and subclass.

Report and display

The report module outputs the resultsfor each image as it is classified and gen-erates output files for calculating finalclassification matrices. Figure 6 is anexample of the output for one image.The output contains various levels ofdecision and their associated confidencelevels.

The display routine is simply an inter-face between the AATD software and a

display -processing system, but the soft-ware is generic enough to be compatiblewith many systems. The detection, seg-mentation, and original images can allbe displayed.

Performance assessment

The NWC held four classification eval-uations and one segmentation evalua-tion to find deficiencies in algorithmsand their development and to compareresults from various contractors. Eachevaluation consisted of a training dataset that was sent for training a classifier,and a test data set of unknown imagesfor testing the software. The results ofthe classification evaluations accuracyover all classes ranged from 63 to 90percent total. Each classifier was self -tested and, as expected, performed verywell. When testing the classifier on thedata, the results always dropped, as wasalso expected. However, the magnitudeof the drop in overall percent correctindicated problems in the algorithms, orpossibly in the image data or corres-ponding ground -truth label informa-tion. Table II, a sample classificationmatrix, shows a self -test on the mostrecent classifier design. The classifica-tion is made to the ship subclass level,and the subclasses varied from 84.6 to95.8 percent correct.

In the segmentation tests, our twodetection algorithms performed asanticipated. The first algorithm did wellon real imagery and produced good seg-mented output, but it performed poorly

4 Images have unfavorable segmentationsO Images have unfavorable aspects (i.e. head-on)O Images have zero area (i.e. not detected)O Images are false alarms (i e. area less than 25)

Classification Matrix:

Group PercentCorrect

Number of samples classified into group -

SC201 SC202 SC205 SC301 SC302 SC3O3 6C401 SC402 SC403 TotalSC201 90.91 190 0 4 5 0 0 6 0 4 209SC202 0. 00 0 0 0 0 0 0 0 0 0 0

SC205 92.99 4 0 292 12 0 0 1 0 5 314SC301 90.54 3 0 23 287 0 0 3 0 1 317SC302 92.72 1 o 3 0 191 0 2 0 9 206SC303 0.00 0 0 0 0 0 0 0 0 0 0SC401 84.55 6 0 5 2 3 0 104 0 3 123SC402 0.00 0 0 0 0 0 C) 0 0 0 0SC403 95.76 4 0 2 1 0 0 7 0 316 330Total 92.06 208 0 329 307 194 0 123 0 338 1499

1380 samples are correctly classiVied from 1499 samplesTotal classification percentages = 92.0613708

22 RCA Engineer 31-1 Jan. / Feb. 1986

on some synthetic images that containedrandom noise as a background. The sec-ond algorithm did reasonably well withboth the real and the synthetic imageryand had good segmented output images.The only drawbacks with the secondalgorithm were its slow computationtime to detect a target and its assump-tion that the targets were queued andnear the center of the image.

The software system was also testedfor robustness to range -estimate errorsand to determine unfavorable aspects.The results indicated that severe errorsin the range estimates could be the causeof large drops in classification percent-ages. The problems with favorableaspect determination are more manage-able. If we use LDA and the currentfeature set, a single node in the classifi-cation tree can determine favorable orunfavorable aspects with a high degreeof accuracy. Targets that have unfavor-able aspects can then be called refusalsuntil a favorable aspect is obtained.

SummaryA software system now exists that willautomatically classify ship targets fromthermal infrared image data. The sys-tem has been tested and produced favor-able results. It has a user-friendly inter-face to allow easy processing under avariety of parameter combinations.This will allow analysis with variousdata classes and subclasses, and pro-vides the ability to introduce new classi-fication schemes without software revi-sions. If software revisions are deemednecessary, the system's modules adapt tochange without major software revi-sions.

Frederick Luce was a Senior Member of theEngineering Staff in ATL's Image TechnologyLaboratory. He was a lead engineer on the ShipTarget Classification program, responsible fordesign, development, testing, andimplementation of the software system. He hasalso performed analysis of the entire systemand its corresponding inputs arid outputs. Priorto joining RCA in 1984, he worked on a variety ofimage processing, remote sensing, anddatabase development projects at the JetPropulsion Laboratory. Fred has a BS degree inForest Science, and an MS in Forest Resourcesand Operations Research from PennsylvaniaState University. He is currently at CorningGlass Co.

Bernie Scheming is Unit Manager of the TargetRecognition Systems group in ATL's ImageTechnology Laboratory. His responsibilitiesinclude the development of automatic targetrecognition technology. He was the programmanager for the Advanced Antiship TargetingDevelopment Program for the Naval WeaponsCenter. He received a BSEE degree fromGannon College and an MSEE degree from theUniversity of Pennsylvania.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6465

AcknowledgmentThe authors would like to thankRichard Gould of the Naval WeaponsCenter, China Lake, California, for hisongoing support of the project and his

assistance and ideas that improved oursoftware system. In addition, we wouldlike to thank ATL engineers MarybethKenig, for her professional softwaresupport, and Lou Gardiner, for hisassistance in data analysis.

Luce/Schaming: Automatic classification of ship targets23

D. VVille' A. Rosen

Laser development and applications

The efficiency and high reliability of diode -pumped solid-statelasers has spurred interest in their use in a variety ofapplications.

Important applications for lasers arefound in communications. One areathat is being addressed is the Navy pro-gram for communications with subma-rines from satellite platforms (SLC-SAT). A second prominent applicationis LIDAR (Light Detection and Rang-ing), which uses space -based lasers tomonitor the state and constituents of theatmosphere. This includes such mea-surements as wind velocity, cloudheights, and altitude of atmosphericconstituents. For both of these applica-tions, two important requirements mustbe met: the laser system must be long-lived (10 years is desirable), becauserepair is not usually feasible if the sys-tem fails; and the system must be power -efficient. The latter is importantbecause the increased requirements forprime power means increased power

Abstract: Advanced TechnologyLaboratories (ATL) is currentlyinvolved in the development andapplication of lasers in conjunctionwith RCA Laboratories andAstro-Electronics Division. Futureefforts will expand the area of interestto include other divisions. The currentlaser activity, which started in 1983, hasgrown significantly since then. Theinitial thrust of this activity has been inthe area of diode -pumped solid-statelasers for space applications, butinterest has expanded to include otherareas, such as the application of lasersto the control, generation, andprocessing of radar signals.

01986 RCA Corporation.

Final Manuscript received November 20. 1985Reprint RE -31-1-4

generating capability. This, in turn, willincrease the launch weight, and willmean a weight restriction someplaceelse.

Achieving high -power efficiency is animportant goal, because solar panelsmust provide the prime power on a sat-ellite. Also, reaching the efficiency goalcan be the difference between makingthe mission feasible or not.

Diode -pumped solid-state lasersThe usual practice with solid-state lasersis to use a flash lamp to pump the lasermaterial, but flash lamps are both inef-ficient and unreliable. We need anotherapproach, such as the use of laser diodesas the pump source. For these applica-tions, the important laser materials areNd-doped YAG (yttrium aluminum gar-net) or Nd-doped glass. With thesematerials, lasing action occurs with arod or a slab of the material in an opticalresonator formed by two mirrors. Lightin the resonator travels back and forthbetween the mirrors and interacts withthe laser material. The light either grows

or decreases in intensity, depending onthe relative number of atoms in the twoenergy levels involved in the laser transi-tion. The pumping mechanism ensuresthat there are more atoms in the higherenergy state than in the lower energystate, so gain occurs.

A typical resonator is shown in Fig. 1.It is a flash -lamp pumping configura-tion where both the lamp and the laserrod are at the foci of an elliptic cavitythat has reflecting walls. Thus, all thelight that the flash lamp emits will passthrough the laser rod and have the bestchance of being absorbed by the lasermaterial.

Now, consider the question of effi-ciency. In Fig. 2, we show the absorptioncurve for Nd:YAG. As can be seen,absorption occurs only at discrete fre-quencies. A flash lamp, on the otherhand, has a very wide emission curve,and this is the source of the efficiencyproblem. Most of the energy that theflash lamp emits is at the wrong wave-length, and is therefore wasted.

A laser diode, on the other hand, hasa line emission (Fig. 3) that can be tail -

Fig. 1. Major components of an optically pumped solid-state laser oscillator

24 RCA Engineer 31-1 Jan. / Feb. 1986

Fig. 2. Absorption spectrum of Nd: YAG at 300K.

ored to occur over a range of wave-lengths and can be matched exactly toan absorption line of Nd. The wave-length selected is at the strongest absorp-tion line of Nd- 0.8085 microns. Thelaser diode is itself a semiconductorjunction device and uses an electricalpumping mechanism; that is, electronsare injected into the device at the upperenergy level and are ready to providegain. Figure 4 shows the layer structureof the diode. These diodes are referredto as oxide -stripe, double-heterostruc-ture devices, and the layers are grownepitaxially. The diodes have a wide junc-tion (100 microns) and are at a spacingof 300 microns.

For these devices the output power, P,is given by

vv

P = - u-ith)

where 77 is the external differential quan-tum efficiency, hv is the photon energy,Q is the electron charge, I is the operat-ing current and 4,, is the threshold cur-rent for lasing to occur. As can be seenfrom this expression, one of the moreimportant design characteristics for adiode laser is a low threshold current.

Diodes grown at RCA Laboratoriesput out as much as one watt of peakpower, but even with this output weneed an array of laser diodes to provideall the power necessary to pump the Ndlaser. Figure 5 outlines the array conceptthat is now being developed.

The basic building block is a bar of sixdiodes that is cleaved from a wafer.These bars are attached to insulatingsubstrates, and the units are assembledonto a grooved baseplate and solderedinto place. Assembling the arrays usingsingle diodes would be much too com-plicated, and very long bars would be

Fig. 3. Laser diode emission spectrum.

EPITAXIALLAYERS

METALLICSTRIPE[CONTACT

7-45 MICRONS

GROUND

a

HEAT SINK

SOLDER

METALLIZATIONp- -"CAP-

- WALL"ACTIVE LAYER

n - "WALL'

n - SJBSTRATE

METALLIZATION

CLEAVEDFACET

111111111Mar

b

/ SiO2

CURRENTDISTRIBUTION

RECOMBINATIONREGION

Cu

InS,O2

GaAs:GeAlxGai_x As:GeAlyGai_y As:undoped or SiAlxGai_x As:Sn or Te

GaAs.S1

Fig. 4. Simple continuous -wave lasers. (a) The layer structure of the oxide -stripe double-heterojunction laser,- (b) The cross section of a heterojunction aluminum gallium arsenidelaser

hard to handle and would cause yieldproblems. The use of six -diode bars is acompromise.

The laser diodes show a power con-version efficiency of greater than 25 per-cent, and because their emission spec-trum overlaps with the Nd absorption,

we gain orders of magnitude increase inoverall efficiency compared to flashtubes.

A typical Nd laser using a diode pumpis shown in Fig. 6. Here, the Nd:YAGslab is pumped by four units of diodearrays, each consisting of five subar-

Wille/Rosen: Laser development and applications 25

200 ,,rn

BERYILLIUM OXIDE LINEAR GaAs ARRAYSUBSTRATE

O SINGLE AIGaAs WIDE -STRIPE DIODE ONAPPROXIMATELY 300 -cm CENTERS,APPROXIMATELY 6 DIODES PER LINEARARRAY, AND APPROXIMATELY 12 DIODESPER BERYILLIUM OXIDE WAFER AS SHOWN

PLATED GOLD BUMP/STRIPSAPPROXIMATELY 25x25x200kn

O AIGaAs LINEAR LASER ARRAY

BERYILLIUM OXIDE STRESS RELIEVING PLATED GOLD STRIP

BUMPS (VERTICAL) APPROXIMATELY 25tnHIGH ON 150 -cm CENTERS

BeO METALLIZATION SHOWINGELECTRICAL ISOLATION BREAK

TYPICAL DIODE EMITTING REGION

Approximate4 57 Rows of Linear AIGaAs Diode Arrays on175,m Centers (114 Arrays, Total)

Heat Sink/Mechanical Mount for 57 Rows of Arrays toSubmodule Holder by Mass Solder Joints in Slots in Holder

Submodule Holder - Copper or Beryillium Oxide

Fig. 5. Aluminum -gallium -arsenide (AlGaAs) laser diode array. Schematics represent: (a) theAlGaAs laser diode mounted on beryllium oxide (BeO); (b) the end view of the diode array; and(c) the diode array submodule.

rays. The subarrays, in turn, consist ofunits like those in Fig. 5, but each con-tains 684 diodes. The complete pumpingscheme shown here has 13,680 diodes.We have developed techniques forassembling the diode arrays economi-cally. Without such techniques, arrayswith this many diodes would be prohibi-tively expensive.

Normally, we would want a shortpulse from the laser, and this can beachieved with a Q -switch device (Fig. 6).The Q -switch is used to spoil the Q ofthe optical cavity and prevent it frombuilding up the lasing resonance. Whilethis prevents lasing, it allows a greater-than -normal population inversion tobuild up and, when the Q of the cavity isrestored, a very short, high -power pulseis emitted. Typically, a non -Q -switchedlaser might have a pulse length of tens ofmicroseconds, while a Q -switched laserwould have a pulse length of tens ofnanoseconds.

The laser diodes we are developingare highly reliable devices, and weexpect them to last much longer than theaverage mission duration. There arevarious failure mechanisms for laserdiodes, but after a burn -in period ofapproximately 100 hours, our testinghas shown that we can expect a verylong mean time between failures.

In Fig. 7, we show the results of lifetests of laser diodes. As can be seen,after 7 x 105 hours only half the diodeshave failed. These tests were part of anaccelerated life test where we used ashort period of operation at an elevatedtemperature to extrapolate to the resultsthat would be obtained at room temper-ature. Diode failure follows a lognor-mal distribution function and its proba-bility density function is given by

f(t) = 1/N/t20227r exp [ (lnt-µ)2

where f(t) is the probability of failure attime, t. The symbols µ and a refer to themean and standard deviation of therelated normal distribution, althoughthey are not the mean and standarddeviation of the resultant lognormal dis-tribution.

Optical control of microwavedevices

A new application area that we areexploring is the use of lasers in conjunc-tion with microwave devices. This field

26 RCA Engineer 31-1 Jan. / Feb. 1986

1064 nmOUTPUTMIRROR

7.4- PLATE

4PLATE

Nd:YAG SLAB

OPTICALLY TRANSPARENT- AT 808.5 nm

COOLING LAYER

SEMICONDUCTORLASERARRAYS

Q -SWITCHKID`P

REARMIRROR

Fig. 6. Diode -pumped Nd: YAG slab laser showing operation in total internal reflection (TIR)mode.

is now a collection of separate tech-niques that, as their primary focus, uselasers to generate, control, or processmicrowave signals. Among the specifictechniques being considered are:

o Fiber-optic rf transmission lineso Optical control of phased -array

antennaso Optical delay lineso Optically controlled switching of

electronic signalso Frequency locking of electronic

devices using optical signalso Optical data processing of electronic

signalso Optical switch networks for distribut-

ing microwave signalso Microwave signal generation

Central to these ideas is the concept ofusing a laser source and modulating itsoutput at microwave frequencies tosend microwave signals on an opticalfiber. Fiber-optic communications tech-nology is proceeding in the direction ofoptical wavelengths in the 1.3- or 1.5 -micron range. However, since long pathtransmission is not desired in this case,

we prefer the 0.8 -micron region becausethe technology of sources and detectorsis more advanced. Laser diodes are thesources of choice because of their smallsize, high efficiency, and high outputpower.

We can modulate the laser diodesdirectly by varying the drive current, orwe can pass the emitted light through anexternal modulator. Lasers have beendirectly modulated at frequencies up to11.6 GHz, and have been externallymodulated at frequencies up to 18 GHz.Because lasers can be modulated atmicrowave frequencies, it is possible touse optical fibers to transmit the micro-wave signals. With this approach thereis significant freedom in choosing thelength of the transmission path andcomplete absence of electromagneticinterference effects.

Today there is great interest in the useof phased -array antennas composed ofindividual emitters. Arrays are envi-sioned with thousands of elements, andthe problem of controlling the array isformidable. Figure 8 shows how opticalsources could be used for array control.The output of a laser diode modulated

108

2

106

tu

0

104

x - EXTRAPOLATED FROM 70 CUSING 0.95 eV ACTIVATIONENERGY11111. I

2% 8 10 15 20 30 00 50 60 70% FAILURES

Fig. 7. Results of life tests on laser diodes.

80 8590 96 98%

at microwave frequency is coupled intoa fiber, and an integrated optical devicedivides that energy into a number offiber output ports. Each output is thenfed to an integrated optical -phaseshifter; it can be a switch matrix thatsimply switches in different lengths ofcoupling fiber to produce the requiredphase shift. The signal from the phaseshifter is then fed to the radiating ele-ment that is turned on and frequency -locked by the incoming optical signal.

To provide optical delay lines, aswitch array and a set of fibers with dif-

Wille/Rosen: Laser development and applications 27

RADIATING ELEMENTS

I TO N COUPLER

PHASE SHIFTER

LASER DIODE

Fig. 8. Concept for optical control of phased array microwave antenna.

Fig. 9. Optical switch concept.

ferent lengths that can be switched in toprovide the required delay. Delays of upto tens of nanoseconds are easilyachieved, and delays in the microsecondrange can be achieved using hybrid tech-niques.

In a more general sense, we can dodata processing of microwave signalsusing optical techniques; functions,such as signal correlation and spectrumanalysis, are prime examples. In addi-tion, numerical processing can also bedone optically.

Switching of signals at high speed is adifficult problem that is compoundedwhen the signals are high -voltage and

high -power. Optical techniques havesignificant advantages in speed, size,and reliability. In its simplest embodi-ment, an optical switch could be merelya slab of semiconductor material that isilluminated by a laser diode (Fig. 9). Ifwe use high -resistivity material, theswitch can hold off a high voltage and,when illuminated, is effectively shortedout by the optically generated carriers.With proper design, optically activatedswitches can withstand hundreds ofvolts, pass tens of amps, and operate atsubnanosecond speeds. If we suitablyconnect groups of switches, they canoperate in the kilovolt-kiloampererange. The same diodes that we use topump YAG lasers find application indriving switches, but smaller arrays aregenerally needed, and there are no sig-nificant restrictions on the output wave-length.

SummaryTwo development areas of laser technol-ogy with important practical uses havebeen discussed. They are currentlyreceiving emphasis at ATL and will beactively pursued in the future. Otherareas, such as the application of lasers infiber-optic communications systems,are being reviewed and will receiveemphasis in the future, if warranted.

Wille (standing) and Rosen

Douglas Wille is Unit Manager of theElectro-Optics Applications group in AILSDevice Technology Laboratory. Hisresponsibilites include development of lasersystems and applications. He is currentlymanaging the PILOT unit -cell definition program,the PILOT 2-D array development, and theDiode -Pumped Laser program. He recentlysupervised a study of techniques for usinglasers for satellite communications withsubmarines. Prior to joining RCA, he was a UnitWork Leader in the Avionics Laboratory atWright -Patterson Air Force Base, engaged indevelopment of acousto-optic and electro-opticsystems. Dr. Wille received his PhD in Physicsfrom Ohio State University.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6498

Ayre Rosen received the BSEE cum laudefrom Howard University in 1963, the MScEfrom Johns Hopkins University (where heattended on a Gillman Fellowship) in 1965,and the MSc in Physiology from JeffersonMedical College in 1975.

He joined RCA Laboratories in 1967 asa Member of the Technical Staff in theMicrowave Technology group. Mr. Rosenis responsible for the research anddevelopment of millimeter -wave devicesand circuits. His work on integrated diodearrays paved the way for power combiningin microwave and millimeter waves. Hereceived a 1972 RCA LaboratoriesOutstanding Achievement Award for ateam effort in the development of S -bandTRAPPATT amplifiers and, in 1982, anindividual RCA Laboratories OutstandingAchievement Award for developing high-performance silicon PIN diodes forapplication to communications systems.

Mr. Rosen now holds an appointment ofAdjunct Professor at Drexel University, inthe Department of Electrical and ComputerEngineering. He is the author of more than60 technical papers and presentations,and holds 21 U.S. patents in themicrowave field.Contact him at:RCA LaboratoriesPrinceton, N.J.Tacnet: 226-2927

28 RCA Engineer 31-1 Jan. / Feb. 1986

P.B. Pierson

Advanced robotics projects at ATLfor remote servicing

Robots can help repair satellites in space, and researchers at

ATL are getting them ready for the job.

The use of robots in automating fac-tory operations been rising steadily inrecent years. Their precision and repeat-ability allow them to do high -volumerepetitive tasks without relying on sen-sors and to perform at maximum speedand reliability. To achieve this precisionin the workspace we use jigs and fix-tures. They are costly, but we can amor-tize the costs over the large number ofcomponents the robot processes.

We are also using robots to performoperations in environments that are haz-ardous or beyond man's reach. For ex-ample, undersea robots recently locatedand retrieved valuable items at greatdepths. Robots have been used innuclear -radiation contaminated areas tohandle materials and clean up. TheArmy, Navy, and NASA are actively

Abstract: For many years, AdvancedTechnology Laboratories (ATL) hasbeen involved in many technologiesthat are integral to advanced roboticsystems: advanced sensor systems,television -signal processing systems,precision mechanism andcontrol -system design techniques,machine -vision systems, computerarchitectures, artificial intelligencesoftware techniques, word recognitionsystems, and very -large-scale integratedcircuit designs capable of real-timesignal processing. These are criticallyneeded components for systemscapable of servicing satellites in remoteorbits in space.

01986 RCA Corporation.Final Manuscript received November 20. 1985Reprint RE -31-1-5

developing robotic systems to meet spe-cific needs in remote or unsafe environ-ments.

Robotic systems are also being devel-oped to process non -uniform produc-tion pieces. With such systems, automa-tion would be economically efficient forsmall production runs. Researchers aredeveloping robotic systems that canmachine just a few parts at low cost.Government agencies are interested insuch systems for their potential to man-ufacture limited -quantity items throughautomation. The U.S. Postal Servicewants robotic mail sorting systems thatcan handle a wide variety of nonuni-form pieces with a minimum of humaninvolvement.

In remote operations and low -quantity or nonuniform productionoperations we do not have precise dataon the location and orientation of workobjects. Also, exact motions usually arenot repeated. Robot motions mayrequire flexibility and freedom to reacharound unanticipated obstacles in theworkspace. Robots may need a varietyof tools or dexterous "hands" to per-form different tasks, but some toolsmay not be determined until the time oftask execution. Sensor systems mustprovide the detailed information aboutthe location, orientation, and status ofwork objects, and flexible software sys-tems must command the robot to per-form unique operations with minimalhuman involvement. Currently, theserequirements exceed the capabilities ofcommercial robotics.

Advanced Technology Laboratories(ATL) decided to combine its skills andcapabilities to meet a variety of automa-

tion and robotics needs in aerospace anddefense, and formed the Robotics activ-ity in January 1985. Under contract tothe U.S. Postal Service, we are develop-ing sensors capable of collecting three-dimensional information on irregularParcel -Post items, and separating themusing unique machine -vision techniquesand special-purpose robot hands.(These programs are described inanother article in this issue.)

Our current IR&D effort focuses ondeveloping telerobotic systems and tech-niques for remote servicing of satellitesin space. We are working closely withthe Astro-Electronics Division (AED),where RCA is designing satellites andspace station subsystems that astronautsor robots may service.

Satellite servicing objectives

Recently, astronauts have successfullyrepaired several satellites during extra-vehicular activity (EVA) from the SpaceShuttle. They repaired the Solar Maxi-mum Mission by manually replacing themain electronics box of the Corono-graph/Polarimeter experiment on Shut-tle flight 41C in April 1984. On Shuttleflight 511 in August 1985, astronautssuccessfully modified faulty circuitry onLEASAT, a communication satelliteowned by the Hughes Aircraft Co. Theythen performed manual spin -up prior todeploying the satellite into its requiredorbit. These successful repairs validatethe concept of space -based servicing.However, EVA is expensive (estimatedat about $75,000 per hour) and hazard-ous to the astronauts. Servicing byrobots near the Shuttle or Space Station

RCA Engineer 31-1 Jan. / Feb. 1986 29

would reduce risk to humans, and couldreduce costs of servicing operations.

Besides repair, robotic systems coulddo planned or routine maintenanceactivities-such as exchanging payloadsor orbital replacement units, refueling,and replacing batteries-thereby mini-mizing risks and operating costs.

Many satellites are in orbits beyondthe 275 nautical mile range of the Shut-tle. These include many of RCA's com-munication satellites at geosynchronousearth orbit (GEO), approximately22,000 nautical miles, and our weathersatellites in polar orbits, approximately350 nautical miles. Servicing at GEOwould be difficult for humans, even ifthe Shuttle could reach them. Becausethe earth's geostationary altitude lies inthe Van Allen radiation belt, mannedstations there would have to carry radia-tion shielding to protect the crew.Robotic servicers operating on site,therefore, offer important alternatives.

We can retrieve satellites at non -Shuttle orbits with an orbital -maneuver-ing vehical (OMV) and service them atthe Shuttle or on the ground. Or, robotic

CCTV

devices attached to OMVs could servicesatellites on site, with minimum inter-ruption to operating service. Time-consuming orbit change and re-establishment operations would not berequired.

Initially, people on the ground, at theSpace Station, or on the Shuttle wouldoperate and control robotic servicingsystems. (The Space Station is scheduledfor assembly in space beginning in1992.) We will modify techniques devel-oped for undersea work and in areas ofnuclear contamination. However, spaceintroduces a problem that land or seatelerobots do not experience-the longcommunication delays (up to 5 seconds)between the robot and the operator.Velocity or position control techniquesinvolve tedious and risky move and waitoperations. Techniques that reflectforces experienced by the robot back tothe operator are not suitable if there isany noticeable delay. To increase thecapabilites of distant robotic servicingsystems, we must develop predictivefeedback techniques or give the robotincreased autonomy.

SHUTTLE SECURE TELEVISION SYSTEMCONCEPT BLOCK DIAGRAM

Video bandwidth compression

TV cameras provide the primary meansfor observing and controlling opera-tions of remote robotic systems. Con-ventional video transmission requiressignificant amounts of bandwidth,more than is practical for most space -based systems.

ATL is currently helping AEDdevelop a video -processing system thatcan transmit high -resolution (768 pixelsper line), real-time color video at 27megabits per second. This system isplanned for use on the Shuttle in thesecure digital television (STV) systemthat AED is developing for the AirForce and NASA (see Fig. 1).

Video bandwidth compression willprovide maximum resolution andframe -rate TV feedback to remote oper-ators of robotic servicing systems inspace that transmit over data links rang-ing from less than 500 kilobits to 27megabits per second. Our STV designwill have a wide range of transmissionrates through variable reduction offrame rates and compression ratiosbetween 1 and 2 bits per pixel.

KG ENCRYPTOR

F/S COLORB/WNTSC

16 Kbs1024 Kbs28 Mbs

AIRBORNE DIGITAL UNIT

A/D:TIME BASE;MATRIX PROC

YIOFRAME STORES

KG DECRYPTOR

B/WI COMPRESS I-

SHUTTLE SYSTEM

SWITCHER

DATA LINKS

GROUND RECONSTRUCTION UNIT

D/A;B/W YIO

FRAME STORESVIDEOSWITCHER -11 EXPAND I

L _JGENERATION

GROUND SYSTEM

Fig. 1. Shuttle secure digital television (STV) system.

16 Kbs1024 Kbs28 Mbs(Future)

NTSC, B/WRGBF/S COLOR

30 RCA Engineer 31-1 Jan. / Feb 1986

Satellite control techniques

We have three primary controltechniques for satellite servicing:manual control, automatic control,and supervisory control as shown inthe accompanying figure.

Manual control includes extravehicular activity (EVA), teleopera-tion, and telepresence. In EVA,astronauts perform tasks directlyfrom within their space suits.Teleoperation is remote manualcontrol from a console where televi-sion views and simple sensor read-outs assist the operator. Teleopera-tion commands control eitherposition or force and torque. Intelepresence, an advanced form ofteleoperation, the teleoperator hasthe illusion of visual, tactile, audi-tory, or other sensory information.

Automatic control includes hardautomation, flexible automation,adaptive robotics, and autonomousrobotics. Hard automation usespreprogrammed sequences toexecute a single task, such as mod-ule exchange. Flexible automationsystems can execute a variety ofpreprogrammed tasks, with minimalretooling or reprogramming. Adap-tive robotics uses sensors to pro-vide fine control of robot motionwhere exact location of objects orservicer elements is not known.Autonomous robotics (or intelligent

EVA

MANUAL CONTROL

TELEOPERATION(TO)

SUPERVISORY(SU)

TE LEPRESENCE(TP)

HARD FLEXIBLE ADAPTIVE AUTONOMOUSAUTOMATION AUTOMATION ROBOTICS ROBOTICS

(HA) (FA) (AR I (AU)

AUTOMATIC CONTROL

Control techniques for satellite robotic activity.

robotics) is adaptive robotics inwhich artificial -intelligence -basedreasoning or planning programsdevelop the detailed control steps.The programs rely on goal -orientedcommands from people andrespond autonomously to unfore-seen conditions and events during amission.

Supervisory control mixes man-ual and automatic control. Althougha human teleoperator has primarycontrol, flexible automation or adap-tive robotics may do segments ofthe operation. In this mode, plannedtask segments are performed on

cooperatively designed subsystemsunder automatic control, while theoperator handles contingencies.Supervisory control is the recom-mended technique for remote serv-icing on the initial operating configu-ration of the Space Station. Asoperator confidence and tech-niques of automatic controldevelop, more tasks will be per-formed automatically. When we addintelligence and the ability toresolve contingencies, supervisorycontrol will gradually evolve towardautonomous robotics.

ATL provided the system architecturefor the video -processing section of theSTV system and designed the hardwaresystem for the bandwidth -compressionmodules. It also did computer simula-tions of various bandwidth compressionalgorithms and computer hardwareemulation of the selected algorithm andthe rest of the color processing providedby the STV system. ATL's real-time,two-dimensional, cosine -transform pro-cessor occupies only two circuit boards ofthe STV system's airborne digital unit,and consumes less than 25 watts. Itoperates on composite Y, I, and Q fieldsseparately, and processes the image in16 x 16 blocks of pixels.

Satellite attitude determination

Remote servicing operations on satel-lites require docking to a specific fixture

on the target satellite. Currently, the ren-dezvous and docking manuevers aredone manually, and each docking opera-tion requires about 16 hours. Automa-tion of the rendezvous and docking taskis identified as a target for early applica-tion on the Space Station because moreand more docking manuevers will beperformed with the increased numberof servicing missions planned for the1990s and beyond.

To manuever to the proper side of thetarget satellite we must determine therelative attitudes of the satellite and theapproaching vehicle. NASA and aero-space contractors currently are develop-ing various sensing techniques, includ-ing various laser -based schemes as wellas methods that rely on camera -videoprocessing. Under the direction ofAED, we have developed a techniquefor determining the attitude of the target

satellite, which uses camera video as itsprimary sensor signal. On the imageplane of an RCA CCD camera we detectthe locations of an array of retro-reflective stickers attached to the sur-face of the target satellite. We search forthe optimum match between mathemat-ical projections of a geometric model ofthe reflector locations and the actualdetected reflector positions.

Our test fixture (Fig. 2) supportsdemonstration of attitude computationover a range of angles of rotation aboutthe x, y, and z axis under a variety ofambient lighting conditions. Currentperformance is accurate enough-within 2° on each axis-to automaterendezvous and docking to within sev-eral feet of contact. Other techniquesthat offer higher accuracy over closeranges may then provide the finalguidance.

Pierson: Advanced robotics technology 31

Fig. 2. Attitude determination test fixture.

Telerobotic demonstration testbed

ATL's telerobotic demonstration testbed(Fig. 3) provides a physical environmentfor verifying new control techniquesand mechanisms. The control room isnext to the robot manipulator room.The curtain on the window may be leftopen. This simulates operation on theshuttle, where the astronaut controls theremote -manipulator system while look-ing out the aft windows into the cargobay. To simulate remote operations, thecurtain is closed, and the console pro-vides all cues to the astronaut.

A camera mounted on the wrist of therobot manipulator provides primaryfeedback to the operator. Other camerasprovide orthogonal peripheral views.Other feedback includes computergraphics of robot motions and forces,and synthesized speech. The operatoruses joysticks to command robotmotions or forces, and voice or key-board entry for higher level sequencedescriptors.

The robot has a set of interchangeabletools: a gripper, nut -runner, pointprobe, and location tool (for registeringthe coordinates of objects within theworkspace of the robot coodinate sys-tem). Figure 4 is a sketch of the gripper,

Fig. 3. Teleoperations and robotics testbed.

and how it connects to the quick -changewrist.

Prototype mechanisms-designedand built by ATL and AED engineers-include umbilical connectors, fluid con-nectors, panel covers, orbital replace-ment units, and complementary grippersystems. They are tested and assessedfor remote robotic exchange using thetelerobotic testbed.

Natural language voice interfacebetween man and robotic systems

In future space operations, robots willwork side -by -side with astronauts toaccomplish tasks neither could doalone. Voice control of robot activitywill be required for efficient operation,especially in the external environmentswhere astronauts wear space suits.

ATL's Speech Recognition, ArtificialIntelligence, and Robotics Laboratoriesare jointly developing a natural man -machine interface for robotics control.Their long-term objective is an AI natu-ral language interface integrated withAI expert systems software. The robotwill be able to respond to sentences spo-ken by anyone. This will make thehuman comfortable and allow for aconversation -like dialog between manand machine.

The initial development uses interac-tive, natural -language, voice recogni-tion and synthesis to control the pan,tilt, zoom, and focus of two perimetervideo cameras of the telerobotic testbed.

During execution of remotely con-trolled robotic tasks, the viewpoint ofthe camera systems may have to change

frequently. Today, operator may controlthe robot motions, while a second oper-ator controls camera positions. Or, oneperson could alternately control thecamera and the robot. Both scenariosare inefficient. However, continuousrobot and camera control is possible bya single operator, who could control thecameras by voice, while simultaneouslymanipulating the robot -control joy-sticks. The interface recently developed,Fig. 6, includes a continuous -speech rec-ognizer, speech synthesizer, and natural -language parser integrated with expert -system software. It currently under-stands 100 words, which limits freedomto some extent, but demonstrates signif-icant improvement over fixed -syntaxvoice control. A message generator pro-vides spoken feedback to confirm thatthe system understood the operator'scommands, or to ask the operator torepeat the command. The speech syn-thesizer provides a parallel means forthe system and the operator to commu-nicate in command input and systemfeedback.

Predictive graphic display

The problem of effectively controlling arobot through communication linkswith long time delays (such as would beexperienced at GEO or polar orbits) hasnot been solved. The operator that pro-vides velocity commands must know thereal position of the robot; otherwise hemight send the robot right through deli-cate satellite surfaces.

ATL is developing predictive feed-back techniques that improve the opera -

32 RCA Engineer 31-1 Jan. / Feb. 1986

tor's ability to control distant roboticactivity. For example, real-time graphicdisplays of the commanded robot posi-tion will appear as graphic overlays onthe real (delayed) camera views of therobot in the workspace. Before robotmotion starts, the operator will see astick figure of the robot superimposedon the camera view of the robot. As theoperator provides velocity commandswith the joystick, the stick figure willmove away from its previous position,and indicate in real time the com-manded positions of the robot. Thecamera view of the robot will catch-upto the stick -figure view after the round-trip time delay is completed. This tech-nique will simulate real-time perfor-mance and overcome most problems ofremote control of robot position withlong time delays.

The graphic preview system will alsoshow the operator what will occur dur-ing the next pre-programmed motionsequence. The operator may then see ifsuch motions are appropriate in the realworkspace, and observe interference byany obstacles that were not anticipatedby the programmed motions. The oper-ator could avoid the obstacle throughjoystick control and then resume pro-grammed task segments.

Force/torque control

An industrial robot is controlled pri-marily by executing a sequence ofmotions described by changes in its posi-tion. This is satisfactory if everything inthe workspace is controlled to tight tol-erances, or if objects in the workspacecan orient themselves to comply withthe exact positions of the robot gripperor end -effector. Many satellite objects tobe serviced will not do this. Many simpleoperations, such as opening hinged pan-els, require the robot to move along pre-cise trajectories defined by the elementsin the workspace, rather than by therobot. Operations may require controlof terms of force to break work objectsloose from their previous position, thenin terms of position to move them tonew locations, then again in terms offorces or torques to seat them in theirfinal postion. Industrial robot control-lers that only control robot positions areinadequate for many satellite servicingtasks.

ATL is currently integrating a robotcontroller, control language, andmanipulator/end-effector drive elec-

WRIST MOUNT FLANGE

AIR LINES

COOLANT. HYDRAULICVACUUM PORTS

ELECTRICAL INTERFACE

TOOL HOLDER

TOOL

TOOL STAND

Fig. 4. Quick -change robot gripper

tronics to sense and control sequences offorces and torques, as well as executesequences defined by position changes.Planned demonstrations include open-ing hinged panels, unfastening boltedobjects and refastening them to pre-scribed torques, and mating and unmat-ing electrical connectors where one partis firmly mounted to a stationary paneland the robot gripper holds the other.

3D robot vision

Many teleoperation tasks will deal withthe mating of two three-dimensional

objects. Such tasks would be difficult todo with joystick control, even if theoperator has stereo or orthogonal viewsof the work objects. We can automatesuch sub -tasks by suitable interpretationof 3-D range imagery and computergeneration of required motions.

ATL has demonstrated a structuredlight range imaging system that can gen-erate range maps of a robot workspace,with resolution of less than one tenth ofan inch at rates up to four frames persecond. We are developing techniques ofinterpreting those images to yield preciseorientation and position information of

Pierson: Advanced robotics technology 33

VERBEXCONN. SP.RECOGNIZER

DECTALKTEXT -SP.SYNTHESIZER

-PAN CAMERA 1 LEFT.--ZOOM IN CAMERA 2. -

IBM PC

A.I.NATURALLANGUAGEPROCESSING

VICONCONTROLLER

ROBOTICSCONTROLPROCESSOR

PAN 1

TILT

PANILT

FOCUSZOOM

-EL2 FOCUS

ZOOM

Fig. 5. Natural -language interface for robot control.

objects to be manipulated in the work-space. After the parts touch, mating ofobjects is completed through force/torque feedback and control.

Future development projectsFuture development projects willinclude integrating ATL's VLSI capabil-ity to incorporate more intelligence atthe remote site. Custom high-performance VLSI -based processorswill be required to compute robot jointmotions and forces in real time, in

response to sensor inputs processed dur-ing robot actions. Real-time sensor pro-cessing, particularly vision, will alsorequire new circuit technology for use inremote locations with minimum physi-cal hardware and power.

Expert systems will be developed tointegrate outputs from multiple sensorsand intelligently process the appropriatesignals for the task. Expert systems willalso be required to plan and replan tasksand motions when unanticipated obsta-cles are detected, identified, and dealtwith while accomplishing tasks that

were defined as high-level goals ratherthan as specific trajectories or forces.

Improved word -recognition algo-rithms will accept speaker -independentconnected speech with an increasingvocabulary. Natural language interfaceswill interpret the astronaut's spokenwords and respond in natural speech.Astronauts in space suits will then beable to communicate naturally andcomfortably with robotic "astronautapprentices" that help complete tasks,retrieve tools or parts, advise the astro-naut of procedural steps, and inspect thequality of completed tasks.

Conclusion

ATL's advanced sensor systems,machine vision systems, computerarchitectures, artificial intelligence soft-ware techniques, word recognition sys-tems, and VLSI designs all contributesignificantly to answering emergingtechnical needs for servicing satellites inremote orbits in space. The desire for,and cost saving potential of, increas-ingly autonomous robotic servicing sys-tems in space will provide an increasingneed for these technologies. It should

to do so through the 1990s andwell into the twenty-first century.

Paul Pierson is the Manager of ATL's RoboticsLaboratory. He is responsible for thedevelopment of robotics technology andapplications, and for associated disciplines.Prior to coming to ATL, he was Manager ofSoftware Review and Evaluation in RCA'sSelectaVision Videodisc Operations, where hewas responsible for video and audio processingsystems used in disc mastering, and for thequality of the tapes and the master discs used toproduce discs. Before that he was a ProgramManager in the Government Systems Division,responsible for high -resolution laser beamrecorder development programs. Paul receiveda BSEE degree from Case Institute ofTechnology and an MSE degree in SystemsEngineering from the University ofPennsylvania.Contact him atAdvanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6502

34 RCA Engineer 31-1 Jan. / Feb. 1986

E. Alexander R. McClain C. Tsikos B. Siryj R.M. Carrell

Advanced technologyfor mail processing in the 1990s

RCA has taken an adventurous approach to help the PostalService handle the increasing volume of mail.

The U.S. Postal Service (USPS) cur-rently processes and delivers over 120billion pieces of mail per year, and thisnumber doubles every 20 years. Whileletter mail processing has been highlyautomated, processing of other mailtypes is still very labor-intensive. To off-set rising costs of labor and employeebenefits that lead to increases in postagerates, the Postal Service has pledgeditself to a long-range productivityimprovement program, using the latesttechnology developments. Advisorycommittees and a Technology ResourceDepartment have been set up within thePostal Service to conduct research inspecific technologies, such as machinevision and electro-optics, robotics, arti-

Abstract: RCA is under contract withthe U.S. Postal Service to researchmachine vision for robotic handling ofirregular parcels and to construct anexperimental robotic feeder mechanismthat can "see" and handle large "flat"envelopes and magazines. This articlediscusses the postal requirements thatgive rise to these technology needs, theobjectives of the research undertaken,and RCA's unique technical approachesto the automated postal system of the1990s.

01986 RCA Corporation.Final Manuscript received November 20, 1985Reprint RE -31-1-6

ficial intelligence, and man -machineinterfaces. Research in these technolo-gies, viewed as critical in the quest forautomation and worker productivityimprovement, is being conducted underPostal research and development con-tracts by a variety of industrial and aca-demic research organizations.

Evaluating robotics for futurepostal operationsMost mail in the postal system consistsof ordinary business envelopes. Theyare handled by automatic machinerythat accepts mailpieces within a specificrange of sizes and shapes. There is aresidue, however, that the existingmachinery cannot handle. This residuecomprises a large part of the immensemail volume and is, thus, a significantproblem that costs over two billion dol-lars each year.

One category of this residual mail isknown as irregular pieces and parcels(IPP), which includes small boxes, filmmailers, rolled newspapers, hotel keys,and small bags. Another group,"flats," consists of generally flat mail -pieces, such as tabloid weekly newspa-pers, magazines, oversized envelopes,packs of inquiry cards, and bank state-ments (stuffed envelopes). Open maga-zines, without sleeves, are especially dif-ficult for machines to handle. This typeof material includes much of the period-

ical and advertising mail, which bringslittle revenue but requires a large laborforce for processing.

The fundamental tasks in mail han-dling are singulation, facing, Zip -codereading, and sorting. Singulation is theprocess of separating one mailpiecefrom a pile, a stack or a jumble on aconveyor. The many attempts to singu-late residual mail have been variationsof conventional material handling tech-niques such as differential motion orspreading. These techniques work wellwhen the machines are designed for auniform stream of a known product,but the techniques often fail for uncon-trolled mixes of unpredictable products.

The USPS is sponsoring parallelwork with several contractors in eachaspect of non -letter -mail processing.Some of these contractors are trying toupdate the traditional technology inthese fields. RCA chose the technicallymore adventurous path of investiga-tion-robotic technology with emphasison machine vision and programmablemachines.

Our initial contract, "Machine VisionResearch," required a search formachine vision technology that couldanalyze a pile of irregular parcels andpieces and direct a programmablemachine to singulate it. After we ana-lyzed 79 research papers and visited uni-versity and industrial laboratories, weconcluded that a range image was the

RCA Engineer 31-1 Jan. / Feb. 1986 35

Fig. 1. Intensity images (left) with corresponding range images.

most promising technique for 3-Dmachine vision.

A range image of a scene replacescoordinates X, 1.; and Z with X, Y, andintensity. To the eye, shapes will haveabnormal shadings and no surfacemarkings. A normal scene and its cor-responding range image are shown inFig. 1. There are two feasible ways toobtain a range image-structured lightand laser ranging.

While RCA has built laser rangers inthe past and several experimentalmodels have been reported in the litera-ture, these functioned at long rangesand were slow. In the last year or so,progress has been made in laser rangingat short distances, but for the postalapplication we recommended a struc-tured light technique' that is detailed inthe section on coded mask projection.We were subsequently awarded a con-tract extension to perform a laboratorydemonstration of this method using the

resources of ATL's Image TechnologyLaboratory.

A second contract was awarded toRCA for Advanced Feeder Research.This requires us to develop and con-struct a feeder that can take a wide rangeof generally flat mail, and singulate it atthe rate of one piece per second with 97 -percent efficiency. For this contract,ATL has provided a robotics researchfacility that consists of a PUMA 762robot and an IRI D256 vision system.We chose this equipment not for speed,but for versatility. Besides being used todevelop technology for the Postal Ser-vice, the equipment is serving militaryand space programs, such as those todevelop robots for repair and mainte-nance of spacecraft.

A main requirement of the advancedfeeder system is the ability to recognizeand locate a single piece of flat mail(usually the top piece in a pile) automati-cally and then direct the robot to pick it

up properly. The findings of themachine vision research on IPP prob-lems were put to use to solve the "flats"problem.

Machine vision requirementsThe apparent ease with which humansinterpret the many elements of a sceneconceals the great complexity of the pro-cesses involved. To emulate vision inmachines we must carefully define justwhat is needed and find ways to reducethe complexity of the scene so it can beprocessed within the time and comput-ing resources available.

Often, we simply need to knowwhether an object is there or not; simplereflective or transmissive sensors willdo. For inspection, the shape anddimensions are needed (Are the holes allthere? Are they the right size?). Silhou-etted images are commonly used,because only binary (black and white)images with minimum data are pro-duced. Usually, the job is to identify,measure, or locate known objects.

For the Postal application, theobjects are not known; they vary widelyin size, shape, surface markings, andattitude, and they are not separated.This closely resembles the classical bin -picking problem that has never beensolved in the general sense. (The bin -picking problem is the robotic emula-tion of the human ability to reach into abin of parts and select and orient onepart. Assembly operators do this withease, but vision -aided robots can onlydo it for known parts.)

Once a mailpiece is found and singu-lated, there are other tasks. The addresslabel must be found, and then the Zipcode. Finally, the Zip code must be read.Mailpieces, especially parcels and maga-zines, may be covered with distractingpatterns that effectively camouflage theaddress label. If machine location andreading of the label fails, an image of themailpiece is transmitted to an operatorstation where the Zip code is located,read and manually keyed.

Machine vision techniquesThe development of machine vision sys-tems to perform these functions is achallenge. If the human visual systemhad not been so successful at extractingmeaningful information from a two-dimensional array of grayscale num-bers, workers in the field might have

36 RCA Engineer 31-1 Jan. / Feb. 1986

given up on the problem long ago. Thehuman visual system processes imagescreated by the IGRP factors: illumina-tion, (surface) geometry, (surface)reflectivity, and (camera perspective)projection. The transformation fromscene to image is many -to -one and,hence, noninvertible. One cannot takean image and "solve" for surfaceshapes and reflectivities. The interac-tion of IGR factors and the ambiguityof the perspective projection combine topresent an extremely complex interpre-tation problem.

Most industrial machine -vision appli-cations have relied on optical ormechanical ways to simplify the prob-lem by selectively eliminating IGRP fac-tors during the image generation proc-ess. For example, when a letter isimaged in an OCR machine, the surfacegeometry is flat and the illumination isuniform; hence, the images indicate sur-face reflectivity. Structured lightingtechniques are often used to illuminatethree-dimensional scenes with an angu-larly modulated light source, such as aplanar projection of light that forms astripe on the scene. A strong light sourceis used, so the stripe can be reliablydetected despite ambient illumination(I) and varying scene reflectivity (R).Projection (P) ambiguity is eliminatedbecause of the known geometrybetween the light source and the cam-era. Hence, structured light providesdirect access to geometric information,such as range to a surface or surfaceshape.

Coded mask projection

ATL developed two structured lighttechniques for the USPS. The more gen-eral method, after Inokuchi,' is illus-trated in Fig. 2. A point source of lightilluminates the scene through a series ofmasks that project wedges of light withwell-defined geometric boundries. Themasks contain a binary- or gray -codedseries of patterns, and a camera viewsthe scene from a different angle. Eachpixel on the camera sensor projects anarrow cone of perception that inter-cepts the projected wedges of illumina-tion at geometrically defined points.These points are unambiguously identi-fied by the mask code; they will be illu-minated by some masks and not others.

For a voxel resolution of 256 by 256by 256, eight masks are projected. (Avoxel is a volume element; a three -

LIGHTSOURCE

PATTERNPROJECTOR

MASK 1 MASK 2

MASK 3

MASK 3

CAMERA

128 LINEPAIRS

MASK 9

Fig. 2. Inokuchi structured -light techniques for range imaging.

dimensional pixel.) Each image isbinary and is mapped to one level of aneight -bit memory. The code in each bytecan be directly interpreted as a range.The basic triangulation scheme yields animage in polar coordinates that is cor-rected by a lookup table.

This process is straightforward forobjects of uniform reflectivity viewed ina dark room. For mailpieces in roomlight and with surface markings, we can-not be certain whether a specific point inthe scene is illuminated by a particularmask. To resolve this, we take two moreimages-one with the projector off; asecond with the projector on, but withno mask- so all points are illuminated.For each point that the camera sees, wesplit the difference in intensity in the twoimages to form a threshold for compar-ing each masked image. The success ofthis technique is demonstrated in Fig. 1,

where surface markings are removedfrom the range image.

This technique is fast and modest incomputational requirements. The pri-mary time required is to change themasks. We expect to use a custom liquidcrystal cell that operates in the disper-sion mode and should change mask pat-terns in 50 ms.

Nextpiece location

In the advanced feeder research system,layers of scattered flat mailpieces arepresented to the vision subsystem,which selects the next (usually top) mail -piece to be picked up. Here, the generalshape and attitude are known. There-fore, it is possible to use a simpler struc-tured light technique.

The vision subsystem's camera viewsthe mailpieces on a conveyor from

E. Alexander/R. McClain/C. Tsikos/B. Siryj/R.M. Carrell: Advanced technology for mail processing in the 1990s 37

TYPICAL SCENE OF FLATS.

- - TOP SIDE

BOTTOM SIDE

PROCESSING TOFIND THE TOPMOST PIECE.1. EXTRACT & LABEL

EDGES2. IDENTIFY REGIONS3. FIND REGION TOTALLY

SURROUNDED BY"TOP SIDE" EDGE.

Fig. 3. Method used for finding the top piece in a pile of mail.

above. The camera image is processedby an algorithm that identifies the top-most piece. The process consists oflocating edges in the scene, using theedges to break up the scene into regions,and labeling the regions by examiningthe type of edge that surrounds eachone.

Figure 3a shows a simple case consist-ing of three flats. In Fig. 3b, the edgeshave been identified, and they break upthe non -background area into threeregions. For each region, all pointsalong the edges have been labeled aseither the top side of the edge (denotedwith a broken line) or the bottom side ofthe edge (denoted with a dotted line).Only the region associated with the toppiece is totally surrounded by edges thathave been labeled as the top side of the

edge. To identify a top piece, we deter-mine which regions are totally sur-rounded by these "drop" edges.

To find the drop edges, we projectlight stripes from an angle and note thedirection of the discontinuity in thestripe as it passes over the borderbetween two mailpieces. If the secondpiece is lower, the stripe "drops" to thenext surface and is displaced along thepath of projection (Fig. 4.) At each dis-continuity, we know the direction of thedrop because we can derive the height ofthe surface at each point along the stripefrom the location of the stripes in thecamera image. Two stripe images areacquired and analyzed, but the stripedirections in one image are rotated 90degrees from the direction in the otherimage. This guarantees that all four

Fig. 4. Use of structured lighting (stripes) toobtain geometric information on flats.

edges of the top -most flat will intersectmultiple stripes. The two stripe imagesare logically combined and analyzedinto groups that correspond to surfaceregions (Fig. 3b). With the stripe imple-mentation, edge sampling only occurs atthe intersection of the stripes with theedges. After the stripes are grouped intoregions, the identification of top -mostflats involves typing the stripe disconti-nuities as "drop discontinuities."

We have investigated interpolation ofpixel samples across the stripes as a wayto increase the resolution of the imagingsystem and allow discontinuity detec-tion for ever thinner flats. For thismethod to work, there must be no ambi-guity as to which stripe is seen. Because

38 RCA Engineer 31-1 Jan. / Feb. 1986

the stripes are projected from a 45 -degree angle, the stripe image moveshorizontally as a surface rises. If the sur-face is high enough, the movement canequal or exceed the nominal spacingbetween the stripes. Now there can be anambiguity about which stripe is seen atany point in the scene. We can devisevarious rules for keeping track of thestripes, but various mailpiece positionscan defeat them.

There are only two robust ways ofidentifying the stripes: spacing and cod-ing. The coding method (describedabove) requires multiple images. For thefeeder project, we spaced the lines 1.5inches apart and restricted the mailpiecelayer thickness to two inches. Widerspacing might miss small mailpieces;closer spacing would require us torestrict the layer thickness even more, oruse a simple coding scheme.

In flat -mail processing, unbandedmagazines present a particularly diffi-cult problem. A suction cup pick-updevice can adhere to the cover, but themagazine will fan apart if the cover ispulled away. The next section describesa gripping tool that lifts the bound edgeand moves a support under the maga-zine. For this to work, the bound edgemust be identified. One way of doingthis is to get a closeup of the mailpieceedge through a telephoto lens, and thenanalyze the texture with two convolu-tion filters. One filter emphasizes thetexture of the cut paper edges; the othersuppresses it. By comparing the filteroutputs for the edge's image, we candetermine if the edge is unbound (show-ing a paper stack) or bound (not show-ing the stack). The details of the wholesystem are beyond the scope of thisarticle.

Grasping the mailpiecesIn robotics technology, the functioningdevice at the end of the "arm" is knownas an "end effector" or "end -of -armtooling." There are some more -or -lessstandard versions on the market today.Most are two- or three -jawed clampswith very specific capability, but theyare not versatile enough to handle partswith unknown or consistently varyinggeometries. In this article, we use theterm "gripper" to refer to an end effec-tor that is custom designed to handle avariety of flat mail.

Usually, the mailpieces are presentedto the gripper in a disoriented pile. It is

Fig. 5. The mail gripper is designed to grasp a flat mail piece in a manner similarto the way a human hand clamps an object between the thumb and fingers.

not good practice to slide the mailpiecestogether when manipulating the pile,because edges tend to catch on othermailpieces that have bent corners orpartially detached labels. This is partic-ularly true if the pile contains unbandedmagazines.

We concluded that the optimum wayto depile and then singulate a stack is toremove the top piece first and then thenext one, and so on, without sliding anypiece. This approach closely approxi-mates the way humans would removethe mailpieces, one by one, starting atthe top of the pile.

The approach to singulation using arobot arm with a gripper is to lift themailpiece in place and then move it to asingulation conveyor. For most enve-lopes, we can do this easily with the helpof suction cups. In handling unbandedmagazines, however, the task becomesmuch more difficult. The suction cupswill attach themselves only to the topsheet(s), leaving the rest of the pagesunsupported except at the bound edge.It is not usually possible to lift heavymagazines by just holding onto thecover, especially under high accelera-tions. One way to solve the magazineproblem is to locate the bound edge (dis-cussed in the preceding section), lift it upslightly, place a support under it, andthen clamp the magazine in place, muchlike the human hand grasps an objectbetween the fingers and thumb (seeFig. 5).

As previously mentioned, the USPShas specified that mailpieces shall besingulated at a rate of one per second.(This is the current rate for keyboardentry of Zip -code data by postal opera-tors.) To achieve this throughput, wehave allocated specific times to machinevision, robotic arm movements, and

gripper action. The goal set for the grip-per is to pick up a mailpiece in 200 ms.Associated with this very short pickuptime are high accelerations and periodicrequirements for high energy. To ensurethat a mailpiece will not be damagedduring the pickup cycle, we need to con-trol accelerations by programming thepickup motion.

We chose the following design goalsfor mailpiece singulation:

The gripper shall be capable of pick-ing up all "nonmachinable" and"machinable" flat mailpieces, in-cluding unbanded magazines.

To preserve mailpiece integrity, thegripper shall pick up all mailpieces inplace without sliding them, especiallywhen dealing with unbanded maga-zines.

The gripper shall curve (crimp) eachmailpiece to stiffen it during trans-port, if possible.

Programmed accelerations shall beused during mailpiece pickup.

Once the robotic arm and gripper arepositioned at the top surface and anedge of a mailpiece, the gripper shalltolerate a thickness variation of oneinch.

The performance goal for the gripper isto pick up a mailpiece in 200 ms.

The general use of vacuum or suctioncups for lifting or holding is a well-known art. The unique aspect of thePostal application is that the suctioncups have to attach themselves to differ-ent, nonuniform, and sometimes po-rous materials. Another problem is wemight lose the vacuum when picking upa piece-such as a stack of papers in avery pliable envelope-and, as a result,the piece forms a bag (Fig. 6). A similarcondition might occur when picking up

E. Alexander/R. McClain/C. Tsikos/B. Siryj/R.M. Carrell: Advanced technology for mail processing in the 1990s 39

The postal technology program

In 1983, the U.S. Postal Service(USPS) made a significant changein its organization for technicalresearch and development. In thepast, such work was conducted bythe USPS Laboratories in Rockville,Maryland, with the support of pri-vate sector contractors and othergovernment research activities.RCA has performed several techni-cal contracts for the USPS Labora-tories, including experimental sys-tems that Advanced TechnologyLaboratories (ATL) designed forparcel sorting and voice Zip coding.In addition, the Communication andInformation Systems Division(CISD) completed a series of elec-tronic mail studies and experimen-tal system designs that culminatedin the national implementation ofthe E-COM system for processingelectronic computer -originatedmail.

The reorganization in 1983directed the USPS Laboratories'role to technical support of thePostal Operations Group. Responsi-bility for advanced research wasassigned to a Technology ResourceDepartment at postal headquarters,with the mandate that research beconducted by the best qualifiedindustrial and academic researchorganizations. The Technology

Resource Department operateswith oversight by various USPSexecutive committees and with thedirect support of a consulting engi-neering staff provided by the ArthurD. Little Corp. Further, it is subdi-vided into an Office of OperationsResearch and Systems Require-ments and an Office of AdvancedTechnology.

The main objective of currentpostal research is productivityimprovement through automation.Postal workers are generally wellpaid, both in salary and benefits.Unless their productivity can beimproved by increased use of auto-mation, normal wage -rate escala-tions will continue to produce cor-responding postage rate increases.Because the amount of mail han-dled grows annually, automationcan reduce the labor content ofprocessed mail and producedesired cost savings without layoffs.To date, significant use of automa-tion has been limited to letter mailthat is uniform enough to permitrapid, consistent mechanical han-dling. The thrust of the currentresearch that the TechnologyResource Department sponsors isto identify and develop techniquesfor processing irregular parcels,"flats," and periodicals in produc-

tion systems designed for the 1990stime frame. Toward this end, spe-cific requirements have been identi-fied for parallel research award inseveral technical areas.

To establish a community ofqualified research organizations,the Office of Advanced Technologynegotiated basic -ordering agree-ments with universities, researchlaboratories and manufacturerswho have qualifying experience andfacilities to work in one or more ofthe following areas:

Materials handling Electro-optics and character

reading Man/machine interfaces Code printing, scanning, and

labeling

RCA has established its qualifica-tions for the first three of thesetechnical areas and is now undercontract to conduct research inmachine vision for sorting irregularparcels, and create a researchmodel of a robotic feeder mecha-nism for obtaining a variety of flatmailpieces from a random pile anddelivering the pieces in a singlestream for address reading andcoding.

RCA established its qualifications

Fig. 6. Suction cup gripping very pliable envelope.

a heavy magazine near its bound edge(Fig. 7).

Single sheets of paper or very lightmagazines present yet another problem.If the suction cup is large, it tends to

wrinkle the paper; the center of the cupis an apex. Quite often, air passageforms wrinkles that produce imperfectsuction cup adhesion, venting the cupvacuum.

Results we observed during static test-ing led us to the following conclusionsabout suction cup design:

The lip of the suction cup should be asflexible as practical restraints will per-mit.

The diameter of the cup should besmall. If additional lifting force isrequired, then several small cupsshould be used. An added advantageof the small cup is that the air volumeis small, so the cup can be evacuatedand then pressurized in a shorter timethan a larger cup.

Bellows type suction cups behave bet-ter than standard suction cups.

The proposed gripper design is shown inFig. 8. It consists of two basic compo-nents: the pickup/pressure pad and thesupport platen. The energy source is aconstantly rotating motor/flywheel that

40 RCA Engineer 31-1 Jan. / Feb. 1986

for the basic ordering agreementson the strength of the broad techni-cal capabilities found in our Corpo-rate divisions. Current programs arestaffed by engineers fromAdvanced Technology Laboratories,RCA Laboratories, and the Com-munications and Information Sys-tems Division. The work is plannedand directed by a Program Manage-ment Office that was recently trans-ferred from Camden to ATL's newlocation in the Moorestown Corpo-rate Center. Eugene M. Alexander isthe RCA program manager respon-sible for all current contracts withthe Postal Service. Mike Carrell ofRCA Laboratories serves as seniortechnical consultant for the work inmachine vision and robotics. Thework currently in progress is staffedprimarily by members of three ofATL's laboratories: the Robotics Labunder Paul B. Pierson, Gerry Claf-fie's Optical Devices Lab, and Wil-liam Ealy's Image Processing Lab.Future projects in the man/machineinterface area could include partici-pation by ATL's Artificial Intelligenceand Software Laboratory, the Mis-sile and Surface Radar Division'sHuman Factors and IndustrialDesign organization, and RCA Lab-oratories' Video Systems special-ists.

is coupled and decoupled from the twobasic components by two spring clutch/brakes. A dc source drives the motorand provides versatility, easily varyingthe speed and cycle time of mechanismmotions and accelerations. Timing beltstransfer rotary motions, while a sinusoi-dal drive picks up mailpieces. Reflectivedetectors provide position and statusinformation on the pick-up pressurepad and support platen to the control-ling electronics.

Figure 9 describes the mailpiecepickup and drop-off cycles in detail,while Figs. 10a -10e depict the physicalpositions of the gripper and mailpiece.

For many flat mailpieces, principallylarge manila envelopes, it may not benecessary to hold the piece against theplaten mechanically; the vacuum cupsalone can support the load stably. Theadvantage of this approach is that we

Fig. 7. Gripping heavy magazine by bound edge.

Fig. 8. Design of gripper for flat mail handling.

can reduce the 200 -ms cycle to 133 ms byeliminating the platen -actuation cycle.The disadvantage is the additional bur-den placed on the mailpiece identifica-tion (vision) system.

Progress and projectionsThe PUMA robot was installed in thefeeder testbed in July 1985 and, byNovember, we were able to demonstratesuccessful singulation from scatteredlayers of flats on a conveyor (Fig. 11).We are now integrating the componentsof the system into the testbed. Transfer -

cycle times that average 4.7 seconds permailpiece have been measured using asingle suction cup attached to thegeneral-purpose laboratory robot. Thiswas achieved even though image proces-sing presently requires 5 seconds and therobot cycle consumes 3 seconds. (Timeis saved because two or more accessible"top pieces" are often found andfetched for each image processed.)

Future plans include modifying thetestbed to handle IPPs. An upgradedvision system is planned that will obtainthe contours of varying three-dimen-sional objects using available processing

E. Alexander/R. McClain/C. Tsikos/B. Siryj/R.M. Carrell: Advanced technology for mail processing in the 1990s 41

END SUPPORTPLATEN CYCLE

765°

405°

MAILPIECECONTACTSSUPPORT PLATEN

MAILPIECE BEINGCLAMPED TO PLATEN

STOP MAILPIECE DROP OFF CYCLE(RELEASE MAILPIECE ONTOSINGULATION CONVEYOR)

540°

STOPR MAILPIECE

PICKUPCYCLE

Nr,START MAILPIECEDROP OFF CYCLE

MOTIONS AREIN PHASE

675°

START SUPPORTPLATEN CYCLE

LINK (Li)POSITION

PICKUP/PRESSURE PAD STATUS SUPPORT PLATEN STATUS

0 = 0 AT ITS HIGHEST POINT (CUPS ARENOT COLLAPSED).

OFF

1 = 180° SUCTION CUPS ARE ATTACHED TOMAILPIECE.

OFF

2 = 315° PAD & MAILPIECE ARE ALMOST AT PLATEN STARTS TO MOVEINTO THE ON POSITION.THE HIGHEST POINT.

38 = 360°

t3 - to - 133 ms

THE VISION SYSTEM HAS DETER-MINED THAT A PLATEN SUPPORT ISNOT NECESSARY. THE PRESSUREPAD (Li HAS STOPPED AFTER ONECOMPLETE REVOLUTION.

OFF

ALL END EFFECTOR DYNAMICS ARE STOPPED.

4 - 405°54 - 12 - 34 ms

PAD & MAILPIECE HAVE STARTEDTO MOVE DOWNWARD. VERTICALPOSITION IS SAME AS IN 1.. 2.

PLATEN IS IN POSITION.

5 540°to - to 200 ms

MAILPIECE IS COMPRESSED ON THEPLATEN.

PLATEN IS IN POSITION -SAME ROTARY POSITIONAS IN t = 4

ALL END EFFECTOR DYNAMICS ARE STOPPED.

MAILPIECE IS READY TO BE SINGULATED BY THE ROBOTIC ARM.

6 8 - 675°PAD & MAILPIECE ARE ALMOST AT PLATEN JUST STARTED

TO MOVE INTO THE OFFPOSITION.

THE HIGHEST POINT - SAMEVERTICAL POSITION AS t = 2.

70 = 720°

t7-t5= 67 ms

PAD & MAILPIECE ARE STOPPED ATTHE HIGHEST POINT. VACUUM CANBE TURNED OFF IF THE ROBOTICARM IS OVER THE SINGULATIONCONVEYOR.

PLATEN ISMIDWAY BETWEEN ON ANDOFF.

88 = 765°

te - 1.7 = 17 ms

PAD IS STOPPED AT THE HIGHESTPOINT. PRESSURE IS INTRODUCEDINTO THE VACUUM CAVITY, ANDTHE MAILPIECE IS RELEASEDONTO THE SINGULATION CONVEYOR.

PLATEN IS IN THE OFFPOSITION.

SUPPORT PAD OFF MEANS THAT THERE IS NO SUPPORT FOR THE MAILPIECE UNDER THE PICKUP/PRESSURE PAD.

Fig. 9. Mailpiece pick-up and drop-off cycles.

An interesting ancedote

Range imaging by stripe projectionhas been used in some interestingways. One pioneer comWyopened a portrait sculpture studio;the subject sat on a stool while a setof stripe projectors and camerasmapped his head and shouldersfrom all sides. Microdensitometeranalysis of the films produced adatabase used to drive a specialmilling machine that created a bustneeding only finishing touches by aprofessional sculptor. While techni-cally successful, the companydecided the robot business wasmore profitable, and it becameRobot Vision Systems.

algorithms with a 3 -second run-time. Byincorporating a high-speed SCARArobot that alternately serves two inputconveyors (each with its own vision sys-tem), mailpieces will be singulated to theoutput belt at a rate of nearly one persecond. Such a system is depicted in Fig.12.

Using available system components,we expect to achieve the one -per -secondgoal for enveloped flats. Extension ofthis capability to magazines at half thisrate is within reach but, for IPPs , is ayear or two further out.

After appropriate testing and postalevaluation, we can undertake specificprototype designs, with the goal of field-ing production -level systems in the early1990s. The productivity improvementsenvisioned can mean a potential savingsof hundreds of millions of dollarsannually.

References1. Inokuchi S., Sato K., Matsuda E, "Range -

Imaging System for 3-D Object Recognition," 7thInternational Conference on Pattern Recognition,Montreal, Canada, pp. 806-808, August 1984.

42 RCA Engineer 31-1 Jan. / Feb. 1986

Side View of IV.iilpiece Gripper

VACUUM!CONTROLLERS

II(I

PRESSURE

"IN

SINUSOIDAL4) DRIVE

oTHICKNESSNess

COMPENSATORLINDERITiIZEVRN

, . .

-'

----

) _

_ol r

..i.,...

A A11

IL II -1v

i -.- I

LT-Tdi-T--1 " 113,...,1_1I

_)1 , .

.- PICKUP -, r II

......,

I'PRESSURE==. PAD

VACUUM CUP I

SUPPORT

mm

UMWIt

***.mmi-7----j,....

L....,

I

IPLATEN II MAILPIECE STACKi11.1.1.110 - - - I I-I

to.i CONVEVIOR BELT

0 = ou

r-i, II= 180

r3

fi = 315PLATEN BEGINS MOVEMENT

1I A..0 I II

II U.

1-

Q

I

)Fig.10. Positions of gripper in relation tcmailpieces during phases of the cycle...

i11 A MIN 6

li ... - .

1I im

1111

10. MII

1

IlmmI

4 1 = 405PLATEN IN POSITION

r5

11 = 540CLAMPING MOTION COMPLETE

Top View of Support Platen

BELTTO SPRINGCLUTCH BRAKE

SUPPORTPLATEN

MAILPIECE

#1,2 & 3 POSITION #4 & 5 POSITION

E. Alexander/R. McClain/C. Tsikos/B. Si ryj/R.M. Carrell: Advanced technology for mail processing in the 1990s 43

Fig. 11. Flat mail in Advanced Feeder Research testbed.

Fig. 12. Proposed dual -line singulator.

Gene Alexander is Program Manager for allUSPS programs in RCA. During the past severalyears, he has been involved in systemrequirement studies, design projects, andimplementation of systems intended tointroduce the benefits of advanced technologyto postal services. He is currently ProgramManager for the USPS Advanced Research inMachine Vision and Advanced FeederResearch and Development contracts.Previously, he was responsible for overallmanagement of RCAs contracts fordevelopment, implementation, and technicalsupport of the USPS E-COM system. On theElectronic Message Service System (EMSS)study performed for the USPS, he was a keycontributor to the modeling of centralized vs.decentralized mail processing systems, to theParametric Analysis Model (PAM), and to theoverall system economic analyses. He servedas Program Manager for the Evaluation and TestSystem (ETS), which was designed by RCA andinstalled at USPS Laboratories as a workingmodel of numerous electronic mailtechnologies. Gene received a BSEE and anMSEE from the University of Pennsylvania.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6420

Richard McClain is Unit Manager of theMachine Vision Systems group in ATL's ImageTechnology Laboratory. Recently, he wasTechnical Director of the Machine Visioncontract for the USPS. He was responsible forthe development of the structured light 3-Dimaging system. On the Advanced Feederresearch and development project he has beencontributing to the development of special visionalgorithms. In addition, he is directing an IR&Dproject for improving target recognitionsystems. He received BSEE and MEngEEdegrees from the University of Pennsylvania,and he is presently a Doctoral Candidate at thatuniversity.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6457

Michael Carrell is a Member, Technical Staff atRCA Laboratories. He is a consultant on roboticautomation throughout RCA, and recently hasbeen working on the development of theAdvanced Feeder for the USPS. Other projectsinclude mixes of robots and material handling

44 RCA Engineer 31-1 Jan. / Feb. 1986

Grouped around the flat mail feeder test-bed are authors (left to right)Constantine Tsikos, Gene Alexander, Michael Carrell, Bohdan Siryj and RichardMcClain.

systems involved with the production of TVpicture tubes, satellites, phased -array radars,and printed circuit boards. Prior assignmentshave involved work with graphic systems foruse in high -intensity noise. Mike received theBSEE degree from Iowa State University.Contact him at:RCA LaboratoriesPrinceton, N.J.Tacnet: 226-2083

Constantine Tsikos is Unit Manger of theVideo Processing/Robot Vision Systems groupin ATL's Robotics Laboratory. He is currentlydirecting machine vision research for the USPSAdvanced Feeder project. Previously, in theMachine Vision project for USPS herecommended methods for automaticprocessing of irregular parcel post, and he wasthe principal investigator in the structured -lightrange imaging study. Prior to joining RCA, hewas a Research Scientist at Siemens,investigating technology in the areas ofrobotics, image processing, intelligent sensors,and artificial intelligence. Constantine receiveda BSEE degree from National Technical

University of Athens, Greece, and an MSEEdegree from the University of Pennsylvania. Heis currently working toward a PhD in Computerand Information Science at the University ofPennsylvania.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6464

Bohdan Siryj is Unit Manager of theElectro-Mechanical Systems and ThermalSystems group in ATL's Optical StorageLaboratory. Included in his responsibilities isdirection of robotics and optical disk recordingprograms. At present, he is Technical Directorof the electro-mechanical tasks in the USPSAdvanced Feeder project. He is the recipient ofa David Sarnoff Award for OutstandingTechnical Achievement. Dan received theBSME and MSME degrees from DrexelUniversity.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253.6488

E. Alexander/R. McClain/C. Tsikos/B. Siryj/R.M. Carrell: Advanced technology for mail processing in the 1990s 45

W.P. Altman G.M. Claffie M.L. Levene

Optical storage for high performance applicationsin the late 1980s and beyond

RCA is developing high -data -rate, high -capacity opticalrecording systems for government applications that cannot beeffectively addressed by alternate recording technologies.

The vastly increased amount of informa-tion that will be generated by advancedsensors and computing systems must becaptured and stored by a new generationof high -data -rate, high -capacity recordingand buffering systems that provide rapid,reliable access to the stored data. For ex-ample, the Space Telescope to be launchedin July 1986 is expected to generate aterabyte of data per year for its 15 -yearplanned life. A computer -compatible mag-netic tape archive for this data wouldconsist of approximately 100,000 tapes at150 megabytes per tape. As a more dra-matic example, the Space Station, to belaunched in the early 1990s, is expectedto generate 1 terabyte of data per day at

Abstract: Over the last ten years, RCAhas moved optical storage and retrievalsystems from mere concept to reality. Twoengineering models of "jukeboxes" havebeen delivered to the Air Force andNASA. These systems provide access toover 1200 gigabytes of stored informationin six seconds.

Current development effort is beingdirected toward jukebox systems witherasable disk media, optical buffers withextremely high speed data access onerasable media, and optical tape recorderswith very high volumetric storage.

01986 RCA Corporation.Final manuscript received November 20.1985Reprint RE -31-1-7

data rates that can exceed 1 gigabit persecond.

Since 1975, the RCA Advanced Tech-nology Laboratories (An) has been devel-oping optical storage technology to addressspecialized user requirements, such as thoseof the Space Station, that cannot be satis-fied on either technical merit or cost effec-tiveness by recorders intended for the moregeneral purpose commercial market. Figure1 shows a chronological progression ofthese technology developments-a progres-sion to high data rate and high areal pack-ing density via multiple channel recording.Rapid access to the stored data is achievedvia simultaneous access to multiple disksurfaces, or automated disk handlingmechanisms.

This paper briefly describes the mostrecent development work at ATL-opticaldisk "jukebox" recorder, optical disk databuffer and optical tape recorder-develop-ments that will be applied to record atdata rates above 1 gigabit per second andto achieve an on-line storage capacityabove 1 terabyte.

Optical disk "jukebox" recorders'Engineering models of optical disk "juke-box" recording systems were delivered tothe NASA Marshall Space Flight Centerand to the Air Force Rome Air Develop-ment Center in September 1984 andFebruary 1985, respectively. The 14 -inchdiameter disks in these systems are arranged

in an on-line library configuration andaccessed via an automated handling mech-anism similiar in concept to a phonographrecord jukebox. Access is provided to anydata in a store of 10" bits (1250 gigabytes)within six seconds. The optical disks arehoused in protective cartridges at all timesto facilitate handling by both the operatingpersonnel and the disk handling mecha-nisms. Cartridges are moved from the storeto a load station by a precision belt -drivenX -Y transport mechanism. The load stationmounts the disks onto a precision turntableand the disks are spun up to speed so thatdata can be recorded or played back atuser rates up to 25 Mpbs per channelusing focused laser beams.

The NASA system has been interfacedto an image data base management systemusing a fiber optic bus. The Air Forcesystem is interfaced to a Digital Equip-ment Corporation VAX 11/750 minicom-puter to service a developmental imageexploitation system.

NASA Optical Disk System (NODS)

The vast amounts of data from NASAdeep -space probes prompted the develop-ment of an advanced data base manage-ment system. NODS, shown in Fig. 2,interfaces to this system using an advancedfiber optic data bus that can handle peakrates up to 100 Mbps. Packetized satellitesensor data will be archived within thissystem for rapid retrieval by an expand -

46 RCA Engineer 31-1 Jan. / Feb. 1986

1975

1977

Optical DiskTestbed Flexibility for Incorporet

log New Techniques asThey Evolved

1976 I R & D

IR X, 0

Optical Disk JukeboxConcept Development Working Hall Scale Model Mechanism to Transport Dist,

from Storage to LoadingPosition and Back

1978

Optical DiskBuffer Concept

1984-1986

1979

1980Optical DiskEngineering Model(ODEM) 100 Mais Data Pate Demo 5 a 1010 Bas/Disk Sole 5 X10410ER Seined

1981-1982

NASA Optical DiskSystemId Dual Channel SO Mt3/s 128 On -Lane Disks11 Fiber Optic 'Merl acs

1983-1984

Wideband Recorder/Reproducer Multichannel Gas L9S6'' 4 -Channel Design Pro,e 300 trials

1981Photomicrograph of

?4

rkE 9 -Track Recording-s- t w Track to Track Spec.

1981-1984

Fig. 1. Chronological progression of optical storage development at RCA.

ing number of users in the scientificcommunity.

RADC Optical Disk System (RODS)

RODS will store and provide on-lineaccess to large files for the Air ForceAdvanced Imagery Exploitation Program.This program is developing a testbed toevaluate techniques for rapidly manipulat-ing and analyzing reconnaissance imageryand cartographic and geodetic data formapping.

The VAX 11/750 computer interfacedwith RODS provides the intelligenceneeded to manage the storage and retrievalof large files by file name in a very exten-sive data base. Each optical disk containsa directory listing every file on the diskand its location by track and sector num-ber. When a command is received torecord a file, the specified disk is loadedand its directory is input to a controlcomputer in the RODS controller to deter-mine where to locate the additional file.This file is recorded on the disk and itslocation is added to the disk directory.During file requests for playback, the speci-fied disk is loaded onto the turntable andits directory is input to the control com-puter to determine the location of therequested file. Fig. 2. Photograph of NODS.

NN1982-1984ROME (AF) OpticalDisk SystemX Single Channel 25 MRS 128 OnLine DisksII LAN Interlace

Advanced OpticalDisk Recorder

o to 100 MBis Data Bat*10, I Bits/Disk Side14 -inch Disks3 -Beam Gas Laser68 OnL ine DisksRevised Jukebox to, Im-proved MaintainabilityGrowth Provisions- Second Turntable- Additional Write/Read

Heads

W.P. Altman/G.M. Claffie/M.L. Levene: Optical storage for high performance applications 47

Fig. 3. Collage of AODR photos (left to right: eye patterns, AODR, track -to -trackspacing).

Table I. Adaptability to user requirements

Use spiral or concentric data format on disk

- SpiralLong, continuous write/read files at fixed(high) data rateReduced data buffering

- ConcentricImproved data access timeSimplified control

Provide higher continuous user data rate per opticalhead

- Spiral (up to 9-beams/head) up to 450 Mbps- Concentric (up to 9-beams/head) up to 300 Mbps

Provide additional write/read and/or read-only heads- For double -sided disks- To increase data rate- To reduce data access time- For simultaneous write/read

Add second turntable- For improved access to on-line data- Improved capability for simultaneous write/read- For improved reliability

Implement continuous linear velocity (CLV) write/read- For increased disk capacity- Will increase data access time- Requires more complex recorder control

Implement user -specified interfaces

- Control and data ports- Protocols- Data directory approaches

Provide additional on-line disk storage- More than 100 disks within recorder- More than 1013 on-line user bits- Automated disk exchange with external storage module

- less than 60 -second access to 1014 on-line user bits

Advanced Optical Disk Recorder(AODRf

The Advanced Optical Disk Recorder(AODR) shown in Fig. 3 is being devel-oped as an evolutionary version of thedelivered NODS and RODS "jukeboxes."

A key objective of the AODR programis to demonstrate the performance of crit-ical optical, mechanical and electronicsubsystems that could, if necessary, becombined in a modular fashion to providea recording system with significantly in-creased capability. The potential designadaptations are summarized in Table I.This plan for growth in capability isdemonstrated by the top view schematicof the optical table in Fig. 4, where it isshown that one of the two available turn-table positions, and one of the four avail-able translation stage positions at the singleturntable position, are populated. A secondkey objective is to demonstrate operationalreliability and maintainability enhance-ments with respect to the NODS andRODS by providing 1) more convenientaccess to the optics and the disk handlingmechanisms, 2) optical system alignmentcontrol loops, 3) disk write power controlloops, and 4) advanced subsystem statusmonitoring with software -controlled faultisolation.

The recording approach, demonstratedlate in 1984, uses a three -channel argonlaser -based optical system to input/outputuser data at rates up to 100 Mbps and tostore up to 10" user bits per side on a14 -inch diameter disk. This capability isachieved at a disk rotation rate under 30rps and at a corrected read bit error rateless than 10-9 by using an efficient dataencoding algorithm, read -while -write verifi-cation and a two -level error detection andcorrection architecture. The automated diskhandling method achieves less than six -second access to the data from 68 on-line

48 RCA Engineer 31-1 Jan. / Feb. 1986

disks with provision made for future inter-face to an external storage module toachieve automated access to several hun-dred disks in under 60 seconds. The re-corder is configured as a Disk Drive Unit(DDU) containing the electronics, optics,and mechanisms required to write to, readfrom, and handle the optical disk media.The recorder also includes a controllerthat 1) controls and monitors operations,2) buffers, formats and error protects theuser data, and 3) interfaces the recorderwith the host system.

Erasable/reusable recordingAnother enhancement to optical disk tech-nology being tested with the AODR isthe use of erasable/reusable disk mediawith diode laser arrays as write/read/erasesources.

Recent advances in optical media tech-nology have indicated that it is possible toerase and reuse optical storage media withone of several approaches: magneto -optics,phase change, and dyes encased in polymerfilms. The magneto -optics approach hasbeen chosen for the current work becauseof its technical maturity and potentialavailability from multiple suppliers. Themagneto -optic record/playback process isshown in Fig. 5. The sensitive, or recordinglayer is a vertically oriented magneticmaterial in which data is written by impos-ing a localized heated area, caused byfocused laser illumination, in the presenceof an external magnetic field. As the tem-perature of the region approaches a criticalpoint, the coercivity of the magnetic mate-rial decreases such that the magnetic vectorswithin the media will align with a relativelyweak external magnetic field in the heatedregion. Therefore, the direction of the re-sulting local magnetic vector in the sensitivelayer is determined by the direction of theapplied external field, and the size of thisrecorded feature is determined by the sizeof the focused spot. Data is read by reflect-ing a linearly polarized light from thesurface of the sensitive layer. A very smallpolarization rotation based upon the Kerreffect is produced, dependent upon thedirection of the magnetic field in the sensi-tive layer. The data readout signal is de-rived via differential detection of the polari-zation rotation. Erasure of the media tothe original magnetic orientation is accom-plished by the same process as recording,except that the imposed magnetic field isreversed. Because of the similiarity to mag-netic recording, the magneto -optic tech-nique has also been referred to as "thermo-

LASER

LOADER

MI Populated

= Space Provided For Future Addition

Fig. 4. Top view of optical table (AODR).

TRANSLATIONSTAGE

OPTICALMODULE

A. Blank DiskAt ambient temperature Hi t 114 4-

4-M -O Medium

bras field has no effecton medium

i(dc)

B. RecordAt elevated temperaturecaused by laser pulse,bias field exceeds coercivityof medium, resulting inlocal reversal ofmagnetization. Focusedspot size determinesminimum feature size

BiasMagnetic Field

Lens

Focused Laser Beam

tttt tttti(dc)

C. Read via Kerr effectPolarization angle oflow -power CW laserbeam is rotated onreflection from M -Omedium according to_orientation

N

44#tii####

D. EraseReversed bias plusheat from high -powerCW laser restores tooriginal blank disk

+4+44444+

Fig. 5. Magneto -optic record/playback/erase process.

magnetic recording" or "optically assistedmagnetic recording." Being nondestructive,the record -read -erase cycle can be repeatedmillions of times.

Recording with diode laser arraysThe very high data rate, high -capacityoptical recorders developed to date havebeen based upon the use of argon lasers.These lasers require external components

to generate and modulate the multiple,beams that are applied to the disk media.The lasers are large, intrinsically inefficient,and require periodic maintenance. Laserdiodes overcome these limitations and alsoprovide the attractive capability for internalmodulation at very high data rates.' How-ever, they must be very closely spacedand precisely aligned to achieve a multiplechannel source. This is a very difficultchallenge that is not practical for produc-

W.P. Altman/G.M. Claffie/M.L. Levene: Optical storage for high performance applications 49

SHAFT

DISK 1

COLLARASSEMBLY

OPTICALMODULE

Capacity: 1012 BitsData Rate: 109 Bits/Sec

Erasable, Reusable Media

14 -Inch Disks

24 Surfaces

24 Optical Heads Solid -State Lasers 9 -Diode Arrays

8 Data Tracks 1 Pilot Track

Fig. 6. Optical disk buffer concept.

Table II. Projected performance of 12 -disk system

Capacity

Number of user bits/revolution /track

Track densityNumber of tracks/surfaceTotal buffer user data capacity

(24 surfaces)

Data rate

Disk rotation rateUser data rate/trackUser data rate/moduleUser data rate/12 modules

Access time

Time to initial access

1,081,344

8 tracks/13.3 pm37,8130.98X1012 bits

15.413 r/s16.67 Mbps133.4 Mbps1.6 Gbps

100 ms

tion recorders. To overcome this problem,the RCA Laboratories has been developingindividually addressable, monolithic diodelaser arrays and has demonstrated veryencouraging performance from researchsamples of early design approaches.'

Early in 1986, a three -element arraywill be installed in the AODR to achievethree -channel write/read/erase operationwith magneto -optic media. Since the fea-ture sizes by which the optical recordingsare made are linearly related to the wave-length of the write source, the larger wave-length of the laser diodes (830 nm) ascompared to the argon laser (488 nm)implies a disk capacity smaller by approx-imately the wavelength ratio squared, afactor of four. In addition, diode laserpower limitations (30 mW/diode CW),and the increased disk rotation rate requiredto achieve a given data rate per channeldue to the increased minimum feature

size, indicate that a maximum user datarate of 60-70 Mbps will be possible withthe three -channel system, as compared tothe current capability of 100 Mbps.

Optical Disk Buffer'The Optical Disk Buffer, shown concep-tually in Fig. 6, will meet the requirementsof very large on-line data capacity (greaterthan 1 terabit) and very high input/outputdata rates (greater that 1.6 Gbps) withrapid access (less than 100 ms) to thestored data. Twelve double -sided 14 -incherasable magneto -optic disks are fixed toa common shaft in this system. Each disksurface has a data capacity of about 41gigabits and is served by a dedicatedelectro-optic module that incorporates anine -element diode laser array for record,playback and erasure of data at rates upto 133 Mbps. The projected performance

of the twelve -disk drive is given in TableII. The relatively modest disk rotation rate(15.4 rps), which does not vary with therecording radius, and a moderate level ofaverage drive power per laser diode (<30mW-CW) both promise a favorable marginin system power and component life.

The projected linear data packing densityon each disk surface is of the same orderas that achievable with magnetic recorders.This system capacity advantage is gainedwith the Optical Disk Buffer by greatlyincreasing the number of recorded tracksper inch. Figure 7 shows the track geom-etry, in which eight data tracks and acentral permanent pilot track used for posi-tion identification and tracking are placedon a 13.3 -micron pitch.

Electro-optic moduleEach electro-optic module is a fully inde-pendent subassembly containing a nine -element laser diode array, and optical sys-tems for array focus, focus detection, datasignal detection, and pilot track readingand tracking. The data signal is recoveredin playback via differential signal detectionusing two nine -element photodetector ar-rays. Figure 8 illustrates the relative loca-tion of major subassembly components.Data amiss time is enhanced by translatingonly the low mass final focus objectiveand its two -axis positioning head. All elec-tronic circuits for laser drive, focus andtracking control, data detection, and lenstranslation control are contained withinthe electro-optic module.

Development timetable

The Optical Disk Buffer is being developedas an exploratory development/brassboardmodel with a partial complement of electro-optic modules and active disk surfaces sothat sufficient engineering performance datacan be generated to predict full systemperformance. A major milestone will occurwhen the brassboard demonstration sched-uled for early 1987 retires major technicalrisks. At this juncture, one or more proto-type variants can be fully developed. Thesewill include the high -capacity, 12 -disk sys-tem that is currently planned, a less com-plex buffer with reduced capability, or aruggedized buffer intended for a specificapplication such as the NASA Space Sta-tion. An artist's concept of the fully popu-lated 12 -disk terabit optical buffer is shownin Fig. 9. The less than one cubic metervolume will contain multiple, identical dataprocessing electronics that are well suited

50 RCA Engineer 31-1 Jan. / Feb. 1986

for LSI implementation. They will controlthe functions necessary for positioning thewrite/read heads and providing internaldata synchronization. Table III comparesthe performance projected for this bufferwith that of the well-known IBM 3380magnetic disk system. As can be seenfrom this comparison, the emergent opticaldisk approach begins with a 25:1 advantagein capacity and over a 60:1 advantage indata rate compared to a relatively newcommercial offering of the mature magneticdisk drive technology.

Data access time must include both fileaccess time and data transfer time. Becausethe Optical Disk Buffer is configured toprovide a very high data rate from acontinuous spiral track, a data access timeadvantage is gained whenever data blocksgreater than 1 megabyte are to be buffered.Figure 10 charts total data block accesstime against file size for the projected 14 -inch magnetic disk drives of the future,and for the Optical Disk Buffer underdevelopment. Magnetic disk drives areavailable today with transfer rates of 3Mbps, with projected growth to 10 Mbps.5Therefore, the total arrPs time compari-sons for the 1990 timeframe graphed inFig. 10 apply for magnetic drives at 6 and12 Mbps (to widely bracket the potentialtransfer rates), with initial data access in33.3 ms (25 ms to track, plus a half-

revolution latency of 8.3 ms). The OpticalDisk Buffer total access time is graphed atthe projected 200 Mbps (1.6 Gbps) transferrate with 100 ms initial access time.

High -data -rate optical taperecorder

Development of a high -data -rate, high -capacity tape recorder with the specifica-tions and performance goals shown inTable IV was initiated during 1985 forapplications that do not require rapid, ran-dom access to the stored data. The ap-proach is to combine the high areal bitpacking density capability of optical taperecording techniques with the high volu-metric bit packing density provided bythe tape format in a recorder like thatshown conceptually in Fig. 11. The basicrecorder building block is a 100-Mbpselectro-optic module that includes an eight-element diode laser array and an acousto-optic beam deflector. The developed re-corder will, therefore, be applicable todata rates ranging from 100 Mbps to 1.6Gbps in 100-Mbps increments.

One of the prime objectives of the re-corder concept is to handle high data

LASER DIODES IMAGED ARRAYON DISK SURFACE DATA BAND

SPOT GEOMETRY AND TRACK SPACING

GEOMETRY 9 ELEMENT ARRAY: 8 DATA 1 TRACKER 1.4 TRACK PITCH 2.1 GUARD BAND BETWEEN DATA BANDS 0.7 ..m SPOT DIAMETER

TRACKING SPIRAL PATTERN CLOSED -LOOP RECORDING AND PLAYBACK PREFORMATTED PILOT TRACK PILOT TRACK CONTAINS TRACK

NUMBER IDENTIFICATION DATAAT SEPARABLE LOW DATA RATE

1.4 ,.m

GUARDBAND

13.3 ..m

PERMANENTPILOT TRACK

ARRAYDATA BAND/1\\

2.1 m

Fig. 7. Buffer track geometry.

DIFFERENTIALAMPLIFIERS

FOCUS ANDTRACKINGACTUATOR/

DATA ANDTRACKINGDETECTORS

BEAMEXPANDERPRISMS

COLLECTIONLENS

LASER ARRAY

LASER DRIVERS

FOCUS LENS

FOCUSDETECTORS

LINEARMOTOR

Fig. 8. E -O module subassembly components.

rates at a moderate tape speed. This isaccomplished by demultiplexing the inputdata to as many as 16 electro-optic mod-ules. The data is further demultiplexed toeight channels within each module to ob-tain up to 128 channels for a 16 -modulesystem. A tape speed of approximately325 inches per second is required for theprojected along -track data packing densityif simple longitudinal recording is used toaccommodate a 100-Mbps output from

each module. Therefore, the output ofeach diode within the eight -element arrayis passed through an acousto-optic beamdeflector to produce the needed tape scanvelocity with the tape advanced at a maxi-mum projected rate under 14 inches persecond to position the tape from scan toscan.

Close contact is being maintained withpotential tape suppliers to help assure thatthe recorder will be compatible with pro-

W.P.Altman/G.M. Claffie/M.L. Levene: Optical storage for high performance applications 51

Fig. 9. Fully populated optical disk buffer.

Table Ill. Comparison of projected optical disk buffer performance withcommercial magnetic disk system

User data density

IBM 3380 (standard)IBM 3380 (double capacity)Optical disk buffer

6.7X108 bits/surface1.34X109 bits/surface4X101° bits/surface

System performance comparisons

IBM 3380 Optical diskbuffer

Optical diskbuffer

advantage

30 surfaces2.5 Gbps=20X109 bits

(standard)5 Gbps=40X109 bits

(double capacity)3 Mbps/sec=24X106 bits/sec379,808 bits/rev/track

24 surfaces1000X109 bits

1000X109

1600X106 bits/sec1,081,344 user bits/rev/diode

50/1

25/1

67/13/1

duction media. Two critical parametersare tape thickness and dimensional stability.A tape base thickness of about 1 mil isrequired to meet the volumetric storagecapacity goal. The tape must be dimension-ally stable at this thickness to assure thatdata is recovered at an acceptable errorrate after many wind/rewind cycles. Themedia development effort has concentratedon write -once media, but some considera-tion has been given to erasable media.

The optical tape is wrapped around a16 -inch diameter capstan supported by ahydrostatic air bearing to produce a verysmooth, stable recording surface. Sincethere is a large tape -to -capstan surfacecontact area, virtually no slippage occurs.This minimizes tape mistracking as seenby the optical recording heads so thatsmall guard bands may be used as animportant step toward increasing the re-corded data packing density. Since thecapstan is very large in diameter and thetape speed is moderate, the angular velocityof the capstan is only 16.5 rpm. Thecapstan will be belt driven to permit ahigher, more stable motor speed and todecouple motor speed variations from thecapstan.

Dust and airborne particles are detrimen-tal to successful recording and playback.Particles on the front side of the tapeobscure the media from the laser beamsince the media cannot have a thick over-coat to act as a dust defocus layer whilemaintaining an overall thickness of about1 mil. Also, larger particles on the capstansurface will "print through" the thin mediato the recording surface and cause a focuserror. To eliminate these problems, theentire tape transport region will be sealedand continuously purged with filtered air.

The recording head for each module iscomposed of an objective lens, focus mech-anism, and tracking mechanism. This assem-bly, which is about 1.5 inches in diameter,must be positioned very close to the tapedue to the short working distance of theobjective lens. Therefore, the optical mod-ules fan out radially from the capstan, asshown in Fig. 11, with each module servic-ing a longitudinal swath of the tape about16 mils wide. The lateral displacement ofthe adjacent modules and the use ofacousto-optic beam deflectors with eachelectro-optic module results in the tapetrack data pattern shown in Fig. 12.

The output from a separate laser locatedon each electro-optic module is passedthrough the same objective lens as the

52RCA Engineer 31-1 Jan. / Feb. 1986

200

TIMEIMS)

100

33 3

0

6 MB/s 12 MB/s

FUTUREMAGNETIC

f--.".111111111, DRIVESS

OPTICALDISK BUFFER200 MB/s

I

FILE SIZES (MBytes)

Fig. 10. Data access and transfer time

eight data channel beams to write a longi-tudinal control track. This is done to assurethat the position of the control track withrespect to the data tracks will be main-tained during record and playback. Duringplayback, the control track provides trackposition information to the tracking servoso that the data tracks can be properlyscanned. Tracking is accomplished by mov-ing the objective lens within the two -axis(track and focus) mounting assembly. Thecontrol track also provides timing informa-tion to the acousto-optic beam deflectorin playback to keep the deflector scanproperly phased to the recorded tracks.

The high -data -rate optical tape recorderbrassboard will be developed over a two-year period, followed by the two-year de-velopment of an engineering prototype.The brassboard will include a single electro-optic module to demonstrate system feasi-bility using several hundred feet of tapemedia provided by one or more suppliers.The prototype will include multiple electro-optic modules to determine guard bandrequirements and the level of interactionbetween module swaths. Under the currentschedule, successful demonstration of theprototype can be achieved in the 1989timeframe, with production units availablefor Space Station ground support and otherapplications in the early 1990s.

DATA PROCESSINGELECTRONICS

ELECTRO-OPTICRECORDING MODULES (16)

CAPSTANTAPE GUIDE

CLEAN AIRCHAMBER

TAPETAKE-UP REEL

TAPESUPPLYREEL

CAPSTAN DRIVESPINDLE AND BELT

SERVO ELECTRONICSPOWER SUPPLIESAIR SUPPLY

Fig. 11. Artist's rendition of optical recorder transport.

Table IV. Optical tape recorder specifications

User data rateData capacityPacking densityEO module data rateNumber of EO modulesTape speedTape widthTape lengthTape thicknessReel diameter

and performance goals

1.6 Gbps2/1013 bits4.75X108 bits/in2100 Mbps/sec16

13.8 inch/sec1/2 in7,000 feet1 mil11.5 in

ConclusionsBy building on the developments of thelast ten years, RCA is achieving very highperformance optical storage systems thatwill capture, store and disseminate thevast amounts of data that will be generatedby advanced sensors and computing sys-tems in the late 1980s and beyond. Theprojected need for even higher areal -storagecapacity using shorter wavelength solid-state sources and multiple layer recordings,and faster access times, is also being ad-dressed to assure that RCA will continueto be the principal developer of advancedoptical storage technology in the followingdecades.

AcknowledgmentThe work presented in this paper has beensponsored for several years by the RomeAir Development Command, Griffiss AirForce Base, Rome, New York; NASAMarshall Space Flight Center, Huntsville,Alabama; and other Government organi-zations. Key Government contributors tothe development of the optical recordingtechnology have included A. Jamberdinoand J. Petruzelli of RADC, and K. Wallgrenand D. Thomas of NASA.

The optical recording technology devel-opments represent the dedicated efforts ofmany talented RCA personnel from theAdvanced Technology Laboratories, the

W.P. Altman /G.M. Claffie/M.L. Levene: Optical storage for high performance applications 53

NOMEN116

ROWS

AXIS OF DIODE LASER ARRAY

RECORDEDBY8 DIODELASERARRAY

TAPE MOTION

DATA TRACKS SCANNED BYACOUSTO-OPTIC DEFLECTION

I

1//' TAPE

Fig. 12. Tape track data pattern.

Communication and Information SystemsDivision, and RCA Laboratories.

References

I. G.J. Ammon and J.A. Calabria, "Operational Perfor-mance of Optical Disk System," Third International

2.

3.

Conference on Optical Mass Storage, SPIE Vol.529, Los Angeles, Cal., January 22-24, 1985.

G.M. Claffie, "High Performance Optical Disk Juke-box," ibid.

D.B. Carlin et al., "Multichannel Diode Laser ArrayOptical Recording," Proceedings; OSA Topical Meet-ing on Optical Data Storage, Monterey, Cal., April1984.

4. M.L. Levene, "A High Data Rate, High CapacityOptical Disk Buffer," Seventh IEEE Symposium onMass Storage Systems, Tuscon, Ariz., November 4-7, 1985.

5. C. Panasuk, "Technology Report, Advanced Com-puter Technology: Mass Storage." Electronic Design,May 3, 1984, pp. 263 and 266.

54RCA Engineer 31-1 Jan./ Feb. 1986

Authors, left to right: Claffie, Altman, Levene.

Wolf Altman is a Manager of MarketingDevelopment at ATL. He is responsible formarketing planning and follow through inthe area of optical data storage systems.Prior to joining ATL in 1984, he was aPrincipal Member of the Technical Staff atAstro-Electronics Division. He worked onlaser remote sensing systems and solid-state and CO2 laser technology. He has aBS in Physics from Drexel University andan MSEE from the University ofPennsylvania. He has completed graduatework toward a PhD at the University ofMaryland.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6423

Gerald Claffie is the Manager of ATL'sOptical Storage Laboratory, where he isresponsible for the development of opticaldisk technology. Prior to this assignment,he held marketing, engineeringmanagement, and engineering designpositions that addressed the conceptdesign and/or advanced development ofelectro-optical and electro-mechanicalsystems for data collection, data

processing, and mass data storageapplications, He has a BSEE fromClarkson University and an MSEE from theUniversity of Pennsylvania.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6484

Martin Levene is a Program Manager inATL's Optical Storage Laboratory. He iscurrently responsible for the Optical DiskBuffer and Optical Tape Recordercontracts. Previously, he was responsiblefor programs in the areas of advancedoptical disk recording, computer -aidedmechanical analysis, and thermalmanagement. He received BSME andMSME degrees from the University ofPennsylvania, where he has alsocompleted the course work toward thePhD in Mechanical Engineering. He is therecipient of a David Sarnoff Award forOutstanding Technical Achievement.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6489

W.P. Altman/G.M. Claffie/M.L. Levene: Optical storage for high performance applications 55

D.E. Britton

Verlangen: Formally verifying system designs

This set of tools can be used to prove that designs of computersystems meet their requirements.

Do we really need to invest our effort informally verifying system designs? In part,the answer relates to how important it isfor a system to function correctly. Forcritical systems, verified design can increaseour confidence that a system will meet itsrequirements. Another benefit of verifieddesign relates to the often enormous costof system development. Verifying a system

Abstract: "Verlangen" is a Germanverb that means "to require." It is also,appropriately, the name of a set of toolsfor formally specifying system designs andverifying that they meet requirements

Specification language-provideshigh-level language features forspecifying system designs andrequirements.

Compiler-translates a specificationinto definitions and theorems in first -order logic.

Theorem prover-proves theorems toverify that a design satisfiesrequirements.

Verlangen is appropriate for many kindsof computer systems, including distributedsystems, communications networks, andoperating systems. Eventually, a translatorwill be added for implementing verifieddesigns in software. Verlangen is beingdeveloped by the Software EngineeringLaboratory of RCA AdvancedTechnology Laboratories.

©1986 RCA Corporation.Final manuscript received November 20. 1985Reprint RE -31-1-8

design can catch design flaws early in theproduct life cycle, while the cost of correct-ing them is relatively low.

For RCA Aerospace and Defense andother defense contractors there is anothermotivation, too. In August 1983, verifieddesign was thrust into a position of specialimportance when the Department of De-fense published its "Trusted ComputerSystem Evaluation Criteria",' a documentthat defines criteria for evaluating howmuch trust to give to secure computersystems. Depending on security policiesand assurances, a secure computer systemcan be rated as low as "D," minimalprotection, to as high as "A1," verifieddesign. The Department of Defense is cur-rently using these criteria to rate existingsystems, such as the Honeywell SCOMP,2and to provide rating requirements forsystems yet to be implemented.

We have developed Verlangen for pro-ducing verified designs as required in theA 1 category, but have not restricted Ver-langen to verifying security requirements.Although several other languages and sys-tems can specify and verify system designs,Verlangen has special strengths not foundelsewhere.3'4'5'6'7

Verlangen encourages separating systemdesigns and their verifications into tractableunits. To do this, the language provides"classes" to support object -oriented design,and "levels" to support levels of refinemert.These language features make Verlangenspecifications readable and keep verificationmanageable. When a change in systemdesign or requirements necessitates a changein a Verlangen specification, most theorems

and proofs will remain unchanged, requir-ing relatively little added effort to verifythe changed specification.

Verlangen is perhaps unique in its appli-cability to truly concurrent systems, suchas distributed systems and networks. Themodel for communications between subsys-tems is extremely flexible, allowing a greatvariety of synchronization schemes to bespecified. This contrasts Verlangen withthe Gypsy Verification System.' AlthoughGypsy is commonly chosen for verifyingnetwork and distributed applications, it

imposes a very restrictive message -basedcommunications model.

The desire to verify designs of securecommunication networks and distributedsystems has played an important role inthe development of Verlangen. We haveused Verlangen to specify and verify thedesign of a communications network withend -to -end encryption (Fig. 1). All mes-sages that travel over the network areencrypted to prevent their being tapped,and only hosts that are authorized to com-municate exchange unencrypted messages.This application is a simplification of anexample described in another paper.'

In another application (Fig. 2), a multi-level secure local area network (SecureLAN) connects several workstations thatdo not deal with or understand securitylevels. Each workstation is assigned a fixedsecurity level and operates only at thatlevel. Between the workstations and thelocal area network are guards, one foreach workstation. To enforce multilevelsecurity, the guards restrict the flow ofmess Ages between workstations. Examples

56 RCA Engineer 31-1 Jan. / Feb. 1986

in this paper use the Verlangen specificationfor this application.

Although Verlangen is not a program-ming language, it includes many program-ming language features, such as block struc-ture, identifier scope and visibility rules,and user -defined data types. These featuresare equally valuable for expressing programand design specifications.

ClassesVerlangen uses a language construct calledCLASS to support object -oriented designand verification. Its concept of class com-bines the concept of abstract data typefrom programming languages with the con-cept of state machine from specificationlanguages. An abstract data type defines aset of values and provides functions (oroperations) that yield new values in theset from old ones. A state machine goesthrough states or cycles to do its job. Forexample, a washing machine cycles throughfill, wash, spin and rinse. A Verlangenclass is an abstract data type whose valuesrepresent the states of a state machine.

Since most system entities can be mod-eled as state machines, the class is a veryuseful and general construct. We use classesto represent data structures, processes, hosts,front -ends, communication links, commu-nication networks, etc. We define a newclass whenever we want to represent anew kind of system entity. If a systemincludes several similar entities that operatemore or less independently-for example,the guards in the Secure LAN example-we define a class for that kind of entityand specify that there are several instancesof that kind of entity in the system. Aclass instance appears in a Verlangen speci-fication as a variable whose data type isgiven by the name of the class.

Each class instance represents a partic-ular state machine and is called an object.Associated with an object is a sequence ofvalues (states), called a history. The firstvalue in the history represents the statemachines's initial state, and the other valuesrepresent each subsequent state. To definethe possible histories, a class definitionspecifies initial values for its objects (or acondition on initial values) and some oper-ations that yield new values from oldones.

How do we use the Verlangen classconstruct? Consider the guard unit fromthe secure LAN. Each guard, which isassigned the security level of its work-station, has two functions. The guard usesits security level to label all data that goes

- ALL MESSAGES ROUTED OVER NETWORK ARE ENCRYPTED- TWO HOSTS COMMUNICATE ONLY IF AUTHORIZED TO DO SO

Fig. 1. A network with end -to -end encryption. Only encrupted messages traversethe network. Two hosts communicate only if they are authorized to do so.

WORKSTATION(SECRET)

(GU RC)

WORKSTATION(CONFIDENTIAL)

WORKSTATION(TO?' SECRET)

Cd ARD

Fig. 2. A secure local -area network. Information does not flow from a workstationwith a low classification to one with a higher level.

from its workstation to the network. Theguard also prevents data with a highersecurity level from reaching the work-station.

We model each guard as a state machineand define a Verlangen class called Guard(Fig. 3) that specifies a class of statemachines-all the guard units. The guardsare not identical, since their security levelsmay be different. So the Guard class defi-nition has a parameter: a constant max oftype Lev. Each VAR declaration for avariable of type Guard will assign a valueto max.

Each Guard value represents a state.The variables, declared by VAR, representthe components of the state. These compo-nents have types Lev, Subj, and Obj repre-senting, respectively, security levels, namesof individual workstations, and classifieddata objects.

The procedures in the Guard class defi-nition represent operations that take theguard from one state to the next. Verlangenprocedures include a precondition and aneffect. The precondition and the effect areboth expressed as one or more logicalformulas. The precondition selects those

D.E. Britton: Verlangen: Formally verifying system designs 57

CLASSVARVARVAR

Guard(CONST max:Lev) ISnetin,netout:Obj;dest:Subj;netinfull,netoutfull:BOOLEAN

INITIALLY FALSE;

PROCEDURE fromnet(o:Obj; 1:Lev) ISPRECONDITION NOT netinfull;EFFECT

IF 1 <= maxTHEN (netinfull' & netin' o)

ELSE NOT netinfull';SAME netoutfull, netout, dent;

END fromnet;

PROCEDURE touser(o:Obj) IS ...PROCEDURE fromuser(d:Subj; o:Obj) IS ...PROCEDURE tonet(d:Subj; o:Obj; 1:Lev) IS..

INVARIANT netinok ISnetinfull

EXISTS g:Guard EXISTS 1:Lev( g (< THIS &g.fromnet(netin,l) &1 <= max );

INVARIANT filter USING netinok ISFORALL o:Obj( touser(o) =>

EXISTS g:Guard EXISTS 1:Lev( g << THIS &g.fromnet(o,l) &1 <= max )

) ;

END Guard;

Fig. 3. Guard class declaration from the Secure LAN specification.

states in which the operation may occur;that is, the operation may occur in a stateonly if the precondition is met. The effectspecifies the state after the operation interms of the state before the operation.Primed identifiers, (e.g., netin') refer tovalues after the operation; unprimed identi-fiers refer to values before the operation.

To express requirements on a class, weinclude assertions in the class definition.There are two kinds of assertions: invariantsand constraints. An invariant is a conditionthat we want every state of every object inthe class to satisfy. A constraint is a condi-tion that we want to hold between everytwo subsequent states in every objecthistory.

The Guard class defines two invariants,filter and netinok. The filter invariant statesthat the guard passes data to its workstationonly if the data came over the networkfrom a workstation with the same or a

lower security level. We may regard thefilter invariant as a requirement placed onthe class, a property that will be maintainedregardless of the class implementation. Itrefers only to the procedures and constantparameters of the class, not to the internalvariables.

For every assertion that appears in aclass definition, the Verlangen compilerproduces verification theorems. Provingthe verification theorems verifies that thedesign does indeed satisfy the assertions.For example, we verify an invariant byinduction. So for an invariant the compilerproduces theorems that correspond to thebasis and induction steps of an inductiveproof:

Basis The initial state satisfies the invariant

Induction. If an arbitrary state satisfies theinvariant, then the next state does also.

Often an invariant is not inductive-notstrong enough for the inductive proof tosucceed. Then, to obtain a verification,we determine additional supporting invari-ants and include them in the specification.When these invariants appear in a USINGclause of a non -inductive invariant, thecompiler adds them as hypotheses to thatinvariant's verification theorems. For exam-ple, netinok supports filter, which is notinductive.

ConcurrencyVerlangen allows us to decompose a systeminto (or compose a system from) simplersubsystems. This approach to system designis generally arrepted as effective for operat-ing systems. For distributed systems andcommunications networks, the approachis also a natural one. The system naturallydecomposes into a set of concurrent, inter-acting subsystems-the host computers,front-end processors, gateways, etc.

We model a system composed of subsys-tems by a collection of state machines,and define a class for each different kindof state machine. In the class definitionfor the overall system, we declare variablesthat represent the component subsystems.The data types of these variables are theclasses for the corresponding state ma-chines. This specifies that the state of theoverall system is composed of the sub-system states.

For example, the Secure LAN specifica-tion defines three classes: WorkStation,Guairl and System (Fig. 4). The classSystem represents the overall system, com-posed of several workstations and guards.In the definition for System, the work-stations and guards appear as variables oftype WorkStation and Guard, respectively.

Verlangen uses SYNC statements tospecify how concurrent subsystems are tobe synchronized. These statements corre-late events (operations) that occur in thesubsystems. A SYNC statement says thatcertain events in the subsystems cannotoccur unless they occur together.

The System class definition in our exam-ple includes SYNC statements that statehow the workstations interact with theguards, and how the guards interact witheach other. For example, a user workstationsends data only if its guard receives it, andvice versa.

When a specification consists of severalclasses, the verification of each class iscarried out independently. Supporting in-variants may come from outside of a class,however.

58 RCA Engineer 31-1 Jan. / Feb. 1986

For example, in the Secure LAN specifi-cation we included an invariant calledOrigination in the System class definition.This invariant asserts that any data objecta user workstation knows was created bya user workstation on the network. Thisrules out, for example, a design where theguards spontaneously create data objectsof their own. The Origination invariant issupported by invariants of the WorkStationand Guard classes.

Levels of refinement

Verlangen uses successive levels of refine-ment to support design. That means wecan write a Verlangen specification as oneor more ordered levels (Fig. 5), each acomplete specification of the whole system.The first (or "top") level presents the mostabstract view of the system. Each successivelevel presents a more concrete specificationthan the preceding one, and includes amap that specifies how it relates to itspredecessor. To verify a specification thatconsists of more than one level we showthat the individual levels are self -consistentand that neighboring levels are consistentwith each other.

Usually, we organize a two -level specifi-cation so the top level represents a set ofrequirements placed on the system andthe bottom level represents the systemdesign. This approach ideally allows us touse a set of requirements-for example, amodel of multilevel security-over andover again with different system designs.

The Secure LAN example is a two-level Verlangen specification. The top levelspecifies a model of multilevel security,and the bottom level specifies the designof the secure local -area network. The Ver-langen fragments in Figs. 3 and 4 camefrom the bottom level.

Verification

The Verlangen compiler translates a Ver-langen specification into a collection ofdefinitions and theorems in typed first -order logic. The theorems state that classessatisfy their assertions, and neighboringlevels are consistent. By proving the theo-rems from the definitions, we verify thatthe specified system design satisfies thespecified system requirements. Figure 6shows theorems the Verlangen compilerproduced to verify the filter invariant ofthe Guard class.

The translation of a class definitiondeclares a type that has the same name asthe class. The type's values represent the

states of the state machines that the classrepresents. The translation also defines arelation precedes and a function next.Precedes defines a partial ordering onvalues of the type, and next is a successorfunction that satisfies precedes(x,next(x)).When we give next a state (in the historyof a state machine), next yields the nextstate in the history.

A variable declared within a class defini-

tion translates into a state function. Givena state, the function returns the value ofthe variable for that state. A constant alsotranslates into a state function. An invarianttranslates into a state predicate. Given astate, the predicate determines whetherthe state satisfies the invariant. Initial con-ditions, constraints, and procedures alltranslate into state predicates. A SYNCstatement translates into an axiom stating

CLASS WorkStation(CONST myself:Subj) IS ...

CLASS Guard(CONST max:Lev) IS ...

CLASS System ISCONST Clearance(s:Subj):Lev;VAR user(s:Subj):WorkStation(s);VAR guard(s:Subj):Guard(Clearance(s));

FORALL s,d:Subj FORALL o:ObjSYNC user(s).send(d,o),

guard(s).fromuser(d,o);

INVARIANT OriginationUSING WorkStation.knowledge,

Guard.f ilter,Guard. transport

IS FORALL s:Subj FORALL o:Obj( user(s).knows(o)

EXISTS sys :LANSystem( sys << THIS &sys.user(Originator(o)).write(o)

);

END System;

Fig. 4. Excerpt from the Secure LAN specification defines concurrent classes.

TOPLEVEL

BOTTOMLEVEL

REQUIREMENTS

1

DESIGN(LEAST DETAILED)

f

DESIGN(MOST DETAILED)

LEVEL mis IS

CLASS System IS

INVARIANT SimpleSecurityConditionINVARIANT StarPropertyCONSTRAINT NoDowngrading

END System:END mis:

LEVEL Ian REFINES mis IS

CLASS WorkStation .

CLASS Guard ...CLASS System ..

END Ian:

Fig. 5. Levels of refinement.

D.E. Britton: Verlangen: Formally verifying system designs 59

PROVE

PROVE

FORALL this:Guard FORALL max:Lev( 1n1t1a1(this,max) &FORALL old:Guard netinok(old)

filter(this) )

FORALL this:Guard FORALL o:Obj FORALL 1:Lev( filter(thls) &FORALL old:Guard netinok(old) &fromnet(th1s,o,l)

filter(NEXT(th1s)) )

PROVE FORALL this:Guard FORALL o:Obj( filter(this) &FORALL old:Guard netinok(old) &touser(thia,o)

filter(NEXT(this)) )

PROVE FORALL this:Guard FORALL d:Subj FORALL o:Obj( filter(this) &FORALL old:Guard netinok(old) &fromuser(th1s,d,o)

filter(NEXT(this)) )

PROVE FORALL this:Guard FORALL d:Subj FORALL o:Obj FORALL( filter(this) &FORALL old:Guard netinok(old) &tonet(this,d,o,l)

filter(NEXT(this)) )

1: Lev

Fig. 6. Theorems for verifying filterspecification.

the equivalence of the state predicates thatrepresent the synchronized procedures.

Mappings between levels are generallyrepresented by axioms that relate theentities of one level to another.

Formal verification at ATL

To meet the verification needs of RCAAerospace and Defense, RCA AdvancedTechnology Laboratories supports a formal

invariant, taken from the Secure LAN

verification skill center in its SoftwareEngineering Laboratory (SEL). Verificationsystems available to the skill center includethe Gypsy Verification System' (from theUniversity of Texas) and Verlangen.

Verlangen development is an ongoingeffort of the skill center. The Verlangencompiler has been implemented in thePascal programming language and runson a Digital Equipment Corporation VAXunder the VMS operating system. The

Dianne Britton is a Senior Member of theEngineering Staff in ATL's SoftwareEngineering Laboratory. She is working inthe area of formal software and systemverification, with emphasis on design andmultilevel security verification. Shedeveloped Verlangen for specifying andverifying designs of systems andnetworks. At RCA Laboratories, shedesigned and built a protoytpe operatingsystem kernel for distributed applications,and developed algorithms for maintainingconsistent, fully -replicated databases in adistributed system. Dianne received anMS and PhD in Computer Science fromthe University of Arizona.Contact her at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6654

Verlangen theorem prover comes fromthe commercially -available Verus verifica-tion system,9 and runs in the same environ-ment as the compiler. We are presentlyadding features to the specification languagethat improve its expressive power andextend the range of properties that can beverified.

Eventually, a translator will be addedto the Verlangen toolset that will producea separate translation from a Verlangenspecification into the Department of De-fense's Ada programming language code.This code will be a "skeleton" of a softwareimplementation of the specified system. Askeleton is an incomplete implementation;it substitutes assertions (imbedded in formalcomments, as in Anna') for omitted code.To obtain a complete implementation thatmeets the system requirements, a program-mer adds Ada code that satisfies theimbedded assertions.

ReferencesI. Department of Defense Computer Security Center,

DoD Trusted Computer System Evaluation Criteria,CSC -STD -00I-83, August 1983.

2. Fraim, "SCOMP: A Solution to the MultilevelSecurity Problem," Computer, Vol. 16, No. 7, July1983.

3. D.I. Good, R.M. Cohen, C.H. Hoch, L.W. Hunter,and D.F.Hare, "Report on the Language GypsyVersion 2.0," ICSCA-CMP-10, The University ofTexas at Austin, Revised September 1978.

4. K.N. Levitt, L. Robinson, and B.A.Silverberg, The

HDM Handbook, Vols 1-3, Computer Science Lab.,SRI International, Menlo Park, California, June 1979.

5. R. Kemmerer, "FDM-A Specification and Verifi-cation Methodology," Proceedings of the Third Seminar

on the DoD Computer Security Initiative Program,National Bureau of Standards, Gaithersburg, Mary-land, November 1980.

6. R.R. Musser, "Abstract Data Type Specification inthe AFFIRM System," IEEE Trans. on SoftwareEngineering, SE -6,I January 1980.

7. D. Craigen, "Ottawa Euclid and EVES: A StatusReport," Proceedings of the 1984 Symposium onSecurity and Privacy, Oakland, California, May 1984.

8. D.E. Britton, "Formal Verification of a SecureNetwork with End -to -End Encryption," Proceedingsof the 1984 Symposium on Security and Privacy,Oakland, California. May 1984.

9. Verus User Documents, Compion Corporation, asubsidiary of Gould Inc., 1984.

10. D.C. Luckham, F.W. von Henke, B. Krieg -Brueck-ner, 0. Owe, "ANNA: A Language for AnnotatingAda Programs," Preliminary Reference Manual, TR84-261, Computer Systems Laboratory, StanfordUniversity, July 1984.

60 RCA Engineer 31-1 Jan. / Feb. 1986

G.W. Mebus L.T. Armstrong H.Rosenthal

Ada® software development tools

Ada, the DoD's programming language of the future, solvesmany software development problems, but also creates someproblems of its own. The ATL Software Engineering Laboratoryis developing some tools to handle them.

The Ada language is a high -order com-puter language (HOL) of many firsts.It is the first major language namedafter a woman-the first program-mer, Augusta Ada Byron (1815-1851),Countess of Lovelace, and LordByron's daughter. It is also the first lan-guage with a name that the U.S. Depart-ment of Defense (DoD) has trade-marked, the first language for whichDoD tests must be used to validate com-pilers, and the first that the DoD hasmandated for use in all major imple-mentations.

As far as the DoD is concerned, theAda language is definitely the softwaresystems language of the future. Indeed,it is quickly becoming the language of

Abstract: The Department ofDefense's Ada programming languageeasily manages the complexities of largemilitary software development. But itsown complexity prevents people fromunderstanding or maintaining Adacode. To solve these problems, theAdvanced Technology Laboratories(ATL) is developing a set of softwaredevelopment tools for the Adalanguage. They consist of a frontendprocessor that analyzes Ada sourcecode for handling by a cadre ofspecialized backend processors as wellas a debugger/tracer. The tools arehighly portable and easily targeted todifferent computer architectures.

® Ada is a registered trademark of the U.S. Depart-ment of Defense, Ada Joint Program Office.

©1986 RCA Corporation.Final Manuscript received November 20, 1985Reprint RE -31-1-9

today as more sophisticated Ada com-pilers are now beginning to appear.

Ada language

The DoD mandated the Ada languagefor their programs to reduce many ofthe development and maintenance costsas well as other problems of large mili-tary software development. (Character-istics of the Ada language, its associatedtechnology, and its place among otherprogramming languages were discussedpreviously in the RCA Engineer. "a)

The Ada language is primarilydesigned to support real-time, parallelprocessing and hardware -intimate,large, complex software development.Several principles for handling the com-plexity of software are the concepts ofprogram structuring, data abstraction,information hiding, reusability of exist-ing proven code, and strong typing. TheAda language supports these concepts,allows separate compilation of pieces ofa large program, and provides for paral-lel processing of special software pieces(tasks).

Program structuring allows us toavoid describing "jumps" or "go tos"in the program logic. Instead, state-ments like

if < condition > then < actionl >else < action2 >

andwhile < condition > do < action >

allow us to better understand and con-vey the intent of our programs to otherpeople and to the computers. The Adalanguage fully supports the normal setof program structures.

With data abstraction we can empha-

size the important details without beingconcerned with the unimportant ones,while information hiding prevents usersof the software from knowing programdetails that they should not be able toaccess.

The Ada language supports thesecapabilities in the Ada package concept:having a specification that tells users(people or programs) what informationand processing is available, and a sepa-rate "body" that tells how data and pro-cessing are actually implemented.

Strong typing is the ability to specifyyour own data types (such as "com-plex" for complex numbers, or "week-day" for a list of day names from Mon-day through Friday) and the operationsallowed to process data of those types.The Ada compiler ensures proper use ofthe data and operations, based on thedefined data types. The package con-cept allows this checking, even whenprogram pieces are compiled separatelyand when body parts of packages havenot yet been written.

All these beneficial features of theAda language are there to support pro-gram reliability. But, like all solutions toproblems, they create some problems oftheir own.

For large programming systems, theAda language supports developing thevarious pieces separately; so, one persondoes not need to know all names used inthe overall program. In some instances,multiple use of the same name isallowed, a feature called overloading ofnames. The names may be "qualified"by the program pieces in which theyoccur, or by the type of data thatinvolves them. Although the compiler

RCA Engineer 31-1 Jan. / Feb. 1986 61

keeps straight the various meanings of aname; people who must maintain theprogram source code can become con-fused.

Abstraction and hiding can also con-fuse things for code maintainers. Forexample, a record structure's definitioncould be distributed over several code -compilation units (some parts may behidden while others are not).

Another problem exists with the cur-rent compilers themselves. The majoreffort in developing Ada compilers hasbeen to conform to the Ada Program-ming Language' standard, not with pro-viding extra features to help program-mers. One glaring deficiency is thatmost Ada compilers do not provide evensimple cross-reference listings to tellwhere a name is declared or used in aprogram, so debugging Ada software isoften a difficult job.

To attack these problems, the Soft-ware Engineering Laboratory (SEL) inthe Advanced Technology Laboratories(ATL) is developing new Ada softwaretools. They include a frontend for thecompiler, backend tools, and a machine -independent Ada language -level debug-ger/tracer. The SEL had been using theTeleSoft Ada compiler, and has installedits second generation Ada compiler,namely Digital Equipment Corpora-tion's VAX®/VMS Ada package.

Compiler frontendThe SEL is currently developing a com-piler frontend for the Ada/M language,which is a large subset of the Ada lan-guage. The Ada/M language excludesgenerics, tasking, fixed-point numbers,and separate compilation of programpieces. In the future, the computerfrontend will be upgraded to the fullAda language.

A compiler frontend is a softwaretool that reads source code written in ahigh-level language (for example, theAda language) and produces anintermediate -language representationof the code that is more easily processedby subsequent software tools. Wedesigned the frontend so it can be usednot only as a frontend for a compiler,but also as a frontend for various back -end tools that need or use informationabout the input Ada source program.

Most code for the frontend is written

® VAX is a trademark of the Digital EquipmentCorporation.

in a special, limited language called PAL(Parser Assembly Language), that hasless than twenty instructions. PAL isspecifically designed for implementingrecursive -descent, table driven compil-ers. The advantage of the PAL code is itadapts easily to another host computer.Because the language is so smallrwritingan assembler program to process thelanguage is almost trivial. Hence, front -ends written in PAL, such as the one forthe Ada/M language, are highly porta-ble to different computers.

The rest of the code for the frontendis currently written in Pascal, but weintend to convert it to the Ada languagein 1986 using our second -generationcompiler. This will enable us to "boot-strap" the compiler when we put thefrontend on another machine. The non -PAL code encompasses what are knownas the "resolvers" (they determine theprecise use of a name), and additionalutility routines (for example, allocationroutines and error routines).

As an example of resolving, considerthe following expression in the Ada lan-guage:

(x +y) x2

When processed, the input expressionwill contain only block pointers(addresses stored on a symbol table) forx and y. But, the Ada language permitsus to reuse identifiers. Therefore, theresolvers will determine exactly whatversions of x and y we mean and returnpointers to blocks that contain the par-ticular contexts x and y represent.

The rest of the non -PAL code is pri-marily for machine -dependent memoryallocation and error handling routines.To promote portability, we decided toallocate space via an HOL rather thanuse the VAX/VMS operating systemspace allocation routines. Also, wewrote the error routines in an HOLbecause PAL does not have any input oroutput instructions.

The frontend produces a data struc-ture graph that represents the parsedinput program and is a completelyresolved graph, both for context (namesof entities) and semantics. We initiallydesigned the data structures to permit acompiler backend to take the frontend'soutput and produce object code. Thus,the graph keeps intact all semanticinformation about the input source.

Therefore, this graph provides a goodgeneric representation for a variety ofbackend tools needed to evaluate an

Ada program. The backends currentlyunder development are:

An Ada/M source code regenerator(that will be upgraded to the full Adalanguage in the future).

A database tool with query/reportcapability. It is specifically designedto give the user semantic and contex-tual information about the input Adasource program.

An interactive Ada debugger/tracerthat does not depend on which Adacompiler is used.

Source -code regenerator and"pretty printing"The Ada/M regenerator will provide thebasis for all future compiler backends.As input, it takes the graph produced bythe Ada/M frontend and reproduces thesource program. This is valuablebecause it helps us verify that we havecaptured the semantic information ofthe input program.

Because the source code regeneratorhas all the information needed to recon-struct the original source code, it alsohas enough information to reformatand standardize the source code as wellas enforce the coding guidelines. Thereformatting is done in such a way thatindenting source code lines clearly dis-plays the structure of the code. This"pretty printing" enhances code read-ability, an important feature when peo-ple have to understand or document aprogram. The regenerator will also bethe basis for both generating target -machine code and developing thedebugger/tracer described below.

Database and query/reportcapabilitiesBecause the Ada language is primarilyintended for large-scale software sys-tems, properly managing the databecomes more difficult as the system'ssize increases. Proper modularizationrestricts as much data as possible to afew routines but, in some cases, datamust be available to a large percentageof routines.

As data must be tracked over manyroutines, we chose to incorporate anAda database into our Ada tool set.This database will be integrated into auser-friendly database management sys-tem (DBMS). When used properly, thisfacility will enable a software designer to

62 RCA Engineer 31-1 Jan. / Feb. 1986

manage large streams of informationquickly and easily. For example, if youwant to list all procedures in a packagethat reference a specific variable X, thenyou can do it with a simple commandsuch as:

Print procedures with variable XThis information may not seem veryuseful. But suppose we suspected thatan unwanted change to X was causing aproblem we were having with a hugesoftware system. Then, we would sim-ply alter our command to:

Print procedures where variable X ischanged

Moreover, this tool can be used formuch more than simple variable infor-mation. It will permit users to generateproperly formatted hardcopies (re-ports), and thus quick -reference infor-mation about their large-scale softwaresystems. This can be particularly helpfulwhen dealing with program characteris-tics that are unique to the Ada language,such as user -defined overloading andgenerics.

To implement this concept, twoapproaches were considered. The firstwas to incorporate a DBMS packagethat already exists into the interactivepart of the Ada tool set. This allows agreat degree of generality and a user-friendly environment because thesepackages are designed for an end user towork in an English language -like envi-ronment with speed and efficiency.

The second alternative was to write aset of specific database routines for theexisting backend code. This wouldallow the user to work in an environ-ment specifically tailored to his or herneeds. But, it would probably requirethe generation of huge amounts of codefor each application.

For the Ada tool set, the SEL chosethe first alternative because it satisfiedrequirements while minimizing risk. Weare currently using the DATATRIEVE4package that allows a software designerto integrate database manipulationfacilities with programs written inhigher -level programming languages.This is achieved through the use of theDATATRIEVE access block (DAB),which is a series of type, variable, andexternal procedure declarations towhich a program must have access.Once communication has been estab-lished, either the DATATRIEVE soft-ware or the program may handle theflow of control.

Authors, left to right: Mebus, Armstrong,

George Mebus is Unit Manager of theLanguages and Compilers group in ATL'sSoftware Engineering Laboratory. The work ofthis group includes creation of Adadevelopment tools, software support foradvanced pipelined processing architectures,parallel processing, and formal verificationtechniques and tools for verifying security andcorrectness of distributed communicationssystems and secure operating systems. Prior tocoming to RCA, he worked with computer andsoftware development systems for 24 years atthe Naval Air Development Center NADC.George received a BSEE degree from theUniversity of Pennsylvania, and an MSEEdegree from the University of Michigan. Hecompleted course work toward a PhD inComputer and Information Science at theUniversity of Pennsylvania.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6634

Leonard Armstrong is an Associate Memberof the Engineering Staff in ATL's SoftwareEngineering Laboratory For the Ada tool setdevelopment program, he has updated existingparser software to increase compilation speed,and he has developed both the AdalM sourcecode regenerator and a set of resolver routinesneeded for the Ada/M compiler to determine the

and Rosenthal.

context of names. For the CMOS MIPS (siliconadvanced pipeline processor) program, hedeveloped an assembly code translator to aid incache memory studies. He received his BS inComputer Science from Saint Joseph'sUniversity, and is currently working on an MS inComputer Science at Drexel University.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6635

Harry Rosenthal is Manager of AILS SoftwareEngineering Laboratory, and is responsible forthe development of advanced softwareengineering tools, transfer of softwaretechnology, and computer operations andadministration. Areas of technical focus includevalidation/verification (both formal and informal),modeling/simulation, compilers, operatingsystems, project/product management,database management, and systems analysis.Before joining RCA, he spent twenty years inDoD consulting, primarily in the research anddevelopment sector, and also worked for twocomputer manufacturers. Mr. Rosenthal holdsMA and BS degrees in Mathematics from NewYork University.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6451

Debugger/tracerThe Ada debugger/tracer, anothermember of the SEL's Ada tool set, willprovide a debugging and tracing facilitythat can be used with any Ada compiler.

The features of the debugger/tracerwill include, but not be limited to:

n Breakpoints at specified Ada state-ments. (A breakpoint is an instruc-tion that temporarily stops program

execution, so the user can check sta-tus.) Here, they involve one or morevalue- or range -dependent break-points that, optionally, permit theuser to access variables by name inorder to inspect or alter them.

n Noninteractive display of named var-iables.

Noninteractive modification ofnamed variables with defined values.

G.W. Mebus/L.T. Armstrong/H.Rosenthal: Ada software development tools 63

The user will select debugger/tracerfeatures via an interactive menu. Thedebugger/tracer backend processes thedata structure graph that the frontendproduced from the input Ada sourceprogram, along with the debugging ortracing information that the user speci-fies. The tool then produces an extendedAda source program (using the sourcecode regenerator). Although the newsource program resembles the originalAda source program, additional codehas been inserted for the debugger/tracer functions at program executiontime. The user can compile the new ver-sion of the program using any Ada com-piler.

Other current and future Ada efforts

As part of the SEL's formal verification(Verlangen) effort-also described in

this issue-we will automatically pro-duce an Ada code skeleton from theVerlangen design/specification state-ments. Furthermore, as another activ-ity, ATL will generate Ada code that rep-resents the contents of an expert shell(the knowledge/rule base as well as thecontrol software). Future Ada tools areplanned and will include program archi-tecture diagrams that graphically dis-play the various structures and interrela-tionships in the Ada code of largesoftware systems.

ConclusionsThe Ada language is becoming moreaccepted as the worldwide military lan-guage (the North Atlantic TreatyOrganization-NATO-has decided touse it). While the language can managethe complexity of large software pro -

Camden engineers: Where can you find the latest

information on research in artificialintelligence?

Where can you obtain a currentbibliography on antennas? Onmanagement practices? Parallelprocessing? Computer science?

Which are the most respected andcited journals for research in aspecific field?

What RFPs and contracts are currentlybeing placed for bids by thegovernment?

The answers to these and other questions canbe found in the CISD Library, located inbuilding 10-6-5. The scope of the periodicaland book collection encompasses subjectfields such as engineering, electronics,computers and control, management,mathematics, and physics. The librarymaintains a subscription to the Visual SearchMicrofilm system, which includes militarydocuments, industry standards, and vendorcatalogs on 16mm microfilm.

For information requests not readily filled on-

jects, its own complexity creates prob-lems, particularly for managers, qualityassurance personnel, and code main-tainers. The SEL is developing Adatools that will greatly alleviate growingpains of the new language and allowRCA development of Ada software tobe truly productive and cost-effective.

References1. R.M. Blasewitz, "Ada-Not just another pro-

gramming language," RCA Engineer, Vol. 29,No. 1, pp. 23-31 (Jan./Feb. 1984).

2. G.W. Mebus and E.J. Braude, "Computerlanguages-A view from the top," RCA Engineer,Vol. 29, No. I, pp. 14-22 (Jan./Feb. 1984).

3. Ada Programming Language, Department ofDefense, Washington, D.C. NAM / M1L-ST D -1815A -1983 (January 1983).

4. VAX DATATRIEVE-Guide to Programming andCustomizing, Digital Equipment Corporation,Maynard, Massachusetts (September 1984).

site, the library has access to a wide range ofsources. First and foremost is access to thecollections held by other RCA libraries.Secondary sources of supply include, but arenot limited to, the British Library DocumentSupply Center, the Engineering SocietiesLibrary, and the New Jersey State Library.Contacts are maintained with college anduniversity libraries to obtain books and articleson an interlibrary loan basis.

Bibliographic citations and abstracts ofarticles and conference papers on a widerange of subjects are available on-line frommore than 200 different databases through theDIALOG Information Retrieval Service. The librarystaff can access both the NASA RECONdatabase and the Defense TechnicalInformation Center database.

The Camden library was founded in 1927,and is the oldest library at RCA. It has an activebooks collection of more than 14,000 titles,and subscribes to approximately 300periodicals.

For more information, contact:Nina ArrowoodTacnet: 222-4046

64 RCA Engineer 31-1 Jan. / Feb. 1986

E. J. Conklin

Leonardo: Design environment of the 1990s

RCA is one of 21 members of the Microelectronics andComputer Technology Corporation (MCC) consortium, and oneof ten members of MCC's Software Technology Program (STP).In that capacity, RCA is contributing to the development of ateam design environment for very large/complex systems.

The mission of the Software Technol-ogy Program (STP) at the Microelec-tronics and Computer Technology Cor-poration (MCC) is to introduce, viaprototypes, new software technolo-gies-coherent techniques and tools-that will bring about extraordinaryincreases in productivity and quality inthe laboratories and developmentgroups of the program participants,such as RCA, in about seven to tenyears.

The approach must be focused for thefulfillment of the mission. Accordingly,the STP is aimed at improving activitiesthat precede programming, to effectprofound changes in the way large,complex software is specified anddesigned, especially the realtime con-strained and distributed systems.Because a team of experts usuallydevelops these systems, we will exploit

Abstract: Much has been written andsaid about the official research plans ofthe Microelectronics and ComputerTechnology Corporation (MCC)Software Technology Program (STP),but these plans do not adequatelyconvey the long-term vision that shapesthe research. This article describesLeonardo, one anticipated result ofthese research efforts. The intention ofthe STP is that program participants-for example, engineers and researchersin RCA-find this vision imaginative,stimulating, and compelling.©1986 RCA Corporation.Final Manuscript received November 20, 1985Reprint RE -31-1-10

the team approach to maximize theadvantages it offers in design efficiencyand quality. Support of complex digitalsystem design is also a prime consider-ation, because large portions of futureapplications will be implemented inmicrocircuits, not in software.

Research outside of MCC will con-tinue to be about software development"in the small," and the aspects of pro-gram design that can be automated,such as executable specification andmachine verification. We will incorpo-rate the best results of these efforts andthe STP results into a comprehensivesoftware development environmentprototype called Leonardo.

As the results of research on pro-gramming "in the small" become trans-lated into technology, developmentcosts will shift more toward the earlier,more creative aspects of design. Duringdesign, alternatives are explored andtheir impact assessed. We believe that wecan eliminate or significantly reducemuch of today's costly design efforts byusing the computer as a powerful tool,for example, to offer alternative graphi-cal representations. The computer willalso be a reservoir for design knowledgethat is available during project develop-ment and for maintaining and enhanc-ing the product system.

Briefly put, the STP approach is touse computers to aid the collective inno-vation that must occur in large-scalesoftware development done by a teamof professional programmers. If partici-pants rely solely on their own advancedtechnology efforts and on academic

research, which is often fragmented andnot committed to technology transfer,then essential parts of complex designwill remain unaided by computers formore than a decade. Furthermore, thereis a serious shortage of qualifiedresearchers, which hampers the partici-pants' ability to staff a comparableresearch effort independently.

One caution is necessary, however. Inthis rapidly changing field, anyone whotries to look more than a few yearsahead must abandon strict logic. Thepicture we paint here will almost cer-tainly be replaced by others as theresearch proceeds. No claims about sci-entific rigor, nor promises about specificdeliverables, are being made.

Leonardo

In general, Leonardo is a system thatties together a team of experts. It pro-vides appropriate tools to each expertand has its own body of knowledge, setof skills, and expertise. In addition,each expert has a customized consolelocated in a control room environment.

Leonardo is not just a collection ofspecialized tools. It is an integrated sys-tem for designing and developingsystems- from cradle to grave. It is alsoa communication vehicle among themembers of the design team and all oth-ers who are part of the system -development process.

A central feature of Leonardo is theUnified Product Model (UPM). Thisunified representation of all aspects ofthe system under development, at all

RCA Engineer 31-1 Jan. / Feb. 1986 65

ELECTRONICBLACKBOARD

LARGE VIEWING SCREEN

CONSOLES

G1=0GEi1:1

ELECTRONICBLACKBOARD

___S GLASSED -INOFFICES

Fig. 1. Plan view of the Leonardo control room.

levels, is rich in pointers to related infor-mation in the requirements, specifica-tions, design, implementation, per-formance and testing data, anddocumentation.

The hardware

Leonardo's hardware will be a collectionof high resolution graphics worksta-tions with a 10k by 10k pixel display, 100megabytes of random-access memory,and a multi -gigabyte address space.

These workstations will be linked by agigabaud fiber optic network. They willhave limited voice input (not multiuserconnected speech) and reasonable voiceoutput.

Most workstations will be in officesthat are clustered around a large, central"war room," and will have glass win-dows facing it (see Fig. 1). Several largeelectronic blackboards in the war roomwill allow a group to share an input/output surface and will provide themwith color output as well as ("chalk")input facilities.

The people

The design team consists of user repre-sentatives (including problem domainexperts) and a core group of Leonardospecialists. The size and structure ofboth groups are somewhat flexible,depending on the type and size of theproblem. The Leonardo core groupincludes:

n Project manager-orchestrates theteam's work; maintains the balance

and flow among team members(analogous to an orchestra conduc-tor); also is responsible for schedules,milestones, monitoring and reportingprogress, and managing the designteam.

n Unified Product Model (UPM)engineer-maintains all UPM sub-systems, (analogous to an airlineflight engineer), looking particularlyfor inconsistent points that Leonardocannot spot among team members;tunes and maintains Leonardo; sup-ports the other team members in theiruse of the Leonardo tools.

n Reuse Engineer-recovers and re -engineers any system elements forwhich previous work is available andappropriate, assures that work prod-ucts being developed are reusable,and catalogs them (analogous to alibrarian).

n Specification analyst-maintains therequirements and specifications forthe system under design; ensures theyare current, relevant, complete, andconsistent; develops new representa-tions of the problem as aids for crea-tive problem solving; acts as mediatorbetween user representatives andimplementation specialists (analo-gous to a system analyst or systemengineer).

n Design specialist-serves as an expertin functional decomposition andexploration; guides work distributionamong team members and monitorsthe bushiness of the design tree tooptimize the number of options speci-fied, if not actually explored, at every

decision point; develops new repre-sentations of the system to aid theteam in problem solving; sees that thedesign works.

E Implementation engineer-runs themetacompilers and prototyping sub-system, monitors integration of themodules and subsystems being devel-oped, and ensures they can be inte-grated; spots implementation snags(analogous to a programmer).

E Performance/reliability specialist-analyzes modules in any developmentphase for performance, reliability,and implications to the rest of thedesign.

n User interface specialist-serves as anexpert in user -cordial, high -band-width interfaces; guides developmentof the interface; constructs prototypeinterfaces for user representatives touse and evaluate; is responsible fordocumentation (both on-line andprinted) for the system.

Among the user representatives are:

E User management representative(s)-management people who are con-cerned with development cost anddelivery schedules. Because develop-ment is extremely fast and uses rapidprototyping, the cycle for negotiatingrequirements is very short. There-fore, user representatives withdecision -making power must bepresent.

Cl Problem domain expert(s)-users orindependent contractors who under-stand the context and environment inwhich the developing system will beused and the constraints that thatenvironment places on the system.

n End user representative(s)-represen-tatives of the users who will install,use, and maintain the product systemin the field. This role is similar to theproblem domain experts.

The approach

Each role has a specialized view or per-spective of Leonardo, which consists ofa set of tools that automate the role'stasks (especially the mundane ones),plus a customized graphical interface.

Sometimes, all the roles "meet"together, focused on a single problem oractivity. At other times each role worksalone, or perhaps confers with one ortwo other roles. Many styles of meetingsare supported: from team members

66 RCA Engineer 31-1 Jan. / Feb. 1986

Software TechnologyProgram

The Software Technology Program(STP) is one of the two researchprograms at the Microelectronicsand Computer Technology Corpora-tion (MCC) in which RCAparticipates-the other is thecomputer -aided design/very-large-scale integration (CADNLSI) pro-gram. Since September 1984, whenLes Belady became the MCC STPDirector, 32 researchers in softwareengineering and related fields havebeen hired. The major areas ofresearch efforts are exploratorydesign, teamwork, and early phasesof system development.

Four subgroups work on theMCC STP program:

The Design Process Groupseeks to create models of bothindividual and group design, aswell as technologies to supportthese models.

The Design Information Groupfocuses on ways to abstract thebehavior of programs and onreusability issues.

The Design Interface Groupdevelops ways for designers toview the emerging product.

The Design Environment Groupworks on the architecture ofLeonardo and the integratedenvironment that it will present toits users.

ATL's Software Engineering Labora-tory (SEL) is responsible for MCCSTP technology transfer withinRCA.

meeting around an electronic black-board, to voice, video, and graphicsteleconferencing via Leonardo; to a

shared data base where team memberscan post and exchange the "objects" oftheir work, while graphically viewingthe "space" of shared objects.

However, the team is not dividedaccording to modules or subsystems. Inthis new paradigm, all the team mem-bers work on and apply their expertiseto all parts of the system. Leonardoautomatically does the mundanework-much of which is now donemanually. The people are left with theanalysis, creative decisions, and com-munication. Furthermore, the work nolonger must proceed in a lockstep,waterfall development style. Leonardosupports many design methods, includ-ing top down, bottom up, most criticalcomponent first, and rapid prototyp-ing. It is the UPM and its specializedviews that permit this team approach.On a football team or a surgical teameach member not only has a specific joband a set of skills for doing that job, butalso has a single coherent view of thefield of action. All members can see theproblem, and they can see each other'sproblem -solving activities.

At present, no such single coherentview of the field of action exists in soft-ware engineering. Instead, the evolvingsoftware system exists as a loose, possi-bly incomplete and inconsistent collec-tion of documents, code, and ideas inpeople's heads. By making the evolvingsystem explicit, and by preserving itsconsistency, the UPM allows a team ofexperts to use their specialized views ofthe product, and to add their expertisein a coherent and synergistic way.

Conclusion

This is one vision of Leonardo. The spe-cific roles described are only a guess atthe right division of labor for aLeonardo -like environment. We believethat coordinating a team of expertsthrough a graphical computer networkwill revolutionize the way large systems,

Jeff Conklin, a Unit Manager within ATL'sSoftware Engineering Laboratory, is serving asRCA's liaison representative to the MCC STP. Heis focusing on the area of softwareengineering-the scientific study of theengineering of large, complex computerprograms. Prior to relocating to MCC in Austin,Texas, Dr. Conklin was a Unit Manager withinATL's Artificial Intelligence Laboratory Jeffreceived his PhD and MA degrees in ComputerScience from the University of Massachusetts.Contact him at:MCCAustin, Tex.(512) 343-0860

especially software systems, are devel-oped. A future article will discuss someof the tools and views that differentroles have, and how these roles interactwith each other.

ReferencesI. MCC STP Financial and Operating Plan (F&O),

1986, August 1985. (MCC confidential and pro-prietary document; available upon request only toemployees of MCC and MCC shareholder compa-nies).

2. "MCC: Investment in the Future," RCA Engi-neer, Vol. 29, No. 4, pp 31-32 (July/August 1984).

E.J. Conklin: Leonardo: Design environment of the 1990s 67

J.A. Adams M. Gale J.W. Dempsey G.W. Kaizar N. Straguzzi

Artificial intelligence applications

ATL is investigating a number of applications for practical,deployable Al systems for government and industry.

This article begins with a discussion of the AEGIS ExpertSystem-one of the more mature AI applications. The AEGISsystem combines a knowledge database developed from experts

in the field with information synthesis and classification software

programs. Other applications discussed include automatic testprogram generation, an expert system to help engineers withcomputer -aided design of integrated circuits, voice -computerinterfacing, and battlefield information fusion. The emphasis inall programs is on building practical, deployable AI systems for

government and industry.

The AEGIS EXPERT systemThe first AEGIS cruiser, USS Ticonderoga, demonstrated itsextensive capabilities off the coast of Lebanon as it tracked andreported on all traffic in the area. It was so well received by theNavy AAW Task Group commander that there was an under-standable reluctance to take the AEGIS system off-line for anyreason-even to perform scheduled maintenance! The decisionto take equipment off-line requires extensive knowledge ofwhich faults have minor consequences (because of built-inredundant capabilities), and which faults have serious operationalconsequences and therefore must be corrected as soon as possible.Further, the decision to perform maintenance depends on detailedknowledge of the maintenance options that allow repairs withminimum impact on operational capabilities. These needs forextensive knowledge to support maintenance decisions led toconsideration of a computerized expert system.

Abstract: The Artificial Intelligence Laboratory at ATL isfocusing most of its efforts on three broad application areas inaerospace and defense: information synthesis, classification, andsignal interpretation. A long-term goal of this group is todevelop systematic approaches to the analysis of new problemsin order to select and apply appropriate techniques in a cost-effective manner. Identifying classes of algorithms effective forthese applications is a principal approach toward achieving thisgoal

©1986 RCA Corporation.Final manuscript received November 20, 1985Reprint RE -31-1-11

The AEGIS Operational Readiness Test System (ORTS) canbe a major component of such a system. However, it is primarilyoriented to the detection and isolation of hardware failures. It

does not deal with system set-up problems and varying environ-mental conditions that must be considered when trying todiagnose fault symptoms, nor does it take advantage of theobservations that a person can make at the various tacticaldisplays within the system.

Figure 1 shows the problem of diagnosing faults in systemswith deeply nested equipment interdependencies. Testing andmonitoring equipment generally can identify, through a readinessreporting system, which of several equipment groups are notperforming their functions. However, the monitoring systemmay not be extensive enough to identify a particular assemblyas a common cause of several identified symptoms (see Fig. 1).These faulty assemblies must be quickly identified and repairedto assure uninterrupted availability of system capabilities.

In some cases, it takes considerable training and experienceto infer the actual cause of faults from the observed faultindications. Computer -based expert systems provide the meansto capture such diagnostic expertise from a few human experts,and then to make this knowledge available to others who haveless experience. Such knowledge, based on extended shipboardexperience, can help less experienced system users distinguish

0FAULT "08SERVABLES ARE AMBIGUOUS AS TO LOCATION OF FAULT.

FAULT OBSERVABLES FROMAFFECTED EQUIPMENT

EQUIPMENT AFFECTEDBY ACTUAL FAULT

ACTUAL FAULT

ifFAULTSYMPTOM

FAULTSYMPTOM

FAULTSYMPTOM

READINESS REPORTING SYSTEM

OPT AO EQPT®EOPT ®

WA IIII

Fig. 1. The problem of diagnosing faults in systems withdeeply nested equipment interdependencies.

68 RCA Engineer 31-1 Jan. / Feb. 1986

anomalous observations caused by adverse effects of environment(sea returns, clutter, countermeasures, etc.) from the observationsassociated with system malfunctions or radar performance degra-dations. One objective of the AEGIS expert system is to captureand pass on just such shipboard experience.

How the AEGIS EXPERT system works

MSRD engaged the ATL AI Lab in a joint effort to build acomputerized expert system for AEGIS. It was decided to usean existing program called EXPERT that was originally devel-oped at Rutgers University for medical diagnosis. The programwas designed so that it could accept a human expert's knowledgeof facts and rules used for making diagnoses of problems-notjust for medical problems. Briefly, here is how EXPERT works.The EXPERT system is a computer program that allows theuser to build a database consisting of facts and rules (see Fig.2). The facts provide descriptions of the problem domain interms of observable symptoms, and the conclusions to be drawnor actions to be taken based on those symptoms. The rulesdescribe the relationship between the symptoms and the conclu-sions. The relationships are in the form of IF -THEN rules, asshown in Fig. 2. These rules can show relationships betweendifferent observations, or between observations and conclusions,or between different conclusions.

An important advantage of the EXPERT system is thatbuilding the database does not require any computer program-ming skills. It is no more difficult than using microcomputerspreadsheet programs. After several hours of instruction, a data-base can be prepared by typing the facts and rules into astandard text file (a word -processor file is fine). The file is

accepted by EXPERT, which then compiles it for furtherprocessing. Changes to the database are made by simply editingthe text file and resubmitting it to the EXPERT compiler. Thismakes it convenient to upgrade the database with new facts orrules.

Once the database is prepared, the EXPERT program allowsthe user to consult it for a diagnosis. In the diagnostic session,the user responds to a sequence of questions presented on acomputer terminal in a menu format. Essentially, the questionsseek to determine which facts are relevant to the problem athand. As each fact is identified, the computer program searchesthe list of rules, selecting those that are affected by that fact.When a rule is "fired" (i.e., when it makes use of a particularfact), the program will present the user with questions todetermine the status of the other facts used by that rule. In thisway, the EXPERT system will work its way through the rules,collecting the additional information it needs to finally come tothe conclusions (diagnoses) specified by the rules. The portionof the EXPERT system that "navigates" through the database iscalled an "inference engine"-it makes inferences based on thefacts provided by the user. Figure 3 shows a sample sessionsequence at an AEGIS EXPERT terminal.

Constructing the AEGIS EXPERT system database

The first attempt to develop a database for AEGIS followed thetraditional methods of building expert systems. AI Laboratory"knowledge engineers" conducted interviews with an acknowl-edged AEGIS radar expert. The knowledge engineers had todetermine if the expert's knowledge could be represented in theformats needed by EXPERT's IF -THEN rule system. The objec-

DATABASE

FACTS

Description of Problem Domain Symptoms Conclusions or Actions

RULES

Description of Relationshipsbetween Symptoms and Conclusion,

RULE FORMAT

CONSULTATIONS

USER INTERFACE

1. User enters problem descriptionin response to menu questions.

2. System applies rules to userinputs to prompt for more in.puts until a conclusion oraction is reached.

F[Fact 1 and Fact 2 and Not Fact 3] then -.Conclusion A

Fig. 2. The EXPERT system shell.

tive was to capture the expertise that an individual had accumu-lated at AEGIS test sites and aboard the USS Ticonderoga.These included problems with symptoms observed by radaroperators and other equipment users. No effort was made todiagnose problems that ORTS was designed to detect, althoughthe radar expert did make use of ORTS tests to confirmdiagnoses.

The knowledge engineers recorded five two-hour interviewswith the radar expert. They then studied the transcripts toidentify the relevant problem symptoms and the logical linksleading from those symptoms to their diagnostic conclusions.These were written into the database, and the "human expert"was invited to consult the "computer expert" to determine howwell the system could diagnose a problem from its symptoms.Other knowledgeable people were invited to consult the systemand comment on its effectiveness during this debugging phase.

The resulting database, restricted to SPY -1A radar problems,was demonstrated to MSRD management; they authorized anextension of the database to include problems with computersand disks. A second human expert, acknowledged for his exper-tise in solving AEGIS computer and computer peripheral prob-lems, was made available for a number of two-hour interviews.His database was developed, tested, and merged with the radarexpert's database.

At this juncture, the AI Laboratory provided instructions toMSRD to allow the experts themselves to enter their knowledgedirectly into the system. A database development course wasgiven to several MSRD staff members to describe how facts areentered, how rules are written, and how facts and rules arearranged so that the system makes efficient use of the informa-tion provided.

This new approach was tried by a former Navy MaintenanceChief who served on the second AEGIS cruiser, USS Yorktown.His objective was to enlarge the database with problem symp-toms as detected by detailed ORTS tests, called OperationalPerformance Tests (OPTs). Since there are over 170 of thesetests, and since they can fail in various combinations, it takesconsiderable expertise to interpret how to use them in the faultisolation process. It was decided that this would be an excellentdemonstration of the shipboard capabilities of the AEGISEXPERT system.

An additional objective was to include diagnostic interpreta-tions that identified the operational consequences of OPT failures,as well as to identify the causes of those failures. This could bedone with AEGIS EXPERT by using the same facts in associa-tion with different rules that identify the fault consequences.

Figure 4 shows the current structure of the AEGIS EXPERT

J.A. Adams/M. Gale/J.W. Dempsey/G.W. Kaizar/N. Straguzzi: Artificial intelligence applications 69

database. The system allows merging of separate database sec-tions to permit the accumulation of the knowledge of several

human experts.Figure 5 shows the database designers at a terminal during a

typical consultation session with the system.

*EXPERT RADAR

Type ? for a summary of valid responses to any question asked by the program.

CASE TYPE (1) Case entry

(4) Case Deletion

(2) Visit Entry(5) Demo Entry

(3) Case Review

(6) Program Exit:

I For what type of problem are you consulting this expert system 7

1) Console problems2) Computer problems

3) Radar problems.4) Expert transmitter diagnostics

Choose one:3

USER SELECTS ADEMONSTRATION (5)and identifies aRADAR PROBLEM (3)for consultation

2 SPY signal processor performance observations'I) Loss of detection sensitivity2) RSC Console display: SPY gyro FAILED

3) RSC Console display: WCS gyro FAILED4) RSC Console display: radiate inhibit light is on5) No tracks in region where tracks expected6) Too many tracks7) Intermittent tracks8) Clustered tracks

9) Rings of tracks11) Tracks only on SPY and not on C8D console12) Hung track with non -zero velocity leader13) Clutter noise noticeable on PPI

Checklist:

3. Angle of effect:1) 90 degree effect (1 face)

w 2) 180 degree effect (2 faces on 1 side)3) 360 degree effect (all 4 faces)

Choose one.IN. 2

[AFTER SEVERAL MORE QUESTIONSTO OBTAIN MORE INFO FROMUSER ... EXPERT PROVIDES ADIAGNOSIS]

USER IDENTIFIES PROBLEMSYMPTOM AS "RINGS OFTRACKS" (9) and ANGLE ofEFFECT AS 1800 (2)

INTERPRETIVE ANALYSIS

Diagnostic Status

0 80 IF switch side lobe blanker channel

Treatment Recommendations:I 00 Run ORTS side lobe blanker test

DIAGNOSIS:An IF Switch sidelobeblanker channel problem

ACTION:Run ORTS sidelobe blankertest (to isolate problemto the faulty assembly)

Fig. 3. Portions of a diagnosticEXPERT system terminal.

session at an AEGIS

Current and future plans

Currently, the AEGIS EXPERT system is implemented on aVAX with access through local computer terminals at ATL andMSRD. Project plans call for transfer of the system from theVAX to a microcomputer that will permit shipboard evaluationsand use. An invitation has already been extended to RCA toevaluate the system aboard an AEGIS cruiser at sea.

Implementation on a microcomputer will be based on currentwork at ATL: writing the essential user consultation features ofthe EXPERT system in C language. This will be implementedtogether with a program called ETC (EXPERT to C). TheETC compiler translates an arbitrary expert shell model file intoan equivalent expert system in the C programming language.The Rutgers EXPERT model was selected as the shell becauseof its numerous knowledge engineering and debugging tools, itssimple model file format, its proven effectiveness in severaldomains, and its case -saving mechanism. The programminglanguage C was chosen because its compilers are available onmicroprocessors and it is capable of accessing low-level ascembly-like constructs. When completed, it will be loaded into an IBM

PC AT for evaluation at several user sites.We also plan to include database development capabilities in

future IBM PC AT implementations. They will serve as databasebuilding tools at various land sites linked to shipboard users.

EQUATE self -test expert systemEQUATE is a testing and troubleshooting program used byengineers at ASD in the development of automatic test equip-

prototype expert system enhances the AN/USM 410 EQUATE self -test program and interfaces with soft-

ware currently in use to provide additional capabilities in faultisolation and identification. An expanded knowledge base pro-vides an improved capability for troubleshooting the ATE with-

out the intervention of service engineers. The expert systemreduces the need for expert help and decreases system downtimein the field. Written in Prolog, the system will run on amicrocomputer with 400k of memory.

Automatic test program generationWhen a new device is developed, a set of valid test programsfor the device also must be developed before the unit can befielded. Without these test programs, the device might as wellbe broken. As devices become more complex, ATE test pro-gramming is consuming a growing portion of the cost and timeinvolved in designing a new device. An automatic system towrite ATE test software could reduce both the cost and timeinvolved in the generation of these software programs.

While ATE has been an RCA military business for sometime, particularly for ASD, new hybrid circuits, including hyper -complex VHSIC chips, are rapidly outstripping the ability ofhumans to quickly develop valid tests that isolate faulty com-ponents of a given unit. Automatic test program generation(ATPG) software is needed to produce the programs requiredto test these systems and isolate faults on analog and digitalcircuits. The long-term objective of ATPG is to produce ATEprogram sets, given only the specifications of the ATE and aunit under test (UUT). ATL has advanced to the point ofincluding fault isolation of a UUT with analog components orsimilar digital components with complex stored -state behavior.

In 1985, ATL enhanced the prototype ATPG system to

70 RCA Engineer 31-1 Jan. / Feb. 1986

The AEGIS EXPERT DATABASE consists of sections dealing with problems arising within and betweenmajor system groups.

COMPUTERS ANDPERIPHERALS (DISKS)

SIGNALPROCESSOR

TRANSMITTER

These problems usually present themselves as "OBSERVABLES" in one or more places.

COMPUTER ROOM- Erratic behavior- Error messages

RADAR SYSTEM CONSOLE(HSC)

- OperationalAnomalies

ANTENNA

ORTS CONSOLE- Hierarchy of

test results(OPTS)

Different EXPERTS were enlisted to develop different sections of the database.They identified the fault observables, and the rules for reaching a diagnosis based on those faults.

COMPUTEREXPERT

RADAREXPERT

Their efforts produced on AEGIS EXPERT SYSTEM which can diagnose:

- Console problems- Computer/Peripheral problems- Radar Operational problems

USER

EXPERT

- Transmitter problems- Antenna problems- OPT evaluations (fault consequences)

Fig. 4. The current AEGIS EXPERT database structure.

reason with resource constraints and test sequencing preferencesacquired from the experience of expert test designers. Also,ATL developed a prototype architecture capable of combiningresource planning with diagnostic decision -making, using a testproblem from AEGIS combat system maintenance. The expertknowledge of personnel at ASD and MSRD provided themodel for both of these advances.

Fault isolation for UUTs currently operates at two extremes:1) a technician sits at a station with a collection of manuals andtools and tries to use them in a highly creative way, or 2) ATEis used to attempt to replace the creative technician with hand -coded UUT-specific software that generates an exhaustive se-quence of tests. Both approaches have drawbacks. Techniciansare scarce, slow, and of varying abilities. ATE software is veryexpensive, varies in quality, is very sensitive to engineeringchanges, and often does not exist when the UUT is fielded.

Recent research has been aimed at integrating various systemarchitectures and knowledge sources, but there is no convincingevidence to date that any group has solved any major part ofthe analog ATPG problem. The lack of progress is an indicationof the difficulty of this problem. The identification of a solvablesubpart, therefore, would be a useful and significant contribution.

The test program set (TPS) development process begins withthe study of the UUT. Inputs usually include schematics of theUUT and a functional block diagram of its operation. AnATPG system could change the current TPS developmentprocess by shifting the test designer's function toward mainte-nance of the knowledge base of the ATPG system. Workcompleted this year confirms that it is possible for a knowledge -based system to reason about functions of a UUT of realisticcomplexity and to generate an intelligent test strategy for such aUUT.

At some point, the decomposition of the functional blockdiagram results in functional components that are not divisible,and for which testing strategies are known. Individual compo-nents that can be tested by straightforward methods correspond

Fig. 5. Database designers at a terminal session with theAEGIS EXPERT system.

to primitive statements in the functional flow chart (FFC).Individual components that require tests that are not directlyimplementable by the ATE, or that require critical resources ofthe ATE, correspond to non -primitive instructions of the FFC.

ATL's current approach is characterized as a knowledge -based, depth -first traversal of the graph corresponding to thefunctional block diagram of the UUT. Each node in the graphrepresents a component of the functional diagram, and eachedge a link between these components. Attached to each nodeis a frame of testing strategy and constraints expressed asaxioms and rules. During the traversal, this frame is accessed,and subject to constraints, the strategy it expresses is imple-mented. A frame can be viewed as a micro knowledge basespecific to its component. The algorithm is a depth -first traversalbecause a strategy for any output is generated completely beforeanother output is considered.

J A. Adams/M. Gale/J.W. Dempsey/G.W. Kaizar/N. Straguzzi: Artificial intelligence applications 71

An important feature of this design is that it explicitly mimicsthe problem -solving behavior of ATE software engineers in theprocess of writing ATE software. This approach is distinguishedfrom most others, which use analytic methods or an abstractsystem design to attempt to solve the problem.

Basically, the expansion of the FFC to the detailed flow chart(DFC) can be viewed as a planning problem in which expansionof a non -primitive instruction to a sequence of primitive instruc-tions is accomplished by an operator, subject to the physicalresource constraints of the ATE and its interface equipment.The plan is viewed as a graph with a partial ordering on nodesthat represent actions (instructions). The ordering on actions isextended if one action achieves a precondition of a successoraction, or if two actions interfere with each other. The systemdevelops a hierarchy of plans at different levels of detail. Thehierarchy conceptually corresponds to the decomposition of anon -primitive instruction to primitive instructions, subject to thelimitations of the ATE/interface equipment.

As an example, suppose that part of the current state ofexpansion of the FFC is represented by the following subgraph:

test a

test bor

test c

test d

test e

test f

test g

This is read as, "perform instruction 'a' or 'b' in either order,then 'c', 'd', or `e' in any order, followed by 'f' or `g' in eitherorder." Examining the plan, a critic finds that the physicalresource of the ATE used to test `g' in fact must be allocatedonly after the physical resource used by test 'f' has been allocatedThe ordering on the plan can be refined to:

test a

test b

test c

test d

test e

test g

where tests f(1) and f(2) are primitive, but test f(3) is not.Examining the plan, a critic finds that test f(3) is a preconditionfor test f(1). The plan is reordered to:

test a

test b

test c

test d

test e

test f (1) test f (2)

test f (3)test g

Suppose now that test 'f' is chosen for expansion as follows:

test a

test b

test c

test d

test e

The process of expansion is completed when all non -primitiveinstructions have been reduced to primitive instructions. The setof components that can be evaluated in this manner has expandedto include decoders, sample -and -hold amplifiers, integrators, andflip-flops.

Test design experts at ASD and MSRD are providing criticismto ATL on the ATPG system's performance as part of theformulation of new heuristics for efficient test design. Implemen-tation of these new heuristics will drive successive experimental

cycles of revision and validation by human experts. In thismanner, the scope and complexity of components and systemssubject to ATPG is being improved and expanded. Currently,ATL believes this joint effort by RCA units is two years aheadof the published work in the ATE field.

Information fusion

Information or message fusion is a general class of interpretationproblems that involves assessing evolving situations based oninformation from a variety of sources whose output may not bedirectly comparable.

There are several factors that contribute to the difficulty indesigning an efficient and effective information fusion system.Different sources may contribute information in differing levelsof detail, at varied sampling rates, and with different degrees ofreliability and relevance. Furthermore, the volume of informationavailable may exceed the information processing capacity ofany single intelligent agent. Understanding the computationalrequirements for this class of problems is crucial for the rationaldistribution of tasks among agents, the design of decision supportsystems, and the structuring of effective command, control, andcommunication networks among the interpreting agents.

ATL is conducting computational experiments to investigatethe quality, efficiency, and accuracy of a knowledge -basedinterpretation process for assessing battlefield situations. A varietyof combinations of information source types and several controlstructure variations are being explored. This research is directedtoward meeting the technology requirements of the battlefieldof the future. In addition to basic research on informationfusion, ATL is pursuing several advanced development effortsin which an AI system solves a portion of a particular fusiontask and supports the decision making of a human expert.

One such project at ATL is the Cooperative Anti -SubmarineWarfare Tracker. The goal of this project is to develop anddemonstrate a methodology for designing "cooperative" man -machine problem -solving systems. In these systems men andintellignet machines are organized into coordinated teams tosolve complex problems in a timely and effective manner. Thestrategy employed has been to redesign the existing operationaltracking system, implement the prototype cooperative system,and compare the prototype to the existing system. The unittargeted for redesign has been a Navy airborne system thatlocates and tracks submarines using a variety of sensors.

The initial focus for this project was on the tracking subtaskinvolving passive acoustic sensors, since this is an extremelydifficult subproblem for the human expert. The man -machinesystem deploys sensors and interprets sensor contacts to deter-mine a submarine's current location, course, speed, predictedlocation in the near future, and its tactical plan. A real-timeemulation of the expert's current (operational) tactical work-station was developed to drive the design and evaluation steps.

AI and cognitive science tools and techniques are being usedto design an intelligent machine component, to design the man -machine communication, and to evaluate the man -machinesystem. The design methodology includes specific steps to ac-count for the user's capabilities and limitations, and the skillsand limitations of the human expert are the basis for assigning asupportive role to an intelligent machine component. In thisapproach, we attempt to extend or enhance the user's expertiseand performance beyond the limits imposed by the humaninformation processing architecture, while introducing only min -

72RCA Engineer 31-1 Jan. / Feb 1986

CRT

fVERBEXVERBEX

CONNECT SPEECH IBM PC VICONRECOGNIZER CONTROLLER

DECTALKTEXT -SPEECH 4 -SYNTHESIZER Al

NATURAL - ROBOTICSLANGUAGE CONTROL

PROCESSING PROCESSOR

PAN CAMERA -1 LEFTZOOM IN CAMERA -2

PANTILT

PANTILT

Fig. 6. Natural -language interface demonstration system.

imal overhead for the additional interaction/communicationtasks.

An explicit model of the expert's problem -solving strategyand capacities is developed and used to identify a difficultsubproblem. This subproblem is then distributed to the manand the machine. Cooperative interaction between man andmachine is embedded in the tactical workstation by includingAI -based components that give the machine the capability tomodel the expert's knowledge state and to initiate and carry onintelligent dialogue. The joint problem -solving activity of manand machine is driven by and affects a real-time simulation ofthe tactical environment.

Data collection/recording capabilities built into the simulationtestbed (emulated tactical workstation) support the design,knowledge engineering, and system evaluation experiments.

Researchers at Rutgers University are collaborating withATL on the information fusion work. Basic research at Rutgerson design and planning problems and expertise acquisitionprovides the tools, techniques, and results that make feasible theapplication of artificial intelligence to these complex and ill-defined problem -solving tasks.

Natural language processingAll is developing natural language interfaces that accept Englishqueries and commands and translate them into directives thatcan be understood by the computer. The interfaces are beingdesigned with maximum modularity to enable them to acceptvaried inputs (such as keyboard, voice, and batch text) and tobe adapted to many different kinds of applications.

Natural language interfaces can ease the burden of remotecontrol of multiple simultaneous functions by a human. Userproblems can arise when a sophisticated electronic workstationhas many more controls, displays, and information sources thanany one user can manage, especially during peak periods, orwhen intense concentration on one particular resource is requiredto complete a task. "Hands free" operation of remote devicesallows teleoperators to concentrate on other tasks. The develop-ment of a natural -language voice recognition interface wouldbenefit many existing government programs, including SpaceStation Automation (AED), Astronaut Apprentice (AED),Ground Site for Satellite Control (AED), Vetronics Program(ASD), TCAC Workstation (ASD), Integrated Interfaces

(DARPA), AEGIS Control Room (MSR), Aircraft Communica-tions (CISD), Hands -Busy Cockpit Control (NADC), andRobotics Command and Control. The major focus of naturallanguage processing within the AI Laboratory is voice controlof a robotic environment. In conjuction with the Speech Recog-nition and Robotics Laboratories of ATL, we are currentlyworking to develop an interface that consists of a continuous -speech recognizer and a natural -language parser integrated withAI expert system software and interfaced to camera and robotcontrollers. The initial development goal is to demonstrate theuse of natural -language voice recognition to control the pan,tilt, zoom, and focus of two video cameras mounted at aremote location, while manually controlling the operation of arobot arm mounted at the same location. At this time, thesystem is for a demonstration in which an operator performs atask via video monitors, using a Puma 762 industrial robot armand two video cameras at a remote location, with natural -language voice commands controlling the cameras.

The working demonstration system developed late in 1985(shown in Fig. 6) consists of:

The operator interface-a head -mounted microphone, speaker,two joy sticks, two video monitors, and the IBM PC terminal.

The processing hardware-a Verbex speech recognizer andthe DECtalk speech synthesizer interfaced to the IBM PC asthe central processor.

The robotics hardware-two video cameras mounted ontwo separate pan/tilt units, the Vicon camera controllerinterfaced to the IBM PC with a bank of relays, and thePUMA robot arm.

Current technology, in the form of template -matching recog-nizers, can support only speaker -dependent, constrained -syntax,corrected -speech, and can recognize up to 100 words.

The current system allows the operator to enter voice com-mands that take the form of full or partial sentences. AnAugmented Transition Network (ATN) parser determines thestructure of the command, and discourse analysis software thenextracts the meaning of the command on the basis of thesituational context in which it occurs. If the command is deter-mined to be sufficiently unambiguous, the desired low-levelcommands are sent to the camera controller. For example, ifCamera 1 was most recently referred to, the command "moveright a little" would cause Camera 1 to pan right a small,

J.A. Adams/M. Gale/J.W. Dempsey/G.W. Kaizar/N. Straguzzi: Artificial intelligence applications 73

VERBS:

GERUNDS:

NOUNS:

ADVERBS:

LIMITERS:

ISOLATED:

PAN, TILT, ZOOM, FOCUS, MOVE, GO, STOP, CONTINUE, KEEP

PANNING, TILTING, ZOOMING, FOCUSING, MOVING, GOING

CAMERA -1, CAMERA -2, BOTH -CAMERAS, THE -OTHER -ONE

RIGHT, LEFT, UP, DOWN, IN, OUT, BACK, MORE, AGAIN

A -LITTLE, A LITTLE -BIT, SOME

GOOD, GREAT, OKAY, FINE, WHOA, YES, NO

Fig. 7. Subset of words for demonstration.

predetermined increment. On the other hand, if the previouscommand had been "Both cameras move right," a subsequentcommand of "The other camera zoom in" would cause asynthesized speech message to be sent to the operator requestinghim to clarify which message was meant. The operator mightsay "Camera 1" and then Camera 1 would then start zoomingin.

The Verbex speech recognizer permits a maximum dictionarysize of 100 words. Figure 7 shows some of the words that arein use in the current configuration.

During 1986 the concept of a voice -controlled camera systemwill be expanded to include voice control of an entire roboticsenvironment in which the human operator is attempting tomanipulate an integrated work environment in which a robot,cameras, and a video imaging system are tied together. Theoperator will be able to issue relatively high-level goal commandsvia free -form spoken English. Typical goal commands might be"Remember this location as toolbox," "Camera 1 look at thetoolbox," "Open the hatch," and "Replace unit 1 with unit 2."

The fields of speech recognition, speech synthesis, robotics,natural language, and artificial intelligence are each rapidlyadvancing on a day-to-day basis. The Voice -Controlled Cameraproject provides an excellent example of plans for further devel-opment representative of many multidisciplinary projects atATL, and where rapid prototyping and advanced technologiesare brought to bear on outstanding problems in aerospace anddefense.

MP2D AdvisorTo gain experience with chip design problems and their solutions,the AI Lab has developed a prototype expert system to support

RCA's multiport, two-dimensional (MP2D) automated standard -cell placement and routing program. This program is part ofATL's computer -aided design/design automation system(CADDAS). The purpose of the MP2D Advisor expert systemis to help designers who lack expertise in the use of MP2D toperform input parameter manipulation when iterating MP2Dexecution during chip design. The knowledge engineering processfocuses on classification rules to determine which sets of param-eters to use and how to use them. Experts from the Microelec-tronics Laboratory of ATL collaborated on the knowledge baseand evaluation of the MP2D Advisor.

While MP2D has received high industry marks for being alarge, comprehensive software system helping chip designersproduce efficient 100 -percent -connected chips, it is necessarily avery complex piece of software that offers hundreds of user -selectable options, features, and parameters. Less experiencedMP2D users often find it difficult to use the program to fulladvantage, and may be unaware of the wide range of optionsand capabilities available.

To assist novice and intermediate level users of MP2D,ATL's AI Laboratory, in cooperation with the MicroelectronicsLaboratory, developed MPECS-the MP2D Expert ConsultationSystem. MPECS is an AI -based expert advisor that assists usersin optimizing their chips by identifying and resetting the appro-priate input (IP) parameters to MP2D. The system was imple-mented using EXPERT.

Knowledge engineers from the AI lab interviewed a numberof MP2D experts and determined the manner in which theyapplied their knowledge to a chip design problem. This informa-tion then was encoded into the MPECS knowledge base, whichcurrently includes approximately 230 rules and 190 hypotheses.Because MPECS runs independently of MP2D, it allows AItechnology to be applied immediately to the chip design processwithout interfering with the proven reliability of an existingVLSI tool.

Because of the size and complexity of the MP2D system, itwas decided to confine the initial MPECS implementation to IPparameter identification and manipulation. A designer who hasmade at least one full run of MP2D on his current chip,including artwork, can thereafter call up the expert system.

PREREQUISITESMET?

INPUT: GENERALCHIP DATA

SPECIAL CHIPREQUIREMENTS?

PRELIMINARY

CELL ROWS -RELATED

PROBLEMS

I / 0 PAD -RELATED

PROBLEMS

SUBCHIP -RELATED

PROBLEMS

PRIMARY

SECONDARYACTIONSNEEDED?

MISCELLANEOUS,OFFER MORE

INFORMATION ?,FUTURE RUNS

III

SECONDARY

Fig. 8. Questioning strategy of MPECS.

74 RCA Engineer 31 -1 Jan./ Feb. 1986

MPECS asks the user a number of questions about the currentstate of his chip, and then recommends the parameters andsettings that may be helpful in decreasing the size of the chipand increasing the efficiency of the layout. The procedure maybe iterated as each improvement reveals additional areas forinvestigation. MPECS helps users meet certain special chipdesign requirements, such as non -square shape or special I/O

pad placement. MPECS also offers a limited on-line help facilitythat allows users to access detailed information on certain topicsof MP2D (See Fig. 8).

Future work in MPECS will include expansion of the depthand breadth of the knowledge base, work on improving theMPECS-user interface, increasing the on-line help facility, andfield testing of Version 1.0 of the system.

Jacob A. Adams is a Staff Engineer at RCA's AdvancedTechnology Laboratories. He is responsible for coordinating allATL Internal Research and Development Programs. Mr. Adamsjoined RCA in 1980 and served as Manager, Marketing Planningand Analysis for Command, Control, Communications andIntelligence Systems. He was appointed Manager, MarketingDevelopment and Planning for ATL's Software Engineering andArtificial Intelligence Laboratories in 1983. Before joining RCA,Mr. Adams served as the New Products Manager, TU77/78Tape Drive/Mass Storage System and Manufacturing PlanningManager with the Digital Equipment Corporation. His earlycareer involved systems engineering and program managementin aeronautical systems with the United States Air Force. Mr.Adams has a BA degree in Mathematical Engineering fromWashington University and an MA degree in BusinessAdministration from the Stanford Graduate School of Business.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6411

Joseph Dempsey has been a Senior Member of the EngineeringStaff of ATL's Artificial Intelligence (Al) Laboratory since 1984. Heis involved in the development of Al -based computer -aidedinstruction and the evolution and application of techniques forevidential reasoning. He also has devised a set of criteria forevaluating the applicability of Al to contemplated problem areas.From 1980 until 1983, as Assistant Professor of ComputerScience at Baruch College, Dr. Dempsey taught bothundergraduate and graduate courses in his field. Otherexperience includes the development of a control and analysissystem for psychological experiments, the development of an Almodel of infant intellectual growth, the design of a computer -based system for the development of high -quality tactualgraphics for the blind, and system and numerical analysisprogramming in support of biomedical research. Dr. Dempseyholds a BS in Mathematics from Fordham University, an MS inMathematics from Purdue University, and a PhD in ComputerScience from the University of Pennsylvania.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6643

George W. Kaizar is Unit Manager, Readiness Engineering, atthe Missile and Surface Radar Division. His most recentactivities are concerned with the development of an integratedAEGIS Combat System Readiness Assessment and ReportingSystem that builds on existing AEGIS test capabilities. His earlieractivities were involved with the development and testing ofshipboard automatic test systems such as the AEGISOperational Readiness and Test System (ORTS), and theVersatile Avionics Shop Tester (VAST) to support Navy carrieravionic systems. Mr. Kaizar holds a BS in Electronic Physicsfrom St. Josephs UniversityContact him at:Missile and Surface Radar DivisionMoorestown, N.J.Tacnet: 224-2157

Jr

Authors, left to right: Kaizar, Gale, Dempsey, and Straguzzi(Adams not available).

Morten Gale is a member of the Readiness Engineering unit atthe Missile and Surface Radar Division. He is currently involvedin efforts to enhance AEGIS readiness evaluation and reportingsystems by the introduction of EXPERT systems and otherartificial intelligence tools. His earlier activities included analysisof fault detection and fault isolation capabilities of AEGISelements. Prior to that he was engaged in systems analysis insuch programs as guided missile fusing, Ballistic Missile EarlyWarning System (BMEWS), postal automation, computer -aidededucation, etc. Mr. Gale holds a BS and an MS in ElectricalEngineering from New York University.Contact him at:Missile and Surface Radar DivisionMoorestown, N.J.Tacnet: 224-7718

Nicholas Straguzzi has been a Member of the Engineering Staffof the Artificial Intelligence Laboratory at RCA's AdvancedTechnology Laboratories since 1983. He participated in expertsystem development related to the RCA/MSRD AEGIS prototypeon-line expert diagnostic consultation program for SPY radarand computer systems. He is currently working on the MP2DExpert Consultation System (MPECS), which applies Al to VLSIdesign. Past projects included research into intelligentman/machine interface, including graphics programming. Hisprofessional competence encompasses LISP, PROLOG, andVAX/VMS programming; systems programming; and computer -aided instruction. Mr. Straguzzi has a BSE in Computer Sciencefrom the University of Pennsylvania.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6646

J.A. Adams/M. Gale/J.W. Dempsey/G.W. Kaizar/N. Straguzzi: Artificial intelligence applications 75

W.A. Helbig R.H. Schellack R.M. Zieger

The design and construction of a GaAs technologydemonstration microprocessor

Is gallium -arsenide technology catching up to silicon forintegrated circuits?

The technology maturity of galliumarsenide (GaAs) in processing digitalintegrated circuits is equivalent to thatof silicon in the early 1970s. Today wecan integrate between 1000 and 4000GaAs gates on a single circuit. Yields forthese medium -scale integration circuitsare generally between 10 and 60 percent.

The major factor that currently con-strains larger integration levels with bet-ter yields is the variation in pinch -offvoltage of the GaAs transistors. Im-provements with GaAs processing tech-nology are occurring at a rate that isthree times what occurred in silicon pro-cessing during the 1970s and early1980s. Many silicon processing tech -

Abstract: Because technology hasreached the point where we mayintegrate a few thousand gates on asingle chip, RCA's AdvancedTechnology Laboratories (ATL) isdesigning and constructing an 8 -bit,reduced instruction set microprocessoras a test case for technologydevelopment and demonstration. Weexpect to produce the first operationalsystem by January 1986. This articlediscusses the technology status, designchoices, and project progress andschedule.

01986 RCA Corporation.Final Manuscript received November 20, 1985Reprint RE -31-1-12

niques that have been refined over theyears apply directly to the processing ofGaAs. As a result, integration levelsapproaching 10,000 gates are now beingseen.'

With the low gate delays that the tech-nology provides, a GaAs 100 -millioninstructions -per -second central proces-sing unit (CPU) was easy to design.However, construction of a completesystem to operate at this speed presentssome unique challenges in the designs ofthe system architecture, demonstrationboard, and support software. Forexample, chip -to -chip communicationalong conduction paths on the board(an insignificant problem in the siliconenvironment) is greatly complicatedbecause propagation delays are about 5percent of the CPU cycle per inch ofconductor length, which makes controlof data skew and delay a significant fac-tor in board layout.

We are using the double -level -metalenhancement/depletion (E/D) processprovided by TriQuint Corporation toconstruct the CPU. The chip is partiallyhandcrafted and partially designedusing standard cells, and was laid outusing RCA CADDAS tools. A systemthat consists of the CPU, 512 words ofmemory, and a minimum I/O capabilityis being constructed using leadlessceramic chip carriers (LCCCs) andemitter -coupled logic (ECL) glue chips.It will be mounted on a single boardmade of alumina.

TriQuint's ED foundry services

RCA is currently using the GaAs en-hancement/depletion E/D process pro-vided by TriQuint Semiconductor ofBeaverton, Oregon. TriQuint is a newlyformed subsidiary of Tektronix, also inBeaverton, Oregon. Research in GaAstechnology began at Tektronix in 1978.Two processes are available from Tri-Quint: depletion -mode and enhance-ment/depletion-mode (E/D) proces-sing. RCA is using the low -power, high-speed E/D process to build an 8 -bit,reduced -instruction set CPU (RISC)microprocessor on a single chip.

The E/D process requires a single, 2 -volt power supply. The E/D logic familyis designed to have a 0.6 -volt logicswing. Logic 0 and 1 levels are repre-sented by 0.2 and 0.8 volts, respectively.The E/D logic family has a typical delaytime of 200 ps that is varied based on thegate's output loading. Figure 1 illus-trates output delay times with respect toloading for the E/D gate family.'

The E/D logic family generated forthe 8 -bit microprocessor design was cre-ated for use in a standard cell layoutimplementation. In this approach, thelayouts for all gates in the family havethe same cell height, and the length var-ies as a function of the gate fan -in. Thispermits automatic placement and rout-ing of all standard cells.

The E/D logic family consists of 28gate types for logic design, ranging froman inverter to a 10 -input AND/OR logic

76

1

RCA Engineer 31-1 Jan. / Feb. 1986

gate. Because we used standard cells toimplement the logic, the 8 -bit micropro-cessor-except for its general registerfile and four program counters-requires 1150 gates. We estimate thatthis level of standard -cell integration,combined with the register file and pro-gram counters, should dissipate 427mW of power for the entire micropro-cessor circuit.

Alumina substrate packaging

We will use an 84 -pin leadless-ceramicchip carrier (LCCC) to package the 8 -bitmicroprocessor circuit. System -levelpackaging of the microprocessor withGaAs memory chips (in 40 -pin LCCCpackages) and emitter -coupled logic/transistor -to -transistor logic (ECL/TTL) translators will be done on an alu-mina substrate. The alumina substrateprovides the support platform for thesystem and interconnection (on multiplelevels) of signals between CPU, mem-ory, and ECL input/output (I/O). Typi-cal signal propagation delay time fortransmission line interconnects built onalumina substrates is 250 ps/inch. Thistranslates into a delay time per inch thatis 5 percent of the microprocessor cycletime.

We considered alternative materialsfor packaging the system-beryllia,epoxy glass board, and Teflon-butproblems with them dictated the use ofalumina.

All the interconnects among themicroprocessor, memory, and ECLinterface parts are uniform transmis-sion lines that have characteristic impe-dances of 50 to 100 ohms with adequateload terminations. This ensures that therising- and falling -edge times of 1 ns donot produce unacceptable noise levelsthat would be caused by mismatchedtransmission lines.

ArchitectureThe GaAs technology demonstrationCPU's low level of integration limits itto an 8 -bit machine. A 16 -bit addressallows for memory growth to 64k bytes.The instruction set contains 23 instruc-tions; 19 are 8 bits long and 4 are 16 bitslong. Our goal of 100 million instruc-tions per second (MIPS) requires that aninstruction be fetched every 10 ns. Toreach the 100-MIPS goal, we used a 400 -MHz clock, a RISC philosophy' of sim-

280

260

240

220

200

180

160

140

120

100

80

60

40

20

FALLING -EDGE DELAY TIME- - RISING -EDGE DELAY TIME

50 100

LOADING CAPACITANCE (LF)

GF01

Fig.1. De/ay versus loading for GaAs EiD standard cell family

ple, fast -executing, hardware -frugalinstructions, and a pipeline that permitsthe concurrent processing of severalinstructions. Table I lists the CPU pro-cesses.

A single chip -select bit divides the 512available 8 -bit memory locations intotwo sets of 256 by 4 -bit memories. Wedid this so the lower 256 addresses fallinto two of the four memory chips andthe upper half of the addresses fall intothe other two. The reason for this stemsfrom the nature of instruction and datafetches from memory.

At 100 MIPS, an instruction fetchoccurs every 10 ns. The data fetchesoccur between the instruction fetches.While future memory parts will be ableto handle requests every 5 ns, we wereuncertain that the available memoryparts could do so. With this memory -chip -selection method, we can run twoexperiments on the system.

A program shorter than 256 (8 bits)

instructions can reside in the lower halfand access data in the upper half ofmemory. In this experiment, no mem-ory part is accessed more often thanevery 10 ns. This experiment uses a formof interleaved memories.

A program that is longer than 256instructions can request data from thesame memory chip as current instruc-tions. This will cause memory chipaccesses 5 ns apart. If the system doesnot permit access at 5-ns intervals, then

Table 1. CPU processes

CPU Pipestage Duration (ns) Phase

Request Instruction 2.5 3

Wait 15.0 4, 1

Receive Instruction 2.5 2

Decode Instruction 5.0 3, 4

Execute Instruction 2.5 1

Write -back Result 5.0 2, 3

W.A. Helbig/R.H. Schellack/R.M. Zieger: The design and construction of a GaAs technology demonstration microprocessor 77

/4

DATA IN

/8

DATA LINES

BIT

MUX

IR

LATCHIM

DATA OUT

8/

ACC

4

MUX

ALU 1

IDU CONTROLSIGNALS

TIMING BLOCKAND IDUB LATCH4/

LOGIC FUNCTION SELECT

MUX

ALUBLATCH

ADDRESS LINES

4/12ADDRESSDECODER

AND LATCH

HIGH

MUX

LOW

MUX

8 -BITHALF

ADDER

8 -BITHALF

ADDER

BASE REG R15

REGISTER SELECT

GRBLATCH

GENERALREGISTERFILE

16 BY 8 BITS

Fig. 2. CPU block diagram.

2.5 50 10.0 12.5 150 17S 20.0 22.5NANOSECONDS

REQUESTINSTR WAIT

RECEIVEINSTR

DECODEINSTRUCTION

EXECUTEINSTR

WRITE BACKINSTRUCTION

NANOSECONDS 0 2.5 5.0 7.5

REQUESTINSTRN1

WAITRECEIVE

INSTRN

DECODE EXECUTEIN TR INSTR

N 1 N1

1D .R 12 5 17.55.0 20D

REQUESTINSTRN2

WAIT

225 250

200 MHz CLOCK

PHASES.

Fig. 3. Typical instruction sequence.

we can lower the clock frequency untilthe system works, and thus test the cycletime of the memory parts as they func-tion in the system.

Figure 2 is a block diagram of theCPU developed from these goals andlimitations. The general register stackconsists of sixteen 8 -bit registers, andthe program counter (PC) stack consistsof four 16 -bit registers. The arithmeticlogic unit (ALU) consists of an 8 -bitripplecarry adder, an 8 -bit logic unit,and an 8 -bit output latch (ALUB). Alltwo -operand arithmetic and logic func-tion instructions take one operand fromthe accumulator and the other operandfrom a register in the general registerstack. All branching is relative to thevalue in the PC; the 8 -bit offset is foundin the 16 -bit instruction.

All loops are implemented with a con-ditional branch. All subroutines requirea push, a branch, and a pop. (The cur-rent address in the PC is saved, which isthe push; the subroutine is executed, thebranch; and the original address isretrieved, the pop, and loaded into thePC.) The PC stack exists only to savethe return addresses that make subrou-tines possible. With four PC registers inthe PC stack, subroutine nesting is lim-ited to a depth of three.

The load and store instructions useaddresses that reside in the general regis-ter stack. The most -significant 8 bits ofthe address are taken from register 15,and the least -significant 8 bits are takenfrom a general register that is specifiedin the instruction.

The typical instruction sequence

WRITE BACKINSTRUCTION

N 1

MUX

PC

HIGHPC

LOW

PC STACK

4 BY 16 BITS

RECEIVEINSTR

N2

DECODEINSTRUCTION

N2

EXECUTEINSTR

N2

WRITE BACKINSTRUCTION

N2

27.5 30.0 32.5 35.0 37.5 40.0

given in Fig. 3 shows that an instructionrequest occurs every 10 ns and a pipelinedepth of two to three instructions isprocessed at once. The instructionsdepicted in Fig. 3 represent 8 -bit instruc-tions, or the first half of a 16 -bit instruc-tion.

The instruction register sends thelower four bits of every instruction tothe general register stack as a registeraddress. It sends the upper four bits ofevery instruction to the logic unit tochoose one of the 16 possible logic func-tions of two operands. The logic unit'sresult is disregarded for all instructionsthat are not among the chosen six logicfunction instructions. The general regis-ter stack's output will be disregarded forinstructions that do not require an -oper-and from the general register file.

78 RCA Engineer 31-1 Jan. / Feb. 1986

This method assigns opcodes (opera-tion codes) to the two -operand logicfunction instructions without choice bythe designer. The two -operand nonlogicfunction instructions are chosen nextfrom the remaining unused combina-tions. The four 16 -bit instructions fallinto the non -two -operand, nonlogicfunction category. Their first eight bitsare decoded in the same manner as the8 -bit instructions. Their second eightbits are a constant or a branch offset;the constant or offset is anticipated bythe decoding of the first eight bits (theopcode) of the instructions. The secondeight bits of a 16 -bit instruction are des-tined for the IM register instead of theinstruction -register (IR). These con-stants or offsets are allowed into the IRlatch register, but prevented from exe-cuting by resetting the IR latch registerto zero, which is one of the opcodes fora no -operation instruction.

Chip and system constructionThe GaAs technology demonstrationsystem includes the CPU chip, four 256by 4 -bit GaAs memories, and ECL I/Oparts. The system is shown in Fig. 4.

The GaAs technology demonstrationCPU chip includes custom -designedmacrocells for the general register fileand the program counter stack. The restof the chip is implemented with 1150standard cells. If we had designed theentire chip with standard cells, therewould have been about 2000 gates.

RCA's MP2D layout tool allows theengineer to specify the corners in whichthe macrocells are to be placed. Then,MP2D will fit the standard cells into theremaining chip space as efficiently as itcan. Figure 5 shows a floor plan of theCPU chip.

The CPU will be packaged on an84 -pin leadless ceramic chip carrier(LCCC). There will be ten address lines,eight data -in lines, eight data -out lines,one 400 -MHz clock input, one resetinput, and one read/not-write output.This totals 29 signals. There will be 16power and ground pins and 39 unusedpins.

We have simplified the I/O of thetechnology demonstration CPU chip.The CPU is kept in a dormant state bythe reset pin until the memories havebeen loaded. Then, the CPU goes into ano -operation instruction loop when theprogram is finished. The system's I/O

ECLI/O

ALUMINA SUBSTRATE

GaAsMEMORY

GaAsCPU

GaAsMEMORY

ECLI/O

ECL SUPPORT LOGICDOWNLOADING

UPLOADING

RS232 INTERFACETERMINAL INTERFACEVAX 11/780 INTERFACE

VAX 11/780SOFTWARE

DEVELOPMENTSYSTEM

CONTROLCONSOLE

Fig. 4. GaAs Technology Demonstration System block diagram.

160 MILS

160 MILS

I/O PADS

21 MILS

GENERALREGISTER

FILE

1150

CUSTOMSTANDARD

CELLS

37 MILS

12 MILS

38 MILS

PC STACK

Fig. 5. CPU chip floor plan.

involves loading the GaAs memoriesthrough the ECL interface parts from aDigital Equipment Corporation VAX11/780 computer.

Support software/documentationIn the CPU development, we have usedseveral approaches that are consistent

with RCA's commitment to use formalhardware -descriptive languages. First,we wrote a behavorial model using ISP'.With this model, the assembler andlinker in the ISP' tool set are being usedfor software production. Initially, weused the N.mPc simulator to test theinstruction set and the functional inter-relationships of the system components.

W.A. Helbig/R.H. Schellack/R.M. Zieger: The design and construction of a GaAs technology demonstration microprocessor 79

Later on, we will use it to debug soft-ware.

Next, as the structural design pro-gressed, we expressed the design inRCA's hardware descriptive language,CADL, and simulated the design usingRCA's gate -level simulator, MIMIC.Subsequently, we transferred the designto a hierarchical description using TexasInstrument's hardware description lan-guage (HDL), and resimulated thedesign using Texas Instruments' simula-tor INTSIM. A translator has beenwritten that fetches the connection listfrom the HDL database and converts itinto the proper format for the RCAMP2D layout program. This provides adirect link from a high-level descriptionof the design-in RCA's standardcells-to a complete artwork file (mask -making drive tapes.) Of course, otherprograms handle macrocells.

Currently, three other related soft-ware development projects are in vari-ous stages of completion. First, anassembler/reorganizer program is beingwritten to translate the DARPA core setassembly language into inputs for theISP' linker, reorganizing (optimizing) italong the way to obtain maximum per-formance from a pipeline machine.5.6.7.8.9Second, a set of diagnostic/demonstra-tion routines is being produced to exer-cise all aspects of the system finally pro-duced. This will help us debug the sys-tem and study construction aspects,with an eye toward expansion. And,third, a loader routine is being producedthat, after hand -loading into the system,will enable us to load programs and datadirectly from the support software host,a VAX 11/780 computer.

Status and plansOn December 31, 1985, we were readyto begin layout of the 8 -bit GaAs tech-nology demonstration microprocessor.

Both the 16 by 8 -bit general registerstack and the 4 by 16 -bit programcounter stack have been hand-craftedand are complete. Work on the standardcell layouts for all 20 cell types is com-pleted.

Final layout of the complete micro-processor circuit was done after wecompleted some final circuit simula-tions. These simulations address thetiming and control of all major elementsof the microprocessor.

We delivered a complete design tape

Authors, left to right: Helbig, Schellack, and Zieger.

Walter Helbig is Unit Manager of the AdvancedComputation Systems Group in ATL's SystemsEngineering Laboratory. He is responsible forthe design and implementation of advancedcomputer system architectures. He directed thedesign of the GaAs 32 -bit RISC architecture,and is participating in the construction of the8 -bit GaAs RISC Technology DemonstrationSystem. Previously, he directed the design oftwo versions of the RCA ATMACmicroprocessor, including all of the supportingsoftware, as well as systems utilizing anATMAC. Walt has a BSEE degree from theMilwaukee School of Engineering.Contact him at.Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6530

Robert Schellack is a Senior Member of theEngineering Staff in ATL's MicroelectronicsLaboratory. His work involves GaAs devicemodeling and circuit analysis for high-speeddigital applications. He is incorporatingautomated design capability for high-speeddigital GaAs ICs into RCA's CADDA system. Heis also Principal Investigator for a study ofadvanced GaAs IC technology. Bob has BSEE

and MSEE degrees from Drexel University.Contact him at:Advanced Technology LaboratoriesMoorestown. N.J.Tacnet: 253-6519

Richard M. Zieger is a member of theengineering staff of ATL's Systems EngineeringLaboratory, where he is involved in designingand developing computer architecture. He hasworked with a System Architecture Simulator(SARSIM), modeling and simulating ahigh-speed signal processing system. Recently,he completed the architecture and logic designof an 8 -bit gallium arsenide (GaAs)microprocessor, a pipelined, RISC architectureto be implemented in 1 -microndouble -level -metal enhancement/depletionMESFET technology. The microprocessor isdesigned to operate at a 200 -MHz rate andperform 100 MIPS. Mr. Zieger holds a BS inComputer Engineering from Lehigh University,and has recently begun work on an MSEE atVillanova University.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253.6518

to TriQuint Semiconductor for genera-tion of masks and fabrication.

Work on the development of the dem-onstration system and its support soft-ware is scheduled to continue into thebeginning of 1986.

ReferencesI. Roosild, Sven A., "Survey of Manufacturing

Capabilities for GaAs Digital Integrated Cir-cuits," /984 IC Symposium Technical Digest.

2. Flegal, T., LaRue, G., Rode, A., "A High -YieldGaAs Gate Array Technology and Applications,"1983 GaAs IC Symposium Technical Digest.

3. Hennessy, J.L., Jouppi, N., Baskett, E, Gross,T.R., Gill, J., and Przybylski, S., "Hardware/Software Tradeoffs for Increased Performance,"Proc., SIGARCH/SIGPLAN Symposium onArchitectural Support for Programming Lan-guages and Operating Systems, ACM, Palo Alto,Cal., pp 2-11, (March 1982).

4. Hennessy, J.L., Jouppi, N., Przybylski, S.,Rowen, C., Gross, T.R., Baskett, E, and Gill, J.,"MIPS: A Microprocessor Architecture," Pro-ceedings, Micro -I5, IEEE, pp. 17-22, (October1982).

5. Gross, T.R., "Code Optimization of Pipeline Con-straints," PhD thesis, Stanford University(August 1983).

6. Gross, T.R., and Hennessy, J.L., "OptimizingDelayed Branches." Proceedings, Micro -15,IEEE, pp. 114-120, (October 1982.)

7. Gross, T.R., "Code Optimization Techniques forPipelined Architectures," Proc. Compcon Spring'83, IEEE Computer Society, San Francisco, Cal.,pp. 278-285 (March 1983).

8. Hennessy, J.L. and Gross, T.R., "Code Genera-tion and Reorganization in the Presence of Pipe-line Constraints," Proc. Ninth POPL Confer-ence, ACM, pp. 120-127 (January 1982).

9. Hennessy, J.L. and Gross, T.R., "Postpass CodeOptimization of Pipeline Constraints," ACMTrans. on Programming Languages and Systems,Vol. 5, No. 3, (July 1983).

80RCA Engineer 31-1 Jan. / Feb. 1986

A. Feller

A new methodology reduces design time for verylarge application -specific integrated circuits (ASICs)

Doing tasks in parallel and using modern tools shortens thedesign cycle for new denser chips.

As a reflection of competitive pressures,both the gate counts and complexity ofcustom VLSI devices continue to increasedramatically, along with the requirementof having these devices designed in a shortperiod of time. Thus, custom chips withthree, four, or five times the device countof chips several years ago must still bedesigned in the same amount of time aschips of the past.

Current design VLSI methodologies,based on past LSI or even MSI designapproaches, are responsible for excessivelylong design times. However, one designmethodology that uses current design aidsand design tools does reduce the designtime (by at least half) of custom LSI andVLSI devices having 30,000 transistors ormore; still, the design time does increaseas the gate count increases. This goal is

Abstract: RCA Advanced TechnologyLaboratories has developed a new designmethodology for very large application -specific integrated circuits (ASICs).Unlike conventional design methodologiesthat implement the various design steps insequence, this new design approach doesmany of them in parallel In addition, chiplayouts are initiated with incomplete andunverified logic. This clearly acceleratesthe chip design schedule becausegenerating the complete logic of the testvectors and verifying the logic isfrequently the most schedule -limitingdesign step.

©1986 RCA Corporation.Final manuscript received November 20, 1985

Reprint RE -31-1-13

achieved with little loss in performanceand an area premium of 5 percent to 15percent depending on the ratio of func-tional to random logic.

Design methodology should not be con-fused with design tools. For example, stan-dard cells, handcrafted design, macrocells,automatic placement, and automatic rout-ing are design tools, not design methodol-ogies. Similarly, programs like logic simu-lators, design rule checkers, logic validation,and circuit analysis programs are designaids, not design methodologies. A designmethodology defines procedures and estab-lishes guidelines for utilizing design aidsand design tools to design and lay outVLSI devices.

Tasks in VLSI designApplication -Specific Integrated Circuits(ASICs) are chips designed for dedicated,special-purpose, or user -defined applica-tions. The devices are defined by systemdesigners, with the resulting chip designoften being categorized as top -down design.Following partitioning, the system designerwill generally verify the functionality ofthe partitioned chip through a high-levelsimulator at the functional or RegisterTransfer Language (RTL) level. After veri-fication is completed, the chip describedat a functional or RTL level is transferredto the chip designer. This input containsthe functional description that includesvectors used for system simulation. Startingat this point, virtually all design method-ologies contain the following tasks:

Partitioning and preliminary logic design

Initial macrocell definition (RAM,ROM, register stack, multiplier, bit slice,ALU, etc.)

Macrocell design and validation Logic design Logic simulation (including generation

of test vectors) Layout of chip Fault simulation (where pressing sched-

ules are required, it is not unusual torelease a chip for fabrication beforefull designed fault coverage is attained).

Although these tasks are contained in vir-tually all design methodologies, this onereduces the overall design time because ofthe unique method for carrying out thesetasks. First, the current conventional designmethodology will be described.

Figure 1 illustrates how these tasks areperformed in current conventional customVLSI design methodology. For a devicecontaining about 160,000 transistors, ofwhich 35,000 are associated with randomlogic, typical elapsed times are shown inFig. 1 for the logic design and layout.

Logic design

The first step in the overall logic designinvolves initial macrocell definition andlogic design starting from functional orhierarchical description of the chip. Duringthe logic design phase, test vectors aregenerated and logic simulation is imple-mented. For high-performance VLSI de-vices, prelayout dynamic calculations aregenerally accomplished using the delayand timing capabilities of the logic sim-ulator design tool. Including the generation

RCA Engineer 31-1 Jan / Feb 198681

ESTIMATED SCHEDULE FOR 160.000 - TRANSISTOR CHIP

LOGIC DESIGNLOGICSIMULATION

MACROCELLPARTITIONING ANDDESIGN

PRELAYOUTTIMING ANDDELAYANALYSIS

LAYOUT ANDDESIGN VALIDATION

POSTLAYOUTTIMINGANDDELAYANALYSIS

9 MONTHS 14 MONTHS

Fig. 1. Current, conventional design methodology.

MACROCELL DESIGN

LOGIC DESIGN ANDLOGIC VERIFICATION

DESIGN AND LAYOUTOF CHIP

DESIGN VERIFICATION

PRELIMINARYOUTLINE

65 70 80 90 100 LOGIC DESIGNED

LOGICSIMULATION

= = = = =3

= = 7

1

2 3

DESIGN TIME (MONTHS)

5 6

Fig. 2. The new design methodology. Chip layout depends on macrocell or logic design.

of additional functional macrocells, ninemonths of elapsed time is a typical designperiod that could be expected for chips ofthis size and complexity.

Layout and design validation

Conventional layout techniques generallystart with the generation of a floorplan,which attempts to place the previouslydefined macrocells and the remaining logicin a relationship that will facilitate thenext step, the interconnections (i.e., therouting). During the floorplan generation,additional macrocells will be defined.Because of the difficulty in interconnectingrandom logic functions on a workstation,or any system supporting interactive rout-ing, it is not unusual to implement therandom logic through functional blockssuch as Programmable Logic Arrays(PLAs). To ease the routing problem, notonly is an efficient and optimized floorplannecessary, but corresponding effort mustalso be addressed to the orientation of theI/O pins on all of the macrocell functions.

The only effective way to determine ifan acceptable floorplan has been generatedis to implement the interconnections. Aftersufficient routing has been implemented

to evaluate the floorplan, it is often toolate to generate a new floorplan, if thatconclusion emerged as a result of the rout-ing phase. As the requirement for higherdensity increases, this problem becomesproportionally more difficult.

Post layout timing and delay analysis

The next step in the design process is

verification that the performance, propaga-tion delay, and clock speed specificationshave been met and that all race conditions,clock skew, and timing problems, if theyexist, have been brought to the attentionof the designer. Generally, a logic simulatorcontaining timing analysis capability is usedto measure the performance. However,for acceptable accuracy, the parasitic capac-itance and resistance must be included toupdate the appropriate simulation models.Currently, tools are reported to be capableof doing this for custom, handcrafteddesigns.

After the model is updated for activeload conditions, the timing analysis isrepeated. If the dynamic performance failsto meet specification, corrective action mustbe taken. This corrective action couldinvolve different drivers, different place-

ment, editing of interconnections, and per-haps functional changes. In a conventionalhandcrafted environment, these changesand modifications are implemented in amuch different manner.

Validation

Validating a layout involves a Design RuleCheck (DRC) and verifying that the logicreflected in the output layout (artworkcommands) is identical to the input logic.A DRC check of a conventional hand-crafted layout involves the use of costly,computer -intensive programs such as thePDS or ECAD systems. Verifying the out-put logic is currently done by manualline -tracing to synthesize the logic fromthe traced logic a difficult, laborious, anderror -prone system. Several systems suchas ECAD and PDS have the ability tosynthesize transistors and the logic gatesfrom the layout and, by this means, providea tool to verify the correctness of theoutput logic. These capabilities are nowbeing evaluated for larger chips wheremajor effort is now directed.

New design methodology usingfully automatic androuting capabilityThis new design methodology is based ona fully automatic placement and routingcapability, and other supporting tools thatvirtually perform all of the basic VLSIdesign tasks in parallel as opposed to thesequential mode that characterizes the con-ventional VLSI design methodology. Thismeans, for example, that the design of alarge macrocell (such as a RAM), logicdesign, and the layout of the chip aredone in parallel. The full implementationof this design methodology and its radicaldeparture from the standard design ap-proaches is described and illustrated inthe following sections.

With the new design methodology, theschedule for generating a validated layoutis generally independent of the chip layout.This approach operates in several modes,with the different design parameters beinglimiting factors on the schedule. The overallconcept, together with several of its differ-ent operating modes, is explained and illus-trated in the next section.

Figure 2 illustrates the basic concept ofthe new design methodology. Note thatthe design and layout of the macrocell,the design and verification of the logic,and the chip design and layout are accom-plished in parallel. The design time to

82RCA Engineer 31-1 Jan. / Feb. 1986

complete the chip layout is dependent onthe macrocell design or the logic design,whichever is longer. The chip layout isshown as a dashed line to emphasize thatits length is a variable determined by themacrocell or logic design.

The basic design methodology operatesas follows. Consider the design and layoutof a chip described at a functional orRegister Transfer Level (RTL), which con-tains a functional macrocell such as RAM,ROM Register Stack, Multiplier, BarrelShifter, etc. Because of their functionalnature, the macrocells can generally bedefined earlier in the design cycle. Atsome earlier point, an estimate is made ofits size, aspect ratio, and pin orientation(shown in Fig. 2 as the PreliminaryOutline).

Logic design is initiated at the start ofthe program. Consider that point, as shownin the schedule, when about 70 percent ofthe logic (still unverified) has been defined.At this point, a netlist (interconnectionlist) is generated and entered into the auto-matic placement and routing program thatproceeds to lay out the chip automatically.Obviously, since the logic is incomplete,the layout is treated as a preliminary layout.However, the layout can be reviewed andoptimized using various support tools thatare compatible with the automatic place-ment and routing capability.

The optimization of the layout continuesuntil 100 percent of the logic is generatedand verified. When 100 percent of thelogic has been generated, logic simulationand fault grading can occur.

At this point, design verification canalso be initiated. Assume that the designand layout of the macrocell is completedbefore the logic design and logic simulation.Therefore, the logic design becomes thelimiting item. As soon as the logic is

verified, the layout is validated usingspecial-purpose design -rule checking toolsand a program that automatically verifiesthe output logic.

The first layout that will be used toillustrate the new design methodology is a38,500 -transistor, signal -processing compu-tation chip that contains two macrocells:an 18X18 -bit multiplier and a 16X32 -bitregister stack. The chip was specified tothe chip designer at a functional level;therefore, a complete detail logic designhad to be implemented. In addition, be-cause of the 50-ns requirement placed onthe multiplier, a special optimized Boothalgorithm was developed. It was estimatedthat the design and layout of the multiplierwould exceed the logic design time. There -

ILLUSTRATION OF DESIGN GOAL

INPUT TO CHIP DESIGNER' FUNCTIONAL DESCRIPTION

MACROCELLS: 18X18 -BIT MULJIPLIER16X32 -BIT REGISTER STACK

TRANSISTOR COUNT: 38,70050°o RANDCM LOGIC50°0 FUNCTIONAL

18X18 -BIT MULTIPLIERMACROCELL

16X32 REGISTERSTACK

LOGICDESIGN

LOGICSIMULATION

LAYOUT

PROPOSEDSCHEDULE

ACTUAL DESIGNTIME

DESIGNVERIFICATION

4

CHIP LAYOUT- DETERMINING

FACTOR

OPTIMIZATION= = = w9, CONTINUED JNTILCOMPLETION OFMULTI -DESIGN

2 3

!MONTHS

a

A ARTWORKTAPE

5 6

Fig. 3. Design and layout of a signal processor computation chip.

18X18 MULTIPLIER

16 -WORD X 32 -BIT. 3 -PORTREGISTER STACK

CHIP SIZE: 277X258 MILS

INTERNAL SIZE: 222X200 MILS

CHIP DENSITY: 1.86 MILS'/DEVICE

INTERNAL DENSITY: 1.19 MILS'/DEVICE

DESIGN STARTED: 30 JULY 1984- INPUT: FUNCTIONAL DESCRIPTION

DESIGN COMPLETED: 7 DECEMBER 1984- OUTPUT: VERIFIED ARTWORK TAPE

Fig. 4. The Thetis -B signal processor computer chip.

fore, the proposed schedule for the chip,shown in Fig. 3, indicates the multiplierdesign time to define the chip layout time.As given in the schedule, four monthswere allotted for the design of the multi-plier. The logic design was completed andverified in about two months. In the firstfew weeks, the multiplier outline, aspectratio, and pin assignment were generatedon a preliminary basis. With the incompletelogic and the preliminary outline of themultiplier, a layout of the chip was gener-ated using the automatic partitioning, place-ment, and routing capability of the RCAVLSI design system.

Coincident with the design of the logic

and multiplier is the optimization of thedynamic performance and the topologicaldesign of the chip layout using a series ofspecial-purpose design tools developedspecifically for that purpose.. For example,one of the tools used for dynamic perfor-mance optimization is the CRIPTIC pro-gram. This program identifies and selectsthe critical timing paths automatically.CRIPTIC automatically extracts the para-sitics associated with the interconnectionsand performs delay calculations that includethe effect of the layout parasitic&

In acklition to the dynamic performanceevaluation and optimization, the layouttopology is also optimized while the logic

A. Feller: A new methodology reduces design time for ASICs 83

and the multiplier macrocell are beingdesigned. This optimization is based onutilizing the automatic partitioning andplacement capabilities to optimize theplacement and therefore the layout. Inthis mode, an engineer might spend up toan hour providing inputs that will enable

the placement to be optimized. The chipis then laid out using the automatic routingprogram. Again, the key to the new designmethodology is the fully automatic routingprogram and the way it is used to allowdesign functions to be done coincidentallyas opposed to sequentially.

A. PROPOSED SCHEDULE

32X32REGISTERSTACK

LOGIC

LAYOUT OFCHIP

DESIGNSPECIFICATION

A VERIFIED LOGIC

B. ACTUAL DESIGN CYCLE

32X32REGISTERSTACK

LOGIC

CHIPLAYOUT

DESIGNVERIFICATION

I I

COMPLETE LOGIC57000

==2 3

MONTHS

4

MANUAL CHECK

LOGIC CHANGE

.ft(

5

VERIFIED LOGIC (MIMIC)

LOGIC CHANGED54000

4652 430' 420'

LOGICCHANGE

380' 3652 REDUCTION OFCHIP AREA

ARTWORKTAPE DELIVERY

2 3

MONTHS

4 5 6

Fig. 5. Microprocessor design.

54.000 TRANSISTORS

MACROCELL- 32X32 REGISTER STACK- STACK DENSITY = 55 MILS,/TRAN.

CHIP SIZE (S&R) 365X368- S&R DENSITY: 2.48 MILS'/TRAN.- ACTIVE DENSITY: 1.79 MILS2/TRAN.

DATE STARTED: NOVEMBER 1984

ORIGINAL END DATE 28 FEBRUARY 1985

DATE DELIVERED 7 APRIL 1985 IMIHROUluilmii -NOM

Fig. 6. Multiple -instruction set microprocessor chip.

As shown in Fig. 3, the multiplier, whichwas the schedule -limiting item, was donein four months. Within the next two weeks,the layout was completed, checked forlogic correctness and design rules, andmask artwork generated.

Thus, a design that would normallytake 12 to 16 months to lay out using theconventional design approaches was com-pleted in 4.5 months. A layout of theactual chip is shown in Fig. 4. Note in thechip statistics that an overall chip densityof less than two square mils per devicewas achieved for a chip containing almost39,000 transistors, about one-half of whichis random logic.

The second layout that will be used todemonstrate the new VLSI design method-ology is a 54,000 -transistor chip that ispart of a sophisticated microprocessor chipset. This chip contains one macrocell, a32X32 -bit register stack. In this case, thelogic was described as complete, but not

Al Feller recently transferred to theMicroelectronics Center as Manager ofthe CAD and VLSI Design Laboratory. Heis responsible for continuing developmentof a comprehensive system for automateddesign, layout, and testing of VLSI/VHS'circuits. He began this work at AdvancedTechnology Laboratories, where he wasProgram Manager for several CADdevelopment contracts. In addition todeveloping RCA's Computer -AidedDesign and Design Automation System(CADDAS), his group designed over 100LSI circuits using five differenttechnologies. Al received BSEE and MSEEdegrees from the University ofPennsylvania. He is the recipient of aDavid Sarnoff Award for OutstandingTechnical Achievement.Contact him at:Advanced Technology LaboratoriesMoorestown, N.J.Tacnet: 253-6544

84RCA Engineer 31-1 Jan. / Feb. 1986

verified (test vectors had yet to be gener-ated). It was estimated that the design,layout, and complete verification and vali-dation of the 32X32 -bit register stackmacrocell would take about four months.Thus, this was established as the originalschedule for the entire chip design andlayout (see Fig. 5a).

Although the logic was originally de-scribed as complete, it in fact was not.The logic experienced at least two majorchanges and was not verified as correctuntil more than four months after thestart of the program (see Fig. 5b, whichdocuments the actual design cycle). Thus,as given in Fig. 5b, the logic design, notthe macrocell design, became from a prac-tical viewpoint the limiting task for thedesign and layout of the chip.

The basic premise of this new designapproach (that the layout itself is not thelimiting task) is clearly illustrated by thechip layout task in Fig. 5b. Notice thatafter the third week of the program, achip layout was produced whose size is465X465 mils. This layout reflected thestate of the logic design at the time andused a macrocell outline based on prelim-inary estimates. Within these constraints,the layout was complete and optimizationtechniques were initiated. First, while thelogic and macrocell designs were proceed -

Looking back . . .

ing, the area of the layout was beingreduced by various techniques that are apart of the RCA VLSI design methodology.When the logic was completed and verifiedusing the RCA logic simulator program(MIMIC), the chip size had been reducedto 365X365 mils, about a 30 -percentdecrease from the original layout. In addi-tion, timing, delay, and critical path analysisand optimization were also done duringthe design period, as illustrated in Fig. 5b.

Within a month after the logic wasfinished and confirmed, the design, layout,and verification of the chip were completedand an artwork tape generated to be usedby the mask -making facility to fabricatethe masks. A layout of the chip is presentedin Fig. 6.

The next two devices to be designedwith this new design methodology contain190,000 and 160,000 transistors, respec-tively. In each case, about 70 percent ofthe logic appears in the form of macrocells,while the remainder can be characterizedas random logic. The schedule calls for a5 -month design cycle starting with justthe outlines of the macrocells and at least70 percent of the random logic. If a higherpercentage of the completed logic is avail-able, then either the schedule can bereduced or the chip area reduced for the5 -month schedule.

At the time of publication of our previousissue (Nov./Dec. 1985), George Whitley, RCALaboratories, author of "Cut and clinchinnovations in printed circuit boardassembly," was assigned to a special projectat Consumer Electronics Operations,Indianapolis, Indiana. George has sincereturned to RCA Laboratories, Princeton, N.J.,and anyone wishing to contact him inconnection with his article may do so atTacnet: 226-2709.

Summary and conclusionA new design methodology for ASICsexists and is available. Where conventionaldesign methodologies implement the vari-ous design steps in sequence, this newdesign methodology implements many ofthem in parallel. In addition, when usingthis new design methodology, chip layoutsare initiated with incomplete and unverifiedlogic. This clearly accelerates the chip de-sign schedule because generation of thecomplete logic of the test vectors andverification of the logic is frequently oneof the most schedule -limiting design steps.The key to this design methodology is thefully automatic placement and routingcapability that permits the interactive lay-outs to be implemented until the logic iscomplete and verified. If density optimiza-tion is required, it can be achieved byadditional application of the iterative layoutprocedure until the desired density isachieved.

It is reasonably clear that as ApplicationSpecific Integrated Circuit devices start toexceed the 50,000 -transistor level, and ifexcessive and unacceptable design timesare to be avoided, present conventionaldesign methodologies must be replacedby those that have properties and charac-teristics of the new design methodologyjust described.

A. Feller: A new methodology reduces design time for ASICs85

Patents

Aerospace and Defense

Hayman, J.Multilevel thresholding for target trackingapparatus -4550435

Astro-Electronics Division

Altman, W. P.High-energy, single longitudinal modehybrid laser -4554666

Ganssle, E. R. Miller, C. P.Reflector antenna mounted in thermaldistortion isolation -4550319

Broadcast Systems Division

Bendell, S. L.Television camera with solid-stateimagers cooled by a thermalservo -4551760

Hamalainen, K. J.Adaptive automatic scan trackingsystem -4550351

Consumer ElectronicsOperations

Blatter, H. Amaral, J. E.Microprocessor self -turn-off arrangementfor a consumer instrument -4544923

Carlson, D. J.RF Diplexing and multiplexingmeans -4555809

Chen, K. J.Television receiver with high voltageprotection circuit -4544954

Fling, R. T.Binary divider as for a digital auto fleshcircuit -4550339

French, M. P.On -off arrangement in a microprocessorcontrolled remote transmitter for aconsumer instrument -4544924

Hettiger, J.Trilevel sandcastle pulseencoding/decoding system -4549202

Norley, R. R. Sendelweck, G. K. Chen,K. J.On -screen display -4549218

Sendelweck, G. K.Automatic contrast reduction circuit for ateletext or monitor operation -4549217

Shanley, R. L., 2ndDC stabilization system -4549203

Shanley, R. L., 2nd Yost, T. D. Lagoni,W. A.Keyed DC stabilization system withprotection from error introduction duringvertical sync interval -4554577

Shanley, R. L., 2ndControl system forluminance/chrominance signalprocessing circuits -4554588

Vanbreemen, B.Vertical color shift correction in a rearprojection television screen -4544946

Willis, D. H.Error compensated control system in avideo signal processor -4554578

RCA Laboratories

Acampora, A.Circuitry for correcting motion inducederrors in frame comb filtered videosignals -4553158

Altman, T. N. Fedele, N. J.Low cost monotonic digital -to -analogconverter -4544911

Batterman, E. P.Signal transition enhancementcircuit -4553042

Blackstone, S. C. Jastrzebski, L. L.Corboy, J. F., Jr.Vertical igfet with internal gate andmethod for making same -4546375

Botez, D. Connolly, J. C.Method of making a laser array -4547396

Carlson, C. R.Spatial prefilter for variable -resolutionsampled imaging systems -4554585

Chin, D.Auto -tint circuit for a TVreceiver -4544944

Corboy, J. F., Jr. Jastrzebski, L. L.Blackstone, S. C. I Pagliaro, R. H., Jr.Method for growing monocrystallinesilicon on a mask layer -4549926

Derendinger, M.Apparatus for applying a layer of powderto a surface -4550680

Dieterich, C B.Video disc encoding and decodingsystem providing intra-field tract errorcorrection -4549228

Dischert, R. A. Moles, W. H. Rhodes, R.N. Walter, J. M.Digital video transmissionsystem -4550337

Ettenberg, M.Optical recording medium andinformation record and method of makingsame -4547876

Gange, R. A.Line cathode heater and supportstructure for a flat panel displaydevice -4551648

Gibson, J. J.Demodulator of sampled data FM signalsfrom sets of four successivesamples -4547737

Gibson, W. G. Plotnick, M. A. Chen, T.Y.

Video disc encoding and decodingsystem providing intra-field track errorcorrection -4546389

Haferl, P. E.Switched vertical deflection circuit withbidirectional power supply -4544864

Haferl, P. E.Variable picture size circuit for atelevision receiver -4547708

Hinn, W.Video signal DC restorationcircuit -4549214

Hurst, R. N., Jr.1 Dischert, R. A.Apparatus for correcting errors in colorsignal transitions -4553157

Jastrzebski, L. L. Ipri, A. C.Vertically integrated igfetdevice -4554570

Kao, Y.Auto flesh circuitry as for a digital TVreceiver -4554576

Kern, W.Deposition of borophosphosilicateglass -4546016

86 RCA Engineer 31-1 Jan. / Feb. 1986

Pen and Podium Recent RCA technical papers and presentations

To obtain copies of papers, check your library or contact the author or divisionalTechnical Publications Administrator (listed on back cover) for a reprint.

Advanced TechnologyLaboratories

G.O. Abrams I J.K. PetersA VAX -Based Personal ComputerEthernet Network-Presented at the 1985Fall DECUS Symposium, Anaheim, Cal.(12/10/85) and published in theProceedings

G.J. Ammon I J.A. Calabria I D.T. ThomasA High -Speed, Large Capacity"Jukebox" Optical Disk System-Presented at the 7th IEEE Symposium onMass Storage Systems, Tucson, Ariz.(11/4-7/85) and published in theProceedings

J.W. DempseyRelevant Help, User Modeling, andUncertainty-Presented at the U.S. ArmyResearch Institute Symposium onRobotics and Artificial Intelligence, AustinTex. (11/6-7/1985) and published in theProceedings

M.L. LeveneA High Data Rate, High Capacity OpticalDisk Buffer-Presented at the 7th IEEESymposium on Mass Storage Systems,Tucson, Ariz. (11/4-7/85) and publishedin the Proceedings

J.I. Pridgen I D.P. O'Rourke I R.O. YeagerA.I. BrambleAgile, Low Power CMOS/SOSFrequency Synthesizer-Presented at the1985 Government MicrocircuitApplications Conference, Orlando, Fla.(11/5-7/85) and published in theProceedings

D.C. Smith I R.N. Putatunda I S.A.

McNeary J.C. CrabbeHAPPI: Fully Automatic Design forSubmicron, Subnanosecond IC Designswith 50k to 400k Transistors-Presentedat the Government ApplicationsConference, Orlando, Fla. (11/5-7/85)and published in the Proceedings

R.T. Strong I E.G. Watson I J.R. TowerThick Film Hybrid Application toCryogenic Infrared Imaging Arrays-Presented at the ISHM Conference,Anaheim, Cal. (11/11/85) and publishedin the Proceedings

Astro-Electronics Divison

T.A. MorrisOmnistar On -Orbit Servicing and ModuleExchange-Presented at the NASA, JSC,Satellite Services Workshop (11/6/85)

N. LaPrade H. ZelenSolid State Power Amplifiers forCommunication Satellites-Presented atWESCON '85, San Francisco, Cal.(11/19-22/85)

K.V. Raman I A.J. CaliseOn Modal Decoupling Insensitivity-Presented at the AIAA, ASME, IEEEAmerican Control Conference, Boston,Mass. (6/19-22/85)

S.S. Seehra G.J. Brucker I C.K. BowmanStudy to Establish Data Sheets for CMOSDevices in Space and NuclearApplications-IEEE Transactions onNuclear Science (12/85)

Automated Systems Division

R.L. Cahoon I N. Meliones B.M.McDermottComputer -aided design of a lightweightelectronic rack-RCA Engineer, Vol. 30,No. 6 (Nov./Dec. 1985)

R.C. GuyerMini Laser Rangefinder-RCA Engineer,Vol. 30, No. 6 (Nov./Dec. 1985)

S.C. HaddenTest and Monitoring Developments forUS Army Gas Turbines-The TechnicalCooperative Program (TTCP) Meeting,NAVAIR, Arlington, Va. (9/85)

J.F. MartinSTE-ICE....A Soldier's Friend-TheOrdnance Magazine, U.S. Army (8/85)

RCA Laboratories

R. AmanteaAn Introduction to Modeling andSimulation-RCA Review, Vol. 46 (9/85)

R. Amantea I B. HwongIntegrated Simulation of CMOSTransistors-RCA Review, Vol. 46 (9/85)

J.K. Butler I D.E. Ackley I M. EttenbergCoupled -Mode Analysis of Gain andWavelength Oscillation Characteristics ofDiode Laser Phased Arrays-IEEEJournal of Quantum Electronics, Vol. QE -21, No. 5 (5/85)

C.R. Carlson I R.W. KlopfensteinSpatial -frequency model forhyperacuity-Journal of the OpticalSociety of America A, Vol. 2, page 1747(10/85)

W.R. Curtice I M. EttenbergN-FET, a New Software Tool for Large -Signal GaAs FET Circuit Design-RCAReview, Vol. 46 (9/85)

G.M. Dolny I H.R. Ronan, Jr. I C.F.

Wheatley, Jr.A SPICE II Subcircuit Representation forPower MOSFETs Using EmpiricalMethods-RCA Review, Vol. 46, (9/85),and presented at the Power ElectronicsDesign Conf., October 15-17, 1985,Anaheim, Cal.

B.R. EpsteinA Program to Test Satellite Transpondersfor Spurious Signals-RCA Review, Vol.46 (9/85)

T.J. Faith I R.S. Irven E.P. BertinHigh -current and thermal -shock testingof TaSi2-polycide/Al-alloy composites-J.Vac. Sci. Technol. B., Vol. 3, No. 5(Sept./Oct. 1985)

M.A. Lampert I R.U. MartinelliBuffering of charge by the coulombcondensate in non-linear poisson-boltzmann theory-Chemical PhysicsLetters, Vol. 121, No. 1,2 (11/1/85)

P.A. LyonDesorption Mass Spectromety-Are SIMSand FAB the Same?-ACS SymposiumSeries 291, American Chemical Society,Washington, D.C. (1985)

C.W. Magee I E.M. BotnickOn the use of secondary ion massspectrometry in semiconductor devicematerials and process development-Mat. Res. Soc. Symp. Proc. Vol. 48

D. MeyerhoferSimulation of Microlithographic Resist

RCA Engineer 31-1 Jan. / Feb. 1986 87

Processing Using the SAMPLEProgram-RCA Review, Vol. 46 (9/85)

S.M. PerlowNew Algorithms for the AutomatedMicrowave Tuner Test System-RCAReview, Vol. 46 (9/85)

H. Schade Z.E. SmithMie scattering and rough surfaces-Applied Optics, Vol. 24, page 3221(10/1/85)

H. SchadeEnhancement of oxygen adsorption onsilicon following electron irradiation-Applied Surface Science 24, North -Holland Amsterdam (1985)

C. H. SteinbruchelOn the sputtering yield of molecularions-J. Vac. Sci. Technol. A, Vol. 3, No. 5(Sept./Oct. 1985)

L.K. WhiteA Modelling Study of SuperficialTopography for Improving Lithography-J. Electrochem. Soc., Vol. 132, No. 12(1985)

Missile and Surface RadarDivision

A.K. Agrawal W.E. PowellMonopulse Printed Circuit Dipole Array-IEEE Transactions on Antennas andPropagation, Vol. AP -33, No. 11 (11/85)

W.M. AtwoodHelping the FAA Modernize our Nation'sAir Traffic Control System-RCA's Role-Trend, Vol. 25, No. 8 (12/85)

Solid State Divison

C.F. Wheatley, Jr.1 G.M. DolnyCOMFET-The Ultimate Power Device; AGeneral Study of Power Devices-SolidState Technology (11/85)

W.D. Williams R. Duclos N.J. MagdaA new approach to surge suppression-Electronic Component News (9/85)

Engineering News and Highlights

Dusio named Division VP,Engineering at ASD

The appointment of Emilio W. Dusio asDivision Vice President, Engineering, hasbeen announced by Eugene M. Stockton,Division Vice President and General Man-ager, RCA Automated Systems Division.

A 24 -year RCA employee, Mr. Dusio isresponsible for Automated Systems Divi-sion's wide range of engineering services.The position was previously held by EugeneM. Stockton, who was promoted to DivisionVice President and General Manager lastfall.

Mr. Dusio comes to Automated SystemsDivision from RCA Astro-Electronics Divi-sion, where he served as Manager, AstroDesign Engineering. Previously, he held anumber of engineering management posi-

tions in electronic systems, software engi-neering, the TIROS -N and DMSP meteoro-logical satellite programs, and variousspecial projects.

Mr. Dusio received Bachelor's andMaster's degrees in Electrical Engineeringfrom New York University. He also holds aMaster's degree in Computer Science fromMonmouth College. Before coming to RCAin 1961, he worked for two years as anengineer at ITT Federal Labs. Mr. Dusiohas written a number of technical paperson software and spacecraft testing, and isa member of the IEEE, AIAA, and ACM.

Charles A. Schmidt has been elected GroupVice President, Government Communica-tions Systems. A 35 -year RCA employee,Mr. Schmidt previously was Division VicePresident and General Manager, RCAAstro-Electronics Division, a position he hadheld since 1981.

In his new position, Mr. Schmidt is respon-sible for the RCA Communication and Infor-mation Systems Division and RCA Govern-ment Volume Production, both located inCamden, N.J. The two organizations providea wide range of electronic products andsystems to government and commercialcustomers. He reports to John D. Rittenhouse,Executive Vice President, Aerospace andDefense.

After Joining RCA in 1950, Mr. Schmidtheld a number of engineering and manage-ment positions at Government Communica-tions Systems. Before moving to RCA Astro-

Charles A. Schmidt is GroupVice President, RCAGovernment CommunicationsSystems

Electronics, he was Manager of IntegratedCommunications Systems, with responsi-bility for the Navy's Trident submarine Inte-grated Radio Room and other advancedcommunications programs. Most recently,Mr. Schmidt was largely responsible forthe formation of EOSAT, a joint venture ofRCA and Hughes Aircraft that has assumedresponsibility for commercial operation ofthe U.S. Government's Landsat program.

Mr. Schmidt received a Bachelor of Sci-ence degree in Electronic Physics fromLaSalle College in 1965. He also is a grad -

88RCA Engineer 31-1 Jan. / Feb. 1986

uate of the Harvard Business School'sAdvanced Management Program.

Mr. Schmidt is an Associate Fellow ofthe American Institute of Aeronautics andAstronautics (AIAA), a member of the Boardof Governors of the National Space Club,and a member of the American DefensePreparedness Association (ADPA), the AirForce Association (AFA), the Associationof the U.S. Army (AUSA), the Navy League,and the Armed Forces Communications andElectronics Association (AFCEA).

Staff announcements

Aerospace and Defense

Preston N. Shamer, Manager, AdvancedProgram Development, announces the ap-pointment of Richard H. Smith as Manager,Advanced Intelligence Programs.

Donald L. Gilles, Staff Vice President,Employee Relations, announces that thefollowing individuals are assigned as full-time Trainer/Facilitators for the Aerospaceand Defense Quality and Management Im-provement training programs: Frank G.Adams, Missile and Surface Radar Division;Robert E. Park, Price Systems; and JosephWylen, Communication and Information Sys-tems Division.

Automated Systems Division

Eugene M. Stockton, Division Vice Presi-dent and General Manager, Automated Sys-tems Division, announces the appointmentof Emilio W. Dusio as Division Vice Presi-dent, Engineering.

Communication andInformation Systems Division

Donald J. Parker, Director, Digital Com-munications and Recording Systems, an-nounces the appointment of WilliamBlackman as Manager, COMSEC Programs.

Consumer Electronics

Elliott N. Fuldauer, Manager, Materials,announces the appointment of Gary L. Dyeras Manager, Production Control.

Harry Anderson, Division Vice President,Program Management, announces hisorganization as follows: Grant A. Adkins,Manager, Development Projects; David G.Campbell, Administrator, Development Proj-ects; Dudley W. Jaggar, Administrator,Development Projects; and Grant A. Adkins,Acting Administrator, Development Projects.

John M. Weisel, Manager, Strategic Sourc-ing, announces the appointment of JamesG. Bishop as Manager, Monitor Sourcing.

Willard M. Workman, Director, ProductEngineering, announces the appointmentof Tom W. Branton as Product Manager,Color Television.

Electronic Products &Technology

George D. Prestwich, Staff Vice Presidentand Corporate Quality Executive, an-nounces the appointment of Paul W.DeBaylo as Director, Quality Processesand Measurement. In this capacity, Mr.DeBaylo will work closely with all MajorOperating Units in developing, implement-ing, and improving processes and measure-ment techniques designed to achieve RCA's"Total Quality" objective.

Microelectronics Center

Dennis R. Rickmon, Manager, Computerand Design Services, announces his orga-nization as follows: Vicki J. Fowler, Man-ager, Integrated Circuit Artwork Design;and Louis J. Judice, Manager, EngineeringComputer Services.

NBC

Michael Sherlock, Executive Vice President,Operations and Technical Services, an-nounces the appointment of Edgar Fereiraas Manager, System Implementation.

RCA Laboratories

James C. Miller, Acting, CAD System Ser-vices, announces his organization as fol-lows: Rodney L. Angle, Manager, VLSIDesign Systems, and William M. Cowhig,Manager, VLSI Design Services.

Dr. Karl Knop, Director, Research, RCALaboratories Ltd. (Zurich), announces hisorganization as follows: Michael T. Gale,Group Leader, Optics, Dr. Gunther Harbeke,Group leader, Solid State Physics; and Dr.Hans W. Lehmann, Group Leader, MaterialsSynthesis and Evaluation.

Louis S. Napoli, Director, Integrated CircuitResearch Laboratory, announces the ap-pointment of Norman Goldsmith as StaffScientist.

Solid State Division

Herbert V. Criscito, Division Vice President,Marketing, announces the organization of

a newly created Strategic Partnering func-tion as follows: Lucien P. DeBacker, Direc-tor, Strategic Partnering-Rockwell/RCAA&D/SCI; Alfred Marmann, Director, Stra-tegic Partnering-Europe; Thomas C.McNulty, Director, Strategic Partnering-Chrysler/Delco Remy; and Melvin L.Petersen, Director, Strategic Partnering-Ford.

Professional activities

ATL paper wins award

The International Society for Hybrid Micro-electronics named the posterboard presen-tation "Thick Film Hybrid Application toCryogenic Infrared Imaging Arrays" theoutstanding paper of the November 1985conference. The paper, which focused onsystem requirements for mounting and pack-aging silicon Schottky barrier diode CCDdetector chips and related successful de-sign solutions, was a joint effort of ATL's R.Thomas Strong, Edwin G. Watson, andJohn Tower, and consultants Robert R.Bigler and Samuel Goldfarb.

Schloss awarded PhD

Rober Schloss, ATL, successfully defendedhis dissertation on the semiconductor laser,and received his PhD in Electrical Engi-neering from MIT in February.

Zarodnansky receives BEE

David Zarodnansky, Associate Member,Technical Staff, RCA Laboratories, receivedthe BEE (with honors) from Villanova Univer-sity. He is presently working on the MEE.

Two receive P.E. licenses

Nancy Graves, Consumer Electronics Oper-ations, has received Indiana ProfessionalEngineer's license number 21432.

John P. Larocco, Missile and Surface RadarDivision, has been awarded New JerseyProfessional Engineer's license numberG30681.

New SSD MOSFET handbookavailable

A new handbook from RCA Solid StateDivision, Circuit Ideas for Linear ICs, con-tains 102 practical circuits using one ormore RCA linear ICs and MOSFETS. Eachcircuit is accompanied by a full schematicand a brief functional description.

RCA Engineer 31-1 Jan. / Feb. 198689

The handbook is 34 pages long, and isdivided into nine sections. Included aresections on timing, measurement, modula-tion, power control, data conversion, com-munications, and alarm /monitoring. Formore information, contact Lon Cantor,Tacnet: 325-6423.

Farrey is Engineer of theMonth

William Farrey, Software Engineering, Com-munication and Information Systems Divi-sion, was named Engineer of the Month forAugust in recognition of his contribution tothe development of sophisticated softwarethat is presently being used on the GPCP,Watchmate, and Data Concentrator systems.Mr. Farrey developed IBM PC programsthat allow the user to enter wire lists directlyinto the computer. The Cable Marker pro-gram automatically formats the "to" and"from" information.

Keith recognized by EtaKappa Nu

The 1985 Eta Kappa Nu (Honorary ElectricalEngineering Society) Jury of Award hasselected Michael J. Keith, Member, Tech-nical Staff, RCA Laboratories, for HonorableMention in the award program recognizingoutstanding young electrical engineers. Mr.

Keith is being recognized for "his contribu-tions to the fields of computer -composedmusic and teletext systems, and for hisinvolvement in church and cultural activ-ities." Mark G. Adamiak, a Senior Engineerat American Electric Power Service Corp.,Columbus, Ohio, has been named the win-ner. Two other young electrical engineershave been selected for Honorable Mention:

Harold A Hoeschen, AT&T Bell Laboratories,Holmdel, N.J.

Harvard S. Hinton, AT&T Bell Laboratories,Naperville, III.

Two others are being recognized as finalists.

Mr. Adamiak, Mr. Keith, and the othersreceiving Honorable Mention, includingthose being recognized as finalists, will behonored at the 50th Anniversary AwardBanquet on Monday evening, April 21, 1986,at the Union league, 140 South Broad Street,Philadelphia. Each winner will receive anappropriately inscribed certificate, presentedby the President of Eta Kappa Nu. Mr.Adamiak's name will be engraved on a bowlthat is kept at IEEE Headquarters.

The Award Banquet will include a special50th Anniversary Celebration. All past win-ners and those who had received HonorableMention are being encouraged to attendthe banquet. As part of the event, threepast winners, one from each of three erasof the award (1936-52, 1953-69, and 1970-85) have been invited to address the audi-ence briefly.

Since 1936, Eta Kappa Nu has annuallyrecognized outstanding young electricalengineers. The purpose of this recognitionis to "emphasize among electrical engineersthat their service to mankind is manifestednot only by achievement in purely technicalaffairs, but in a variety of other ways. It

holds that an education based upon theacquisition of technical knowledge and thedevelopment of logical methods of thinkingshould fit the engineer to achieve substantialsuccess in many lines of endeavor."

In the past 50 years, fifty young engineers(including the 1985 winner) who were lessthan 35 years of age, and who had receivedtheir Baccalaureate degree less than 10years before, have received the award, and108 others of similar characteristics havereceived Honorable Mention. The mostrecent RCA employee to be named thewinner is John G.N. Henderson (RCA Lab-oratories), who was selected in 1977. Themost recent employee to receive Honorable

Mention is Robert P. Parker (RCA ConsumerElectronics Operations), who was selectedin 1984.

If you would like further information con-cerning this award program, please refer topage 20 of the July/August 1984 issue ofthe RCA Engineer, or contact Jim D'Arcy,RCA Astro-Electronics Division (Tacnet229-2359). If you have ever been a memberof Eta Kappa Nu, the RCA Technical Excel-lence Center (Princeton) would like to know.Please inform Robin Deal (Tacnet 226-2410)and include your chapter.

RCA contributes to TVhandbook

The most recent edition of the TelevisionEngineering Handbook, edited by K. BlairBenson (McGraw-Hill, New York, 1985, 1478pages) has several RCA authors and con-tributors. It has a Foreword by Donald G.Fink, editor of the first edition (1957), and aPreface by K. Blair Benson. The RCA au-thors and contributors are:

Oded Ben-Dov, Broadcast Systems Division(coauthor, Chapter 8)

A.D. Cope, RCA Laboratories, retired (con-tributor, Chapter 11)

Robert N. Hurst, Broadcast Systems Division(contributor, Chapter 17)Anthony H. Lind, RCA Camden, retired(coauthor, Chapter 17)

Robert G. Neuhauser, Broadcast SystemsDivision (author, Chapter 11)

Krishna Praba, Broadcast Systems Division(coauthor, Chapter 8)

Dalton H. Pritchard, RCA Laboratories(author, Chapter 21).

New AIAA AssociateFellowships

The American Institute of Aeronautics andAstronautics has announced that the follow-ing engineers at Astro-Electronics Divisionhave been upgraded to Associate Fellows:L. Berko, R. Buntschuh, R.J. Cenker, R.deBastos, E.L. Elizondo, S.M. Fox, J.A.Frohbieter, E.R. Ganssle, S.J. Gaston, P.G.Goodwin, J.J. Horan, A.J. Manna, R. Miller,S. Palocz, G.E. Schmidt, Jr., R.D. Scott,J.F. Seliga, J.F. Swale, P.C. Wise, L.P.Yermack, and H. Zelen.

90 RCA Engineer 31-1 Jan. / Feb. 1986

Technical excellence

Third-quarter MSRD winners

Reider

Kadakia

Turowski

The four winners of the third-quarter Missileand Surface Radar Division TechnicalExcellence Awards are as follows:

Carl P. Bannar-for special dedication andcontributions to the integration of the Ele-ment Test Function (ETF) maintenancesystem into the AN/SPY-1B radar. Mr.Bannar personally resolved a number ofcomplex anomalies, enabling the ETF sys-tem to function smoothly with the AN/SPY -1 B signal processor. His effort was amajor factor in the timely and successfultesting of the ETF in the formal NavyAN/SPY-1 B Operation Evaluation.

Sarit Kadakia-for major contributions tothe development and integration of theAN /SPY -1B radar tactical programs, lead-ing to the successful Operational Evalua-tion. Mr. Kadakia's perserverance wasparticularly effective in troubleshooting andproblem isolation in hardware/softwareinterfaces as well as those between com-puter programs. Another key contributionwas his modification of software to enableoperability testing to begin before the avail-ability of the Operational Readiness TestSystem.

Robert L. Reider-for exceptional skill andinitiative in developing an advanced detec-tion algorithm that affords significantlyincreased detection performance againstvery low cross-section targets in the pres-ence of point clutter. By applying a highlyselective approach to multiple -pulse dopp-

ler sequence correlation, Mr. Reider's ap-proach overcomes severe ghosting limita-tions of conventional detection algorithms.Initial tests of the new algorithm indicate asignificant increase in target -handlingcapability.Bernard M. Turowski-for conceptual con-figuration, detailed implementation and testverification, and team leadership in thesuccessful design of the Multiple AlthorithmProgrammable Processor (MAPP). Thispowerful new radar signal processing as-sembly provides programmable processingfunctions at processing speeds of 960 mil-lion operations per second. Mr. Turowski'sleadership of and dedication to this projectover an extended period firmly establishesRCA's leadership position in radar andsignal processing.

Third-quarter CE TECAwards

Pitsch Benson

There were two winners of the third-quarter1985 Consumer Electronics OperationsTechnical Excellence Awards. The winners,announced on December 11, are:

Robert Pitsch-for making a CAV (Di-mensia) compatible satellite receiver in lessthan three weeks to support a corporateannouncement concerning future DBSbusiness. Although the satellite receiverand descrambler that were used were off -the -shelf items, they were not compatible.The units also had to be interfaced to amicrocomputer controller that communi-cated with the front panel controls of thenew package and the Dimensia controlbus. Bob designed the necessary hardwareand software, procured the equipment,wrote the software, and delivered the projecton schedule.Walter Benson-for coordinating the fund-ing, design, and development of a 14 -stationin -line hot stamp system for plastics finish-ing operations on TV cabinet fronts. This

system is the first in the industry and theproject required extensive interaction be-tween vendor and plant personnel. Mr.Benson organized appropriate training andmaintenance programs for both manufac-turing and maintenance personnel. He hasdemonstrated an exceptional degree ofthoroughness and professionalism in everydetail of the project and has been respon-sible for the successful completion of theprogram.

Best is second-quarterwinner at MSRD

William Best has received a TechnicalExcellence Award for outstanding contri-butions to the integration and testing of theEDM-4 Signal Processor. Mr. Best cameto the assignment as a junior team memberwith no previous integration experience,and has become one of the team's mostvalued assets after only 18 months. Ofparticular note are his expertise in micro-processor firmware analysis and his abilityto troubleshoot all modes of the system.

PBG fourth-quarter TECAwardsPalm Beach Gardens presented two fourth-quarter Technical Excellence Team Awards:

C. Hardy and A. Ladick-for the conception,design, and development of a high -temper-ature test apparatus for packaged inte-grated circuits. This resulted in accuratetesting of packaged devices at elevatedtemperatures, reducing characterizationtime and manufacturing costs.P. Chiovarou, H. Foxman, and E. Jordan-for establishing a process and procedureto prepare ion scan glass wafers to monitorion implanters. This resulted in a reducedcycle time for sample preparation at a sub-stantial cost reduction.

Eight at Somerville receive40 TEC AwardsThe Somerville Technical ExcellenceCommittee has announced eight winnersof its fourth-quarter Technical ExcellenceAwards:

Tom Pampalone and Frank Kuyan-fortheir efforts in developing a photo -resist

RCA Engineer 31-1 Jan. / Feb. 1986 91

system that minimizes resist dimensionalvariations over steps in 1.25 -micron designrule circuits. This current generation ofresist has allowed variations of less than±1 micron at gate level,

R. !sham-for developing a "Sparkle TestSystem" addressing the need to quanta-tively define the upper frequency limitswhere any high-speed A/D converterceases to function properly. Besides theability of the system to detect full-scaleerrors, it can also be set for errors as lowas one or two bits.James J. O'Keefe-for developing a veryflexible, operator -friendly control languageprogram that automatically writes an RCAPfile containing the device model parameters,the topology, and command files for singleor multiple 3 -micron standard cells. Al-though developed in conjunction with thesmall ICBM project, it can be applied to allfamilies of standard cells and gate arrays,and may also be expanded to include mul-tiple logic families. Autogate virtually elimi-nates the chances of error in preparingRCAP files for simulations of standard cells.I.E. Martin-for establishing a library ofRCAP model parameters for the 3 -micronRad Hard CMOS/SOS process. This hasenabled the Hi-Rel Design Group to eval-uate the Standard Cell Library for function-ality and propagation delay as a functionof temperature and radiation level and anumber of process variations. Althoughthis work was done in conjunction with thesmall ICBM contract, it can be universallyapplied to the study of any application ofthe Rad Hard CMOS/SOS technology.R. Giordano, M. Low, and M. Hagge-fordeveloping the AIU circuit on the first cut,and in a record time of five months. Due totheir efforts, Consumer Electronics wasable to proceed with an aggressive develop-ment schedule of their next -generationchassis. Due to the fact that this circuitworked on the first cut, it can representsales of $7.5 million over the period 1987to 1991, and it opens the doors to newbusiness with Consumer Electronics andother consumer manufacturers.

SSD third-quarter TEC Awards

Left to right: Carl Turner, Joe Siwinski, Tuan Bui, Carmine Salerno.

Left to right: Carl Turner, Chester Leoszewski, Carmine Salerno.

There were three winners of the Solid StateDivision third-quarter Technical ExcellenceAward:

Tuan Bui and Joseph Siwinski-for design-ing and developing an 8X8 -bit parallel mul-tiplier as the first building block type of aDSP line of devices. The device will be

built in both QMOS and SOS technologies.

Chester Leoszewski-for developing andimplementing a full ac circuit probe testcapability at wafer probe. This method ofcircuit test has led to yield improvementsof from 50 to 90 percent on complex circuits.

92 RCA Engineer 31-1 Jan. / Feb. 1986

Editorial Representativesand Technical Publications Administrators

Contact your Editorial Representative at the Tacnetnumbers listed below to plan your RCA Engineer articleand to announce your professional activities.

Advanced Technology Laboratories*Merle PietzEd Master

TacnetMoorestown, New Jersey 253-6429Moorestown, New Jersey 253-6436

Aerospace & Defense Staff*Theresa Law

(Approvals only)

American Communications*Anita Labib

(Approvals only)Carolyn Powell

Astro-Electronics Division*Frank YannottiCarol Coleman

Cherry Hill, New Jersey 222-5833

Princeton, New Jersey 258-4346

Princeton, New Jersey 272-4194

Princeton, New Jersey 229-2544Princeton, New Jersey 229-2919

Automated Systems Division*Gene Galton Burlington. Massachusetts

Linda Kriesman Burlington, Massachusetts326-3775326-3001

Communication and Information Systems Division*Dan Tannenbaum

Harry GreenBruce White

Camden, New JerseyCamden, New JerseyCamden, New Jersey

Consumer Electronics Operations*Eugene JansonJohn HopkinsLarry Olson

Indianapolis, IndianaIndianapolis, IndianaIndianapolis, Indiana

222-3081222-2423222-3908

422-5208422-5217422-5117

Corporate Information Systems & Services*Sue Handman Cherry Hill, New Jersey 222-6242

Global Communications*Dorothy Unger Piscataway, New Jersey 335-4358

Microelectronics Center*Susan Suchy Somerville, New Jersey 325-7492

Missile and Surface Radar Division*Don HiggsGraham BooseJack Friedman

Moorestown, New JerseyMoorestown, New JerseyMoorestown, New Jersey

224-2836253-6062224-2112

National Broadcasting Company*Bob Mausler New York, New York 324-4869

Feb 3,1986

*Technical Publications Administrators, responsiblefor review and approval of papers and presentations,are indicated here with asterisks before their names.

Network Services*Bill Brown

New Products Division*P.G. BedrosianBob McIntyre

Patent OperationsGeorge Haas

RCA CylixPaul Dixon

RCA Laboratories*Julie Dann

(Approvals only)Eva Dukes

TacnetPrinceton, New Jersey 272-7601

Lancaster, Pennsylvania 227-6880Ste Anne de Bellevue 514-457-9000

Princeton, New Jersey 226-2888

Memphis, Tenn. 739-0214

Princeton, New Jersey 226-2061

Princeton, New Jersey 226-2882

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