A New Control Strategy of Z-Source NPC Inverter using ...iret.co.in/Docs/IJETEE/Volume 10/Issue9/21. A New Control Strategy... · Power quality improvement S.Venkatesh1, Dr.G.Jayakrishna2

S.Venkatesh1, Dr.G.Jayakrishna2

International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 10, Issue. 9, Oct. 2014

A New Control Strategy of Z-Source NPCInverter using Space vector Modulation for

Power quality improvementS.Venkatesh1, Dr.G.Jayakrishna2

PG Scholar, Dep of EEE, NEC, Gudur, Andhra Pradesh, IndiaProf, Head, Dep of EEE, NEC, Gudur, A.P., India.

Abstract— Power electronic circuit is a circuit thatconverts direct power to alternative power. Inverters areused to supply AC power from DC sources such as solarpanels or batteries. It is widely used in industries due itsrobustness and ruggedness for high power applicationsand industrial high power conversion systems both forutility and drive applications .The Z-source inverter is arelatively recent converter topology that exhibits bothvoltage - buck and voltage - boost capability. The Z-source concept can be applied to all dc-to-ac, ac-to-dc, ac-to-ac, and dc-to-dc power conversion whether two-level ormultilevel. Previous publications have shown the controlof a Z-source neutral point clamped inverter using thecarrier-based modulation technique. Z-source inverterbased adjustable speed drive system (ASD) effectively usesthe shoot-through state to boost DC bus voltage bysimultaneously gating on both the upper and lowerswitches of a same phase leg. The shoot-through zerostate has no harmful effect on the inverter and is used toboost the DC link voltage. In this thesis, modeling andsimulation of modified SVPWM Z-source three levelneutral point clamped fed three phase induction motordrive is presented. The drive system is modeled using theblocks of simulink and the harmonic performance isverified. This Thesis presents the control of a Z-source neutral point clamped inverter using the spacevector modulation technique. This gives a number ofbenefits, both in terms of implementation and harmonicperformance. The adopted approach enables theoperation of the Z-source arrangement to be optimizedand implemented digitally without introducing any extracommutations. The proposed techniques are simulatedusing MATLAB/SIMULINK & the results are presented.The results shown that the improved harmonicperformance of the ULST over the FST strategy andalso this simulation results shown that the Z-source NPCinverter with space vector modulated algorithm is able toboost the output line to line voltage to a value higher thanthe available dc supply voltage with enhanced sinusoidaloutput current waveforms.

Index Terms — Buck–boost, neutral point clampedinverter, space vector modulation (SVM), InductionMotor, Z-source inverter.

I. INTRODUCTION

MANY industrial applications require higher

power converters (inverters) which are now almostexclusively implemented using one of the multileveltypes. Multilevel converters offer many benefits forhigher power applications which include an ability tosynthesize voltage waveforms with lower harmoniccontent than two-level converters and operation athigher dc voltages using series connection of a basicswitching cell of one type or another [1]–[4].

Even though many different multilevel topologieshave been proposed, the three most commontopologies are the cascaded inverter [5]–[7], thediode clamped inverter [8]–[12], and the capacitorclamped inverter [13]–[15]. Among the three, thethree-level diode clamped [also known as the neutralpoint clamped (NPC)] inverter has become anestablished topology in medium voltage drives and isarguably the most popular [16]–[19], certainly forthree-level circuits. However, the NPC inverter isconstrained by its inability to produce an output line-to-line voltage greater than the dc source voltage.For applications where the dc source is not alwaysconstant, such as a fuel cell [20], [21],photovoltaic array [22], and during voltage sags, etc.,a dc/dc boost converter is often needed to boost thedc voltage to meetthe required output voltage or to allow the nominaloperating point to be favorably located [23], [24].This increases the systemcomplexity and is desirable to eliminate if possible.

The main function of a multilevel inverter is toproduce a desired AC voltage level from several DCvoltage sources. ThisDC voltage source may or may not be equal to oneanother. The AC voltage produced from this DCvoltage appears to be a sinusoidal. One pitfall ofusing multilevel inverter is to approximate sinusoidalwaveforms concern with harmonics. The staircasewaveform produced by a multilevel inverter containssharp transitions. The harmonics which aregenerated, in addition to the fundamental frequencyof the sinusoidal waveform are analyzed using theFourier Series Theory. The harmonics generated onthe AC side greatly influence the power quality of the



control system. The multilevel inverter improves theAC power quality by performing the powerconversion in small voltage steps leading to lowerharmonics. For this reason, researchers are doingconsiderable work on multilevel inverter in recentyears.

The Z-source inverter [25] topology was proposedto over-come the above limitations in traditionalinverters. The Z-source concept can be applied to alldc-to-ac [26], ac-to-dc [27], ac-to-ac [28]–[31], anddc-to-dc [32], [33] power conversion whether two-level or multilevel. The Z-source concept wasextended to the NPC inverter in [34], where twoadditional Z-source net-works were connectedbetween two isolated dc sources and a traditionalNPC inverter. In spite of its effectiveness in achiev-ing voltage buck–boost conversion, the Z-sourceNPC inverter proposed in [34] is expensive because ituses two Z-source networks, two isolated dc sources,and requires a complex mod-ulator for balancing theboosting of each Z-source network. To overcome thecost and modulator complexity issues, the design andcontrol of an NPC inverter using a single Z-sourcenetwork was presented in [35]. The operationalanalysis and optimal con-trol of the reduced elementcount (REC) Z-source NPC inverter wassubsequently described in [36].

The REC Z-source NPC inverter is expected tofind appli-cations in grid connected distributedgeneration (DG) systems based on renewable energysources such as photovoltaic sys-tems, wind turbines,and fuel cell stacks [37]. Two DG systems can beconnected to the grid with only one REC Z-sourceNPC inverter , thus reducing the volume and costwhile increasing theefficiency and facilitating control. The power qualityof current injected to the grid is improved because ofthe three-level struc-ture. It can also find use inadjustable speed drive systems in applications such asconveyor belts, fans, and water pumps [38].

In [36], the modulation of the REC Z-source NPCinverter was described using the carrier-basedapproach. However, the space vector modulation(SVM) approach offers better harmonic per-formance[11] (compared with carrier-based pulse width modu-lation (PWM) strategy without zero-sequence voltageinjection) and can more conveniently handle overallswitching patterns and constraints [39], [40], and it issimple to implement using a DSP

[41]. The contribution of this paper is, therefore,the development of a modified SVM algorithm forcontrolling theREC Z-source NPC inverter. The theoretical

development is discussed in detail, and simulations aswell as experimental results are used to verify theoperation of the circuit and proposed SVM-basedmodulation.

Application of ASDs in commercial and industrialsectors is increasing due to their improved efficiency,energy savings, and effective control. There are twotraditional power inverter topologies surviving forinduction motor drive applications: voltage sourceinverter (VSI) and current source inverter (CSI).

In these inverters, a DC voltage/current sourcesupported by a relatively large capacitor/inductorfeeds the main three phase bridge inverter circuit.The DC voltage source could be a battery or outputof a front end rectifier circuit connected with theutility AC supply or a capacitor. Six switches areused in the main circuit; each is traditionallycomposed of a power insulated gate bipolar junctiontransistor (IGBT) and an anti parallel (or feedback)diode to provide bidirectional current flow andunidirectional voltage blocking capability. Z-sourceinverter (ZSI) is a direct current (DC) to alternatingcurrent (AC) power conversion concept that is verypromising in the areas of power conditioningespecially in alternative energy sources, adjustablespeed drives (ASD) and distributed generation.

II. REVIEW OF Z-SOURCE CONCEPT

The topology of a two-level Z-source inverter isshown in Fig. 1. The only difference between the Z-source inverter and a traditional voltage sourceinverter (VSI) is the presence of a Z-source networkcomprising a split-inductor (L1 and L2 ) and twocapacitors (C1 and C2 ). The unique feature of thetwo-level Z-source inverter is that the output acvoltage fundamental can be controlled to be anyvalue between zero and (theoretically) infinityregardless of the dc source voltage. Thus, the Z-source inverter is a buck–boost inverter that has avery wide range of obtainable output voltage.Traditional VSIs cannot provide such features.In Fig. 1, the two-level Z-source inverter bridge has15 permis-sible switching states unlike the traditionaltwo-level VSI that has 8. The traditional three-phaseVSI has six active states when the dc voltage isimpressed across the load and two zero states whenthe load terminals are shorted through either thelower or upper three devices, respectively. However,the two-level Z-source inverter bridge has seven extrazero states (termed shoot-through states) when theload terminals are shorted through both upper andlower devices of any one phase leg (i.e., both devicesare gated ON), any two phase legs, or all three phaselegs. These shoot-through states are forbidden in atraditional VSI for obvious reasons. The Z-source



network makes the shoot-through zero states possibleand provides the means by which boosting operationcan be obtained. Critically, any of the shoot-throughstates can be substituted for normal zero stateswithout affecting the PWM pattern seen by the load.Therefore, for a fixed switching cycle, insertion ofshoot-through states within the zero intervals with theactive state intervals maintained constant will notalter the normalized volt– second average perswitching cycle seen by the ac load. Instead, with theshoot-through states inserted, the effective inverter dclink voltage Vi can be stepped up as given in (1) [25],[42]. Consequently, taking also the PWM modulationindex M into account, the phase ac output voltage Vxcan be expressed by (2)V = ( / ) = B. E (1)V = .√ = B ME/√3 (2)

where TST and T are the shoot-through interval andswitching period, respectively, B is the boost factorand the term in paren-thesis represents the phase acoutput voltage of a traditional VSI.

Equations (1) and (2) show that the acoutput voltage of a Z-source inverter can be regulatedfrom zero to the nor-mal maximum by altering M andmaintaining B = 1, or can be boosted above thatobtainable with a traditional VSI by choosing B > 1.A similar analysis can be carried out for the current-type Z-source inverter [43]. However, since the focusof this paper is that of the voltage-type Z-sourceinverter, the analysis for the current-type Z-sourceinverter would not be discussed further due to spacelimitation.

III. TOPOLOGY OF REC Z-SOURCE NPCINVERTER

A. Extension of the Z-Source Concept to the NPCInverter

To describe the operating principle of the REC Z-source NPC inverter shown in Fig. 2, we concentrateinitially on the operation of one phase leg. The

operation of each inverter phase leg of a traditionalNPC inverter can be represented by three switchingstates P, O, and N. Switching state “P” denotes thatthe upper two switches in a phase leg are gated ON,“N” indicates that the lower two switches conduct,and “O” signifies that the inner two switches aregated ON.

However, each phase leg of the Z-source NPCinverter has three extra switching states whichresemble the “O” state of the traditional NPCinverter. These extra switching states occur when allthe four switches in any phase leg are gated ON [full-shoot-through (FST)], or the three upper switches inany phase leg are gated ON [upper-shoot-through(UST)] or the three bottom switches in any phase legare gated ON [lower-shoot-through (LST)].

TABLE ISWITCHING STATES OF AN REC Z-SOURCENPC INVERTER

Statetype

ONswitches

ONDiodes

Vxo Switchingstate

NST Qx1,Qx2 D1,D2 +Vi/2 P

NST Qx2,Qx’1 D1,D2,{Dx1orDx2}

0 O

NST Qx’1,Qx’2 D1,D2 −Vi/2 N

FST Qx1,Qx2,Qx’1,Qx’2

— 0 FST

UST Qx1,Qx2,Qx’1

Dx2,D1

0 UST

LST Qx2,Qx’1,Qx’2

Dx1,D2

0 LST

These shoot-through states are forbidden in thetraditional NPC inverter because they would cause ashort circuit of the dc-side capacitors. Again, the Z-source network makes these shoot-through statespermissible and provides the means for boostoperation.

B. Circuit Analysis

Among the three-level Z-source power convertertopologies reported to date, the Z-source NPCinverter implemented using a single LC impedancenetwork (see Fig. 2) is considered to be an optimized



topology in terms of component count [44], [45].

Referring to Fig. 2, the REC Z-source NPCinverter is supplied with a split dc source. The middlepoint O is taken as a reference. By controlling theswitches of each phase leg according to thecombinations presented in Table I, each output phasevoltage Vxo(x_{a, b, c}) has three possibilities: Vi /2, 0, and −Vi/2.When the REC Z-source NPC inverter is operatedwithout

any shoot-through states, then Vi is equivalent to 2E.As noted earlier, with this kind of operation, themaximum obtainable output line-to-line voltagecannot exceed the available dc source voltage (2E).Therefore, to obtain an output line-to-line voltagegreater than 2E, shoot-through states are carefullyinserted into selected phase legs to boost the inputvoltage to Vi > 2E before it is inverted by the NPCcircuitry. Thus, the REC Z-source inverter can boostand buck the output line-to-line voltage with a single-stage structure.

In [36], two new switching states namely the USTand LST states were identified, in addition to the FSTstate and the non-shoot-through (NST) states (P, O,and N) that had been reported earlier in [35].Although operation using the FST and NST statesis possible (termed the FST operating mode), it isgenerally preferable to use the UST and LST states inplace of the FST states (termed the ULST operatingmode). The ULST operating mode is preferredbecause it produces an output voltage with enhancedwaveform quality.

The simplest FST operating mode requires all fourswitches in a phase leg (see Table I) to be turned ON.This is not a minimal loss approach since, forexample, switching phase A from +Ethrough FST to 0 V would require switches {Qa1,

Qa2, Qa’1, Qa’2} changing from {ON,ON, OFF, OFF} through {ON, ON, ON, ON} to{OFF, ON, ON, OFF}. An alternative FST operatingmode which gives minimal loss uses two phase legsto create the shoot-through path. This requires, forexample, synchronization of the turn ON instants ofswitches Qa1 from phase A and Qc’2 from phase Cat the start of an FST state. Doing so creates a timeinterval during which switches {Qa1, Qa2, Qa’1}from phase A and {Qc2, Qc’1, Qc’2} from phase Care gated ON simultaneously to create a shoot-through path [35].

However, the output line-to-line voltage obtainedusing the minimal loss FST approach has higherharmonic distortion (compared to the ULSTapproach) in its output voltage wave-form becausethe voltage levels produced do not have adjacentlevel switching [35]. Therefore, in this paper, theULST op erating mode is used for controlling theREC Z-source NPC inverter. Fig. 3(a) shows thesimplified equivalent circuit for the NST state, whileFig. 3(b) and (c) shows the UST and LST states. Notethat there are multiple ways of creating the UST andLST states using different phases. The choicebetween these is discussed later. Assuming that theZ-source network is symmet-rical (L1 = L2 = L and C1 = C2 = C), then VL 1 = VL 2= VL and VC 1 = VC 2 = VC and the voltageexpressions for the NSTstate are as follows:NSTV = 2E − V (3)V = + , V = (4)V = 2(V − E) (5)

Similarly, the voltage expressions for the UST andLST states are as follows:

UST V = E (6)V = 0 V , V = E − V . (7)

LSTV = E (8)V = −E + V , V = 0 V. (9)

We denote the duration of the NST, UST, and LSTstates by TN , TU , and TL , respectively, and theswitching period by T . Also, we assume that TU andTL are equal (this is necessary to ensure symmetrical



operation) and denote the total combined UST andLST duration by TU LST . At steady state, the averagevoltage across the inductors is zero; therefore,averaging the inductor voltage over one switchingperiod, we have

( ). . . = 0 (10)+ + = (11)

Solving for Vc using (10) and (11), we have

= (2 ). (12)

Substituting (12) in to (5),we have the dc-link voltageVi during the NST state as= / (13)

Similarly, when (12) is substituted into (7) and (9)and noting that Vi = VP − VN , we have the dc-linkvoltage during the UST and LST states as

V = V = (14)

It is noted from (13) and (14) that the higher dc-link voltage is present during the NST states and it istwice the dc-link volt-age available during the USTand LST states, as required. The fundamental peak acoutput voltage Vxo (x_{a, b, c}) is given by

= √ . _ (15)= √ (2 ) = ′ √ (2 ) (16)

Fig.3 (a). Simplified representation of REC Z-

source NPCinverter in Non shoot through state

Fig.3 (b). Simplified representation of REC Z-source NPC

inverter in Upper shoot through state

Fig. 3(c). Simplified representation of REC Z-source NPC

Lower shoot through states

where B ≥ 1 is the boost factor [44] and all the other symbols

IV. MODIFIED SVM OF THE REC Z-SOURCE NPCINVERTER

A. Duty Cycle Calculation

The space vector diagram of a traditional NPC inverter for



sector 1 is shown in Fig. 4. The reference vector Vref can beexpressed as

( ) = [ ( ). + ( ). + ( ). ] (17)Generally, in SVM, the reference vector Vref is synthesizedwith three nearest space vectors, which are selected based onthe triangle in which the reference vector is located at thesampling instant. If the reference vector is located in triangle3, the nearestthree vectors are V1 , V7 , andV13, respectively. Let the dutyratios of these vectors be denoted by d1 , d2 , and d3 ,respectively.

The modulation law with a sequence of the nearest threevectors based on the volt–second product is then as follows:. + . + . =

d1+d2+d3 = 1. (18)The voltage vectors V1 , V7 , V13, and Vref in Fig. 4can be expressed as V = 13 . (2E)V = √33 . e π/ . (2E)V = 23 . (2E)V = V . e θ. (19)

Substituting (19) into (18), the duty ratios of thenearest three voltage vectors are given by (20), whereM is the modulation index and 0 ≤ θ ≤ π/3= 2 − 2 sin(3 + )= 2 sin= 2 sin + − 1. (20)A similar procedure is used for calculating the dutyratios of the selected voltage vectors in all the othertriangles. To complete the modulation process, theselected voltage vectors are applied to the outputaccording to a switching sequence. Ideally, aswitching sequence is formed in such away that ahigh quality output waveform is obtained withminimum number of switching transitions [46].

B. Switching Sequence and Insertion of Shoot-Through States

To achieve the minimal number of switches changingbetween two adjacent states, a seven-segmentswitching sequence is adopted in SVM. If thereference vector stays in triangle 3 (see Fig. 4), andusing the decomposition method, where the null state

is shifted from {PPP/OOO/NNN} to {POO/ONN},the

Equivalent Null (E-Null) states areV1{POO} and V1{ONN}, while the EquivalentActive (E-Active) states are V7{PON} andV13{PNN}, respectively. The seven-segmentswitching sequence in triangle 3 can then be brieflyillustrated as shown in Table II [46]. In a traditionalthree-level NPC inverter, only switching transitionsbetween the “P” state and the “O” state or the “N”state and the “O” state are permitted. Switchingdirectly between the “P” state and the “N” state is notallowed because it results in all four switcheschanging state, which results in nonequal dynamicvoltage and double the switching loss.

TABLE IISEVEN SEGMENT SWITCHING SEQUENCE INTRIANGLE 3

Segment Vector StateE-Null 1 1st V1 ONNE-Active1

2nd V13 PNN

E-Active2

3rd V7 PON

E-Null 2 4th V1 POOE-Active2

5th V7 PON

E-Active1

6th V13 PNN

E-Null 1 7th V1 ONN

TABLE IIIPERMISSIBLE UST AND LST STATES

Upper Shoot Throughstates

Lower ShootThrough states

UNN PLOUON POLOUN PPLNUN LPONUO OPLNOU LPPNNU LOPUNO OLPONU PLP



In order to introduce shoot-through states, itis necessary to determine where the UST and LSTstates can be inserted, and on which phase, in orderthat the normalized volt–second area applied to theload is unchanged from the standard NPC casediscussed above. In addition, it is desirable to ensurethat no extra commutations are introduced.Theoretically, a shoot-through state can be introducedon any phase which is switched to the zero level (O)without affecting that phase voltage. However, theeffect on the line-to-line voltages must also be takeninto account. Note that when any phase has USTapplied, the positive rail (P) is at the same potentialas the dc mid-point (O). Similarly, during LST, thenegative rail (N) is at the same potential as the dcmid-point (O). Consequently, it is only possible touse the UST state on a given phase when it isconnected to O and the other two phases areconnected either to O or N in order to get the correctline-to-line voltages. Similarly, an LST state can onlybe used when the other two phases are O or P.Therefore, the permissible shoot-through states are asshown in Table III where “U” and “L” represent USTand LST states in a phase leg, respectively.

Taking the above into account, theobjective is to deploy the UST/LST states for voltageboosting in an optimal way that does not increase thenumber of commutations. A modified PWMsequence which achieves this can be derived asdiscussed below. Fig. 5(a) shows the seven-segmentPWM

switching sequences for modulating atraditional NPC inverter and an REC Z-source NPCinverter when the reference vector, Vref is in triangle3 of the vector diagram shown in Fig. 4.

FIG . 5(a) Modulation of traditional NPC and Z-source NPC when the reference vector is in triangle3on the three level vector diagram shown in Fig.4.

FIG .5(b) Modulation of traditional NPC and Z-source NPC when the reference vector is in triangle(4) on the three level vector diagram shown in Fig.4.

Comparing the sequences shown in Fig.5(a), it is observed that the only difference betweenthem is the insertion of a UST state in phase A to theleft of the E-active state {PNN} and the insertion ofan LST state in phase C to the right of the E-activestate {PON}, respectively, within half switchingperiod, T/2. Insertion of shoot-through states at theseinstants will not result in additional switching since,for example, the transition from {ONN} to {PNN}can be achieved by switching devices{Qa1,Qa2,Qa_1,Qa_2} from {OFF, ON, ON,OFF}through {ON, ON, ON, OFF} to {ON, ON,OFF, OFF} [47]. The process is reversed in theremaining half switching period. The phase A voltageduring the UST state is the same as that of the “O”state because during the UST state, the voltage E isdropped across inductor L1 and the voltage seen byphase leg A is 0 V [see Fig. 3(b)]. Hence, the {UNN}and {ONN} states can supplement each other forvoltage boosting without modifying the line-to-linevolt–second average (normalized by taking the boostfactor into account).Applying the same analysis and moving on to thesecond transition ({PNN} to {PON}), where phase Bswitches from the “N” state to the “O” state, noshoot-through state is inserted (note that it is notpossible to introduce UST or LST for the {PON}state for the reasons discussed earlier).Movingforward again to the third transition ({PON} to{POO}) where phase C switches from the “N” stateto the “O” state, an LST state is inserted since theswitching of devices {Qc1,Qc2,Qc_1,Qc_2} from{OFF, OFF, ON, ON} through {OFF, ON, ON, ON}to {OFF, ON, ON, OFF} will not affect phases A andB, which remain clamped to points P and O. Thephase C voltage during the LST state is equal to thatof the “O” state since the voltage E is dropped acrossinductor L2 and the voltage seen by phase C is 0 V[see Fig. 3(c)].TABLE IVSWITCHING SEQUENCES AND INSERTION OFSHOOT –THROUGH STATES IN TRIANGLES 2-4

Trian-gle

SwitchingSequence

2a {ONN}→{UNN}→{ONN}→{PON}→{POL}→{POO}

2b {PPO}→{PPL}→{POO}→{PON}→{UON}―›{OON}

3 {ONN}→{UNN}→{PNN}→{PON}→{POL}→{POO}

4 {OON}→{UON}→{PON}→{PPN}→{PPL} →{PPO}



When the previous methodology is applied to anotherdistinct triangle, triangle 2a, a similar state sequenceis derived and shown in Fig. 5(b). It is noted thatalthough it is possible to insert a UST state at the({OON} to {PON}) transition, no shoot-though stateis inserted at this transition since doing so will resultin an inferior output voltage. From the above, it isnoted that in all triangles, the UST (or LST) states areinserted at the “E-Null” to “E-Active” statetransitions with no shoot through states inserted at the“E-Active” to “E-Active” state transitions.

It is also noted that the shoot-through statesdo not affect the PWM control of the inverter,because they equivalently produce the same zerovoltage at the load terminals. Another feature notedwith the ULST modulation scheme is that the USTand LST states are introduced for only half of thetotal shoot-through duration of TULST, unlike the FSTmodulation scheme, where the Z-source network isshorted for the full shoot-through duration.Therefore, to produce the same boost factor for theULST and FST schemes, we need to set TULST/T =2TFST/T , where TFST is the FST duration. Theavailable shoot-through period is limited by the E-null period that is determined by the modulationindex according to (21) for the simple boost controlmethod [34], [44]= = = = 1 − .(21)Table IV gives a summary of the above discussionswhen the reference vector is in the various trianglesof sector 1. A similar situation happens in sectors 2–6. However, it should be noted that in triangle 1, noshoot-through states are inserted because thiscorresponds to a low modulation index which causesthe inverter to degenerate into three-level line-to-linevoltage switching with no additional voltage boostproduced [34].

V. SIMULATION RESULTS

To verify the proposed approach, simulations werefirst carried out for the proposed SVM-basedmodulation algorithm using an REC Z-source NPCinverter.

In this simulation platform, a standalonethree-phase induction motor was used to verify thetheoretical findings. To demonstrate the boostingability of the REC Z-source NPC inverter, first, amodulation index, M of 0.825. The spectrum of theoutput line-to-line voltage, the output line-to-linevoltage, line currents, Z-source capacitor voltage, andthe dc-link voltage seen at the input of the NPC

circuitry. The inverter dc-link voltage is obviouslynot boosted and the peak value of the output line-to-line voltage is maintained at almost 400V by the dcsource. The spectrum of the output line to linevoltage shows a peak fundamental component of 80V, corresponding to a phase voltage of 47 V which isthe expected value according to (16). High-qualitysinusoidal line currents are also observed. Thevoltage across the Z-source capacitors (VC1, VC2 =VC) is clearly maintained at almost 120 V since noboosting is commanded. Similarly, the dc-linkvoltage seen by the NPC circuitry, Vi is maintainedat around 120 V.

TABLE VCOMPARISON OF ULST AND FSTSTRATEGIES

Parameters FSTStrategy

ULSTStrategy

Total harmonicdistortion

29.27% 28.39%

Commutationcount

4 2

Switching loss High Low

The simulation results show that the RECZ-source NPC inverter, with the proposed SVMalgorithm, is able to boost the output line-to-linevoltage to a value higher than the available dc supplyvoltage with sinusoidal output currents.

To show the improved harmonic performance ofthe ULST strategy over the FST strategy, simulationsusing the FST strategy were also carried out with thesame parameters as those of the ULST strategy(except that TFST/T = 0.175 = 0.35/2) and the resultsshown in Fig.7.2 and Fig.7.3. Table V gives acomparison of the performances of the ULSTstrategy, non minimal loss FST, and the minimal lossFST strategies. Also, to show that the UST and LSTstates do not introduce any significant harmonicdistortion to the output line-to-line voltage, the samedc-link voltage was used for the non boost mode (i.e.,2E = 120 V, TULST/T = 0) and the boost mode (2E= 120/1.53 V, TULST/T = 0.35) and their harmonicperformances compared as shown in Fig. 9



Fig.6.1.Simulink model for Carrier UST basedInduction Motor.

Fig.6.2(a) Three Phase Voltages Vab,Vbc,Vca &phase to neutral voltage Van

Fig.6.2(b) Three Phase Currents (Iabc)

Fig.6.2(c) Voltage THD in %Fig.6.2 Simulated waveforms of REC Z-source NPCinverter using Carrier UST strategy.

Fig.7.1.Simulink model for FST based InductionMotor.

Fig.7.2(a) Three Phase Voltages Vab,Vbc,Vca &phase to neutral voltage Van



Fig.7.2(b) Three Phase Currents(Iabc)

Fig 7.2(c) Voltage THD in %

Fig.7.2 Simulated waveforms of REC Z-source NPCinverter using Carrier UST strategy.

Fig.8.1 Simulink model for ULST based InductionMotor

Fig.8.2(a) Three Phase Voltages Vab,Vbc,Vca &phaseto neutral voltage Van

Fig.8.2(b) Three Phase Currents (Iabc)

Fig.8.2(c) Voltage THD in %

Fig.8.2 Simulated waveforms of REC Z-source NPCinverter using Carrier UST strategy.

Finally, the simulation results of the carrier-based PWM described in [36] using the sameparameters as those of the proposed SVM strategyand the total harmonic distortion (THD) of theoutput line-to-line voltage is compared to that of theproposed SVM strategy in Table VI.



TABLE VICOMPARISON OF THD OF THE PROPOSEDSVM AND CARRIER-BASED PWM WITH ZERO-SEQUENCE VOLTAGE INJECTION.

Mode Proposed SVM Optimisedcarrier-basedPWM

Non boostMode

49.54% 37.47%

ULST Mode 28.39% 36.81%

From Table VI, it can be concluded that the harmonicperformance of the proposed SVM strategy iscomparable to the carrier-based PWM with zero-sequence voltage injection strategy described in [36]and hence is a competitive alternative for modulatingthe Z-source NPC inverter.

VI. CONCLUSION

In this paper, the simulation of Threelevel multilevel inverter is carried out in MATLAB/Simulink, to identify the suitable level inverter whichhas comparatively less total harmonic distortion in itsoutput. The total harmonic performance of ULST andFST strategies with the same dc-link voltage. Acomparative study is done for better configuration ofmultilevel inverter. A modified SVM for an REC Z-source NPC inverter is presented. The insertion of theshoot through states was such that the number ofdevice commutations was kept at a minimum of sixper sampling period, similar to that needed by atraditional NPC inverter.

The Z-Source multilevel inverters aremainly used as drive for induction motors,STATCOM, shunt active power filters, aero spaceand solar powered applications. Application ofSVPWM technique, incorporating Neuro-Fuzzycontroller for performance improvement in closedloop control and hardware implementation of closedloop control are some of the important future scopeof the present work.

REFERENCES[1] S. Busquets-Monge, J. Rocabert, P. Rodriguez, S.Alepuz, and J. Bordonau, “Multilevel diode-clampedconverter for photo voltaic generators withindependent voltage control of each solar array,”IEEE Trans. Ind. Electron., vol. 55 , no. 7, pp.2713–2723, Jul. 2008.[2] J. Zhao, Y. Han, X. He, C. Tan, J. Cheng,and R. Zhao, “Multilevel circuit topologies based onthe switched-capacitor and diode-clampedconverter,” IEEE Trans. Power Electron., vol. 26,no. 8, pp. 2127–2136, Aug. 2011.

[3] J.-S. Hu, K.-Y. Chen, T.-Y. Shen, and C.-H.Tang,“Analytical solutions of multilevel space -vector PWM for multiphase voltage sourceinverters, ”IEEE Trans. Power Electron., vol.

26, no. 5, pp. 1489–1502, May 2011.[4] Z. Zhao, Y. Zhong , H. Gao , L. Yuan , and T.Lu, “Hybrid selective harmonic elimination PWMfor common-mode voltage reduction in three levelneutral - point clamped inverters for variable speedinduction drives, ” IEEE Trans. Power Electron., vol.27, no. 3, pp. 1152–1158, Mar. 2012.[5] P. Sun, C. Liu, J.-S. Lai, and C.-L. Chen,“Cascade dual buck inverter with phase - shiftcontrol , ” IEEE Trans. Power Electron., vol. 27,no. 4, pp. 2067–2077, Apr. 2012.[6] J. Ebrahimi, E. Babaei, and G.Gharehpetian,“Anew topology of cascaded multilevel converterswith reduced number of components for high -voltage applications , ” IEEE Trans. PowerElectron., vol. 26, no. 11, pp. 3109–3118, Nov. 2011.[7] C. Govinda raju and K. Baskaran , “ Efficientsequential switching hybrid modulationtechniques for cascaded multilevel inverters,”IEEE Trans.Power Electron., vol. 26, no. 6, pp.1639–1648, Jun. 2011.[8] J. Shen, S. Schroeder, R. Roesner, and S. El-Barbari, “A comprehensive study of neutral-pointself-balancing effect in neutral – point -clampedthree level inverters , ” IEE Trans.PowerElectron., vol. 26, no. 11, pp. 3084– 3095, Nov.2011.

S.Venkatesh received B.tech(EEE) From jntu , anantapur in the year (2007-2011).Presently doing M.tech (Power Electronics) inNarayana Engineering College , Gudur , A.P , India(2012 – 2014 ) batch.

G.Jayakrishnareceived B.Tech,M.Tech and Ph.Ddegrees in ElectricalEngineering fromJawaharlal Nehru

Technological University, Anantapur,India in 1993,2004 and 2013respectively. Currently he is workingas professor & Head of Department ofElectrical and ElectronicsEngineering, Narayana Engineering





Non boostMode

49.54% 37.47%

ULST Mode 28.39% 36.81%


VI. CONCLUSION













Non boostMode

49.54% 37.47%

ULST Mode 28.39% 36.81%


VI. CONCLUSION











College, Gudur,A.P, India. Hisresearch interests include PowerQuality, Electrical drives and PowerSystems. He is life member of ISTE.

Documents

A New Control Strategy of Z-Source NPC Inverter using ...iret.co.in/Docs/IJETEE/Volume 10/Issue9/21. A New Control Strategy... · Power quality improvement S.Venkatesh1, Dr.G.Jayakrishna2