A Multi-Standard ADC for Cellular and WLAN in 65nm CMOSssenn.de/files/master_thesis_pres.pdf · A Multi-Standard ADC for Cellular and WLAN in 65nm CMOS Master Thesis of Tomislav Cvetic

A Multi-Standard ADC for Cellular andWLAN in 65nm CMOS

Master Thesis of Tomislav Cvetic and Stephan SennAdvisors: Thomas Christen and Craig Keogh

Professor: Prof. Dr. Qiuting Huang

Integrated Systems LaboratoryETH Zurich

1 Introduction

2 System Design

3 Circuit Design

4 Results

5 Conclusion and Outlook

Integrated Systems Laboratory 2 / 19 Department of Information Technologyand Electrical Engineering Zurich

1 Introduction

2 System Design

3 Circuit Design

4 Results



Overview: Σ∆-Modulator in a Receiver System

WLAN IEEE 802.11a/b/g

WLAN IEEE 802.11n

UMTS

GSM-EDGE

Reconfigurable Σ∆-Modulator

No dedicated Σ∆-modulator for eachstandard

The same performance as for asingle-standard Σ∆-modulator

Main problems: wide range of bandwidthsand resolutions for all standards, lowvoltage operation, high input stable range

Σ∆-

Modulator

Decimation

Filter

Σ∆-ADC

Receiver System:

Low-NoiseAmplifier (LNA)


Specification

GSM-EDGE

fb : 100kHz

fs : 13MHz

DR : 88dB

OSR : 130

UMTS

fb : 1.92MHz

fs : 30.72MHz

DR : 79dB

OSR : 16

WLAN IEEE 802.11a/b/g

fb : 10MHz

fs : 240MHz

DR : 71dB

OSR : 12

WLAN IEEE 802.11n

fb : 20MHz

fs : 320MHz

DR : 64dB

OSR : 8


1 Introduction

2 System Design

3 Circuit Design

4 Results



System Design

Architecture-Overview

One resonator, controlling zeros

Integrator feed-forward paths, controlling poles

4

6

1

6z−1

1−z−1

+z−11

1−z−1

G

2

5z−1

1−z−1

3

4+

z−1

1−z−1

7

8+

1

4

−

X(z)

4

−

Y (z)

4

6

4

6


Effects of Pole/Zero-Placements

log (ω)

‖N

TF‖

ωBW

Im

Re

ejω

Input Stability [%FS]

100%0%

[dB]

[rad/s]



Im

Re

ejω


100%0%

log (ω)

‖N

TF‖

ωBW

[dB]

[rad/s]



Im

Re

ejω


100%0%

log (ω)

‖N

TF‖

ωBW

[dB]

[rad/s]



Im

Re

ejω


100%0%

log (ω)

‖N

TF‖

ωBWω0

[dB]

[rad/s]


System-Optimization

less noise,better DR

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

real part = 0.6875imaginary part = 0

Select a pole...

real axis

imag

inar

y ax

is


System-Optimization

better stability

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1


Select a pole...

real axis

imag

inar

y ax

is


System-Optimization

local optimum−1 −0.5 0 0.5 1

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1


Select a pole...

real axis

imag

inar

y ax

is


1 Introduction

2 System Design

3 Circuit Design

4 Results



Overview

+

-

-

+

C3

C3

C4

C4

+

-

-

+

C5

C5

C6

C6

+

-

-

+

C7

C7

C8

C8

+

-

-

+

1

2

C2

C2

C12

C12

C13

A3A2A1 A4

2d

C13

C11

C11

C10

C10

C9

C9

DWA

C1,i1

Np〈i〉

Nn〈i〉

vrefp

vrefn

Nn〈i〉

〈6 : 0〉

C1,i

vrefp

vrefn

Np〈i〉

7 7

QuantizerxDO

vcmo

vcmi

1,2 phase 1,2

delayed phase 1,2

Nn〈i〉

1

1

2

1

1

1d

2d

2

1

12d

2d

1d1d

2d

2d 1

1

2

1 1d

2 2d

2d2

1d1

Np〈i〉

1d,2d

〈6 : 0〉

〈6 : 0〉

2d

Realization Technique:

switched-capacitor


Overview

+

-

-

+

C3

C3

C4

C4

+

-

-

+

C5

C5

C6

C6

+

-

-

+

C7

C7

C8

C8

+

-

-

+

1

2

C2

C2

C12

C12

C13

A3A2A1 A4

2d

C13

C11

C11

C10

C10

C9

C9

DWA

C1,i1

Np〈i〉

Nn〈i〉

vrefp

vrefn

Nn〈i〉

〈6 : 0〉

C1,i

vrefp

vrefn

Np〈i〉

7 7

QuantizerxDO

Integration Stages

4 stages, the last stage is

merged with the

summation amplifier

vcmo

vcmi

1,2 phase 1,2

delayed phase 1,2

Nn〈i〉

1

1

2

1

1

1d

2d

2

1

12d

2d

1d1d

2d

2d 1

1

2

1 1d

2 2d

2d2

1d1

Np〈i〉

1d,2d

〈6 : 0〉

〈6 : 0〉

2d


Overview

+

-

-

+

C3

C3

C4

C4

+

-

-

+

C5

C5

C6

C6

+

-

-

+

C7

C7

C8

C8

+

-

-

+

1

2

C2

C2

C12

C12

C13

A3A2A1 A4

2d

C13

C11

C11

C10

C10

C9

C9

DWA

C1,i1

Np〈i〉

Nn〈i〉

vrefp

vrefn

Nn〈i〉

〈6 : 0〉

C1,i

vrefp

vrefn

Np〈i〉

7 7

QuantizerxDO

Quantizer

8 levels

vcmo

vcmi

1,2 phase 1,2

delayed phase 1,2

Nn〈i〉

1

1

2

1

1

1d

2d

2

1

12d

2d

1d1d

2d

2d 1

1

2

1 1d

2 2d

2d2

1d1

Np〈i〉

1d,2d

〈6 : 0〉

〈6 : 0〉

2d


Overview

+

-

-

+

C3

C3

C4

C4

+

-

-

+

C5

C5

C6

C6

+

-

-

+

C7

C7

C8

C8

+

-

-

+

1

2

C2

C2

C12

C12

C13

A3A2A1 A4

2d

C13

C11

C11

C10

C10

C9

C9

DWA

C1,i1

Np〈i〉

Nn〈i〉

vrefp

vrefn

Nn〈i〉

〈6 : 0〉

C1,i

vrefp

vrefn

Np〈i〉

7 7

QuantizerxDO

Resonator

for placing the notch:

tunable capacitor C13!

vcmo

vcmi

1,2 phase 1,2

delayed phase 1,2

Nn〈i〉

1

1

2

1

1

1d

2d

2

1

12d

2d

1d1d

2d

2d 1

1

2

1 1d

2 2d

2d2

1d1

Np〈i〉

1d,2d

〈6 : 0〉

〈6 : 0〉

2d


Overview

+

-

-

+

C3

C3

C4

C4

+

-

-

+

C5

C5

C6

C6

+

-

-

+

C7

C7

C8

C8

+

-

-

+

1

2

C2

C2

C12

C12

C13

A3A2A1 A4

2d

C13

C11

C11

C10

C10

C9

C9

DWA

C1,i1

Np〈i〉

Nn〈i〉

vrefp

vrefn

Nn〈i〉

〈6 : 0〉

C1,i

vrefp

vrefn

Np〈i〉

7 7

QuantizerxDO

Feedforward Path

4 feedforward paths

vcmo

vcmi

1,2 phase 1,2

delayed phase 1,2

Nn〈i〉

1

1

2

1

1

1d

2d

2

1

12d

2d

1d1d

2d

2d 1

1

2

1 1d

2 2d

2d2

1d1

Np〈i〉

1d,2d

〈6 : 0〉

〈6 : 0〉

2d


Overview

+

-

-

+

C3

C3

C4

C4

+

-

-

+

C5

C5

C6

C6

+

-

-

+

C7

C7

C8

C8

+

-

-

+

1

2

C2

C2

C12

C12

C13

A3A2A1 A4

2d

C13

C11

C11

C10

C10

C9

C9

DWA

C1,i1

Np〈i〉

Nn〈i〉

vrefp

vrefn

Nn〈i〉

〈6 : 0〉

C1,i

vrefp

vrefn

Np〈i〉

7 7

QuantizerxDO

DAC and

Feedback Path

DAC realized with

voltage references

vcmo

vcmi

1,2 phase 1,2

delayed phase 1,2

Nn〈i〉

1

1

2

1

1

1d

2d

2

1

12d

2d

1d1d

2d

2d 1

1

2

1 1d

2 2d

2d2

1d1

Np〈i〉

1d,2d

〈6 : 0〉

〈6 : 0〉

2d


Overview

+

-

-

+

C3

C3

C4

C4

+

-

-

+

C5

C5

C6

C6

+

-

-

+

C7

C7

C8

C8

+

-

-

+

1

2

C2

C2

C12

C12

C13

A3A2A1 A4

2d

C13

C11

C11

C10

C10

C9

C9

DWA

C1,i1

Np〈i〉

Nn〈i〉

vrefp

vrefn

Nn〈i〉

〈6 : 0〉

C1,i

vrefp

vrefn

Np〈i〉

7 7

QuantizerxDO

Data WeightedAveraging (DWA)

for improving the

linearity of the DAC

vcmo

vcmi

1,2 phase 1,2

delayed phase 1,2

Nn〈i〉

1

1

2

1

1

1d

2d

2

1

12d

2d

1d1d

2d

2d 1

1

2

1 1d

2 2d

2d2

1d1

Np〈i〉

1d,2d

〈6 : 0〉

〈6 : 0〉

2d


Amplifier Design

800mV

600mV

300mV

200mV

300mV

900mV

675mV

500mV

1.2V

gm = 9.5mS

gds = 261µS

vdsat = 123mV

Vin+ Vin−

Vout− Vout+

Id = 375µAW4 = 11.5µm

L4 = 180nm

m = 15

W5 = 6.8µm

L5 = 600nm

m = 15

W4

L4

W3

L3

W3 = 2.85µm

L3 = 180nm

m = 15

W1 = 5.4µm

L1 = 600nm

m = 30

W2

L2

gm = 6.2mS

gds = 1.2mS

vdsat = 80mV

gm = 5.7mS

gds = 337µS

vdsat = 91mV

gm = 6.6mS

gds = 350µS

vdsat = 92mV

gm = 3.7mS

gds = 75µS

vdsat = 193mV

W2 = 4.55µm

L2 = 160nm

m = 15

W5

L5

102

103

104

105

106

107

108

109

1010

1011

−40

−20

0

20

40

60

80

100

120

Bode−Plot, CL=800fF

frequency [Hz]

gain

[dB

]

UGBW: 2.86GHz

Corner frequency: 20.9kHz

DC−gain: 100.66dB

102

103

104

105

106

107

108

109

1010

1011

−300

−250

−200

−150

−100

−50

0

50

frequency [Hz]

phas

e [°

]

Phase margin: 63.7°


Comparator Design

Overview

CompxS

vin+

vin− vref−

vref+

CompxS

CompDxS

CompDxS CompDxS

ResCmpxDO

Com

pxS

M1 M2

M3 M4

M5 M6

M7

M8

M9

M10

M11 M12M13 M14

M15 M16

S

R

Q

300mV 300mV

Vb = 600mV

w = 0.12µm

l = 60nm

w = 6.2µm

l = 120nm

w = 1µm

l = 140nm

w = 3.55µm

l = 300nm

w = 1.5µm

l = 60nm

w = 1.2µm

l = 200nm

w = 3µm

l = 60nm

600mV

600mV

Ib Ib

Standard Ib [µA]

GSM-EDGE 18UMTS 18WLAN a/b/g 42WLAN n 60


Comparator Design

Working Principle: Recovery Phase

CompDxS

CompDxS

CompxSB

Timing of Control Signals

CompxS

vin+

vin− vref−

vref+

CompxS

CompDxS

CompDxS CompDxS

ResCmpxDO

Com

pxS

Vb

M1 M2

M3 M4

M5 M6

M7

M8

M9

M10

M11 M12M13 M14

M15 M16

S

R

Q

Standard τrec [ns] T [ns] UGBW [GHz]

GSM-EDGE 1.4 38.462 0.75UMTS 1.4 16.276 0.75WLAN a/b/g 0.9 4.166 1.27WLAN n 0.7 3.125 1.53

Recovery Time τrec:

τrec = 2 · Ron,8 · CL

CL ≈ 15fF

active parts

generates a voltage differencebetween v1 and v2

acts as load(switch M8 closed)

v1

v2


Comparator Design

Working Principle: Regeneration Phase

CompDxS

CompDxS

CompxSB

Timing of Control Signals

CompxS

vin+

vin− vref−

vref+

CompxS

CompDxS

CompDxS CompDxS

ResCmpxDO

Com

pxS

Vb

M1 M2

M3 M4

M5 M6

M7

M8

M9

M10

M11 M12M13 M14

M15 M16

S

R

Q

active parts

Standard τreg [ps] T [ns] ∆Vmin [mV]

GSM-EDGE 24.5 38.462 1.8UMTS 24.5 16.276 1.7WLAN a/b/g 29.3 4.166 1.7WLAN n 31.8 3.125 1.7

Regeneration Time τreg:

τreg =CL

gm3,4 + gm5,6

Resolution:

minimally allowable input

voltage difference ∆Vmin

v1 and v2 are biased slightly below Vdd

(switches M13 and M14 are closed)

v1

v2

latch swings to Vss and Vdd

(switch M8 open)

latch result


Comparator Design

Kickback Noise Comparator in Regeneration Phase

vin+

vin− vref−

vref+

M1 M2

M3 M4

M5 M6

M15 M16 v

v

i

Cgd

Fast voltage changes

leads to current peaks!

i = C · v̇

Latch produces fast

voltage changes.

“kick-back”


Comparator Design

Kickback Noise Countermeasures

CompxS

vin+

vin− vref−

vref+

CompxS

CompDxS

CompDxS CompDxS

ResCmpxDO

Com

pxS

Vb

M1 M2

M3 M4

M5 M6

M7

M8

M9

M10

M11 M12M13 M14

M15 M16

Keep Cgd of

the transistors small!

Disconnect switches while

latch is regenerating!

Cgd

S

R

Q


1 Introduction

2 System Design

3 Circuit Design

4 Results



Results for Circuit Simulations

10−2

10−1

100

101

−140

−120

−100

−80

−60

−40

−20

0

GSM−EDGE

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 100.35 dBSNDR = 100.35 dBTHD = −Inf dBDR = 103.62 dBfsig = 0.08 MHzP

sig = −9.03 dB= −6.03 dB

FS

8192 FFT

GSM-EDGE

DRt Requirement:88dB

DRq of CircuitSimulation:103.62dB

[.]q : without thermal noise

[.]t : with thermal noise


Results for Circuit Simulations

10−1

100

101

102

−120

−100

−80

−60

−40

−20

0

WLAN IEEE 802.11n

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 59.63 dBSNDR = 59.12 dBTHD = −68.69 dBDR = 65.16 dBfsig = 5.00 MHzP

sig = −8.97 dB= −5.97 dB

FS

8192 FFT

WLAN IEEE 802.11n

required DRt:64dB

DRq of CircuitSimulation:65.16dB

[.]q : without thermal noise

[.]t : with thermal noise


Summary of Circuit Simulation Results

Properties GSM-EDGE UMTS WLAN a/b/g WLAN n

required DRt [dB] 88 79 71 64

DRq [dB] 103.62 87.29 79.00 65.16

SNDRq [dB] 100.35 81.49 72.82 59.12

Bandwidth [MHz] 0.1 1.92 10 20

Input Stable Range stable up to 0.8FS

Operating Condition tested for T = 0 . . . 100◦C and for different corners

[.]q : without thermal noise, [.]t : with thermal noise

FS : Full-Scale


Summary of Circuit Simulation Results

data material: ISSCC, JSSC

100kHz 1MHz 10MHz50

55

60

65

70

75

80

85

90

95

100

Bandwidth

DR

[dB

]

Comparison of Implemented Σ∆−Modulators

DT Σ∆−ModulatorCT Σ∆−Modulatorimplemented Σ∆−Modulator


1 Introduction

2 System Design

3 Circuit Design

4 Results



Conclusion and Outlook

Σ∆-design: elaborated cost-function for finding an optimalsolution

Implemented Σ∆-modulator:65nm CMOS processcovers a bandwith from 100kHz up to 20MHzstable input range up to 0.8FSfulfills the requirements for GSM-EDGE, UMTS and WLANa/b/g/n

What remains to do?Design of reference buffer and clock netDigital circuit synthesis for DWADrawing of the layout


Are there any questions?


Documents

A Multi-Standard ADC for Cellular and WLAN in 65nm CMOSssenn.de/files/master_thesis_pres.pdf · A Multi-Standard ADC for Cellular and WLAN in 65nm CMOS Master Thesis of Tomislav Cvetic