A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC Based on Multi-Stage Amplifiers

Young-Ju Kim1, Hee-Cheol Choi1, Kyung-Hoon Lee1, Gil-Cho Ahn1, Seung-Hoon Lee1,

Ju-Hwa Kim2, Kyoung-Jun Moon2, Michael Choi2, Kyoung-Ho Moon2, Ho-Jin Park2, and Byeong-Ha Park2

1Dept. of Electronic Engineering, Sogang University, #1 Sinsoo-Dong, Mapo-Gu, Seoul, 121-742, Korea 2Samsung Electronics Co., Ltd, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do, 449-771, Korea

Abstract- A 12-bit 1.2V 160MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65nm CMOS process are less than 0.69LSB and 1.00LSB respectively. The ADC shows a maximum SNDR of 58.5dB and 53.1dB and a maximum SFDR of 76.0dB and 67.8dB at 160MS/s and 200MS/s, respectively. The ADC with an active die area of 0.72mm2 shows a FoM of 0.75pJ/conv-step at 160MS/s and 1.2V.

I. INTRODUCTION

The advanced technologies for liquid crystal and plasma

display panels have accelerated the improvement of digital video systems. Particularly, the demand of high-definition televisions (HDTVs) processing over 2-million pixels has been gradually increased along with a wide screen size. Those high definition display panels require high-speed signal processing for video inputs and an A/D converter (ADC) is one of the most essential building blocks for the systems. For example, the ADCs to handle RGB signals in high-definition and wide-screen systems require the 8 to 10 effective number of bits (ENOB) and a sampling rate up to 150MS/s. However, the implementation of those ADCs in nanometer-scale CMOS technologies becomes more and more difficult due to a reduced voltage headroom and low intrinsic output resistance of transistors. To overcome the performance limitations of analog circuits, especially operational amplifiers, various inventive circuit design techniques such as reference scaling, correlated double sampling, and zero crossing-based circuits have been developed [1]-[3]. However, the techniques cannot be directly applied to high-performance amplifiers for high-resolution ADCs operating at several hundreds of MHz. As a result, one of the key design issues with the state-of-the-art CMOS processes is an implementation of amplifiers with a high DC gain, a wide bandwidth, and a high output swing range with a low supply voltage.

This work proposes a 12-bit 160MS/s 1.2V 65nm CMOS

pipeline ADC based on multi-stage amplifiers. To overcome the reduced DC gain problem due to a low output resistance of MOS transistors in a 65nm low-voltage digital CMOS process, three-stage amplifiers are used for the input sample-and-hold amplifier (SHA) and multiplying D/A converters (MDACs). The proposed multipath frequency-compensation

technique based on the reversed nested miller compensation (RNMC) maintains a stable operation of conventional three-stage amplifiers at a high conversion speed up to 160MS/s at 12-bit [4].

II. PROPOSED ADC ARCHITECTURE

The proposed 4-step 12-bit pipeline ADC consists of an

input SHA with gate-bootstrapped sampling switches, three MDACs, four sub-ADCs, and on-chip references, as shown in Fig. 1. The front-end SHA with a voltage gain of –2.92dB reduces the internal signal range from 1.4Vp-p to 1.0Vp-p considering high input signal levels at a low supply of 1.2V. The SHA, MDAC1, and MDAC2 are implemented with a three-stage amplifier for a high DC gain, while the MDAC3 employs a two-stage amplifier. The output stages in all the multi-stage amplifiers adopt a common-source circuit with a single tail current source for a high signal swing.

Fig. 1. Proposed 12-bit pipeline ADC architecture.

III. CIRCUIT IMPLEMENTATION

A. Proposed input SHA with gate-bootstrapping switches and level shifting capacitors

The proposed input SHA employs gate-bootstrapping MOS switches to minimize the non-linear distortion of sampled inputs due to the on-resistance variations of switches by keeping the gate-source voltage of input sampling switches constant. Two capacitors, CD1 and CD2, of the input SHA reduce the 1.4Vp-p input signal to 1.0Vp-p for the remaining

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pipeline stages to operate properly with a high enough margin. The full schematic of the input SHA during the sampling and holding modes is illustrated in Fig. 2. The active circuits and switches at each mode are indicated in a heavy line for easy understanding of the SHA operation. During the sampling mode in Fig. 2(a), capacitors, C1 and C2, sample an input signal passing the gate-bootstrapping switches through while capacitors, CD1 and CD2, sample a common-mode voltage, VCM , at both of the top and bottom plates. During the next holding mode in Fig. 2(b), all the capacitors, C1, C2, CD1, and CD2, are tied to the outputs, which produces a reduced input signal by the ratio of C1/(C1+CD1). Considering the thermal noise of input switches, a capacitance of 1.2pF is chosen for C1 and C2 and 0.48pF for CD1 and CD2.

(a)

(b)

Fig. 2. Proposed input SHA with gate-bootstrapping switches and level shifters: (a) sampling mode and (b) holding mode. B. Proposed multipath RNMC-based three-stage amplifier

Although a three-stage amplifier is not an attractive candidate for high-speed applications due to complicated frequency compensation and relatively high power dissipation, recently developed ADCs in a low-voltage nanometer CMOS employ this topology to achieve the required high DC gain [5],[6]. Of many frequency compensation techniques for a three-stage amplifier, nested miller compensation (NMC) and RNMC techniques have been commonly used. The RNMC

technique has a considerable bandwidth advantage over the NMC since the most inner feedback loop of the RNMC has no connection to a load capacitance as shown in Fig. 3(a) [4]. However, the transfer function of the RNMC amplifier consists of three poles and two zeros as described in (1). One zero is located in the left half plane, while the other is located in the right half plane (RHP). The RHP zero may cause a stability problem due to the reduction of phase margin. To remove the undesirable RHP zero, an additional feed-forward path is employed between the input node of the first amplifier and the output node of the second amplifier. Fig. 3(b) shows the proposed three-stage amplifier based on the multipath RNMC in a simplified single-ended topology. When the trans-conductance is set to be g mf =g m1, its transfer function without the RHP zero is summarized in (2). In Fig. 3, g mi, Ri, and Ci are defined as the trans-conductance, output resistance, and parasitic capacitance for the i-th stage, respectively, while Cm1, Cm2, and CL are indicated for the relevant compensation and load capacitors.

(a)

(b)

Fig. 3. Three-stage amplifiers with two compensation techniques: (a) conventional RNMC and (b) proposed multipath RNMC.

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The proposed multipath RNMC based three-stage amplifier

in this work consists of folded-cascode and telescopic amplifiers connected to a backend common-source amplifier in a fully differential architecture as illustrated in Fig. 4. The additional feed-forward path for high stability is connected to a low-impedance node in the second amplifier. With this scheme, the proposed three-stage amplifier achieves the overall open-loop DC gain above 90dB. Each stage amplifier employs independent switched-capacitor type common-mode feedback circuits for low power consumption.

Fig. 4. Circuit implementation of the three-stage amplifier.

IV. PROTOTYPE ADC MEASUREMENTS

The prototype ADC is implemented in a 65nm CMOS

process and consumes 82mW at 160MS/s with a 1.2V power supply. The active die area is 0.72mm² (=0.99mm ´ 0.73mm) as shown in Fig. 5. As demonstrated in Fig. 6, the measured differential non-linearity (DNL) and integral non-linearity (INL) are within ±0.69LSB and ±1.00LSB, respectively. At a clock frequency of 160MHz, the measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 58.5dB and 76.0dB, respectively, with a 4.2MHz 1.4Vp-p input signal, as plotted in Fig. 7. The figure of merits (FoM), defined as (3), is 0.75pJ/conv-step. The SNDR and SFDR of the prototype are maintained above 54.2dB and 67.2dB, respectively, up to a Nyquist input frequency of 80MHz at a 160MHz sampling rate.

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The SNDR and SFDR of Fig. 8 are measured with different sampling frequencies up to 200MS/s at a 4.2MHz input signal. The SNDR and SFDR are maintained over 53.1dB and 67.8dB, respectively, up to 200MS/s. The overall ADC performance is summarized in Table I and the recently reported 12-bit CMOS ADCs operating above 70MS/s are compared with the proposed ADC in Table II [7]-[11]. As observed in Table II, the proposed 12-bit 1.2V 160MS/s CMOS ADC shows a high linearity and power efficiency with a relatively small chip area in a state-of-the-art 65nm CMOS process.

Fig. 5. Chip photograph of the prototype ADC (0.99mm × 0.73mm).

Fig. 6. Measured DNL and INL.

Fig. 7. Measured FFT spectrum.

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Fig. 8. Measured SFDR and SNDR versus sampling frequency.

TABLE I

PERFORMANCE SUMMARY OF THE PROTOTYPE ADC

TABLE II PERFORMANCE COMPARISON OF RECENTLY REPORTED

12-Bit CMOS ADCS OPERATING ABOVE 70MS/s

V. CONCLUSION

This work proposes a 12-bit 1.2V 160MS/s pipeline 65nm CMOS ADC for high-definition video systems. The proposed multipath RNMC based three-stage amplifier is employed for a high DC gain and stable operation at a sampling rate of 160MS/s. The prototype ADC shows a maximum DNL and INL within 0.69LSB and 1.00LSB, respectively, and a FoM of 0.75pJ/conv-step at 160MS/s and 1.2V.

ACKNOWLEDGMENT

This work was supported by Samsung Electronics, System

IC 2010 Project of Korea Ministry of Knowledge Economy, and the IDEC of KAIST, Korea.

REFERENCES

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[8] A. Loloee, A. Zanchi, H. Jin, S. Shehata, and E. Bartolome, “A 12-bit 80MSps Pipelined ADC Core with 190mW Consumption from 3V in 0.18um Digital CMOS,” in Proc. Eur. Solid-State Circuits Conf., Sept. 2002, pp.467-470.

[9] T. Ito, D. Kurose, T. Yamaii, and T. Itakura, “55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers,” in Proc. Eur. Solid-State Circuits Conf., Sept. 2006, pp.540-543.

[10] T. N. Andersen et al., “A cost-efficient high-speed 12-bit pipeline ADC in 0.18um digital CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7 pp. 1506-1513, July 2005.

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