A 65nm, 1- Buck Converter With Multi-Function SAR-ADC-Based CCM-PSK Digital Control Loop

7/28/2019 A 65nm, 1- Buck Converter With Multi-Function SAR-ADC-Based CCM-PSK Digital Control Loop

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1546 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

A 65-nm, 1-A Buck Converter With Multi-FunctionSAR-ADC-Based CCM/PSK Digital Control Loop

Sbastien Cliquennois, Achille Donida, Piero Malcovati, Andrea Baschirotto, and Angelo Nagari

AbstractThis paper proposes a 1-A, 6.4-MHz switchingfrequency DC-DC converter with embedded digital controller,implemented in 65-nm CMOS technology. The proposed DC-DCconverter, exploiting a customized, multi-function SAR ADC anda non-linear PID controller, can switch automatically betweencontinuous-conduction mode and pulse-skipping mode, thusmaintaining a fairly large efficiency also for light loads. Moreover,a feedforward path in the digital control loop, implemented usingthe SAR ADC for converting also the battery voltage, significantlyimproves the line transient performance. The DC-DC converter,which occupies an area of 0.038 , consumes 115.5 , andrequires an external inductance as low as 470 nH, is particularlysuited for portable applications.

Index TermsAnalog-digital conversion, analog-digital in-tegrated circuits, CMOS integrated circuits, DC-DC powerconverters.

I. INTRODUCTION

D IGITAL control of Switched-Mode Power Supplies(SMPS) circuits is spreading in power electronics appli-cations [1][8] and it can now be found in discrete commercial

products. However, the adoption of this technique is not yet

very common in Integrated Circuits (IC) for portable applica-

tions. First of all, digital SMPS ICs for portable applications

work in the low power range (typically around 1 W), where

high efficiency is a must. To cope with this constraint, dedicated

very low-power ADC structures [4], [8] and circuit solutions

[2], [6] have to be developed. At the same time, as most of

the ICs for portable applications, digital SMPS circuits have to

be implemented in cutting edge technologies [3], [5], [6], [8],

where they can benefit from better digital density and transistor

speed, which allows higher switching frequencies (1 MHz

10 MHz) to be used. Moreover, small silicon area is also of

paramount importance, in order to compete with analog SMPS

circuits, thus requiring dedicated solutions for implementing

both the ADC and the digital controller. Finally, last but not

least, digital SMPS circuits can take advantage of the inherent

Manuscript received November 15, 2011; revised January 30, 2012; acceptedFebruary 20, 2012. Date of current version June 21, 2012. This paper was ap-proved by Guest Editor Atila Alvandpour. This work was supported in part bya Nano 2012 grant.

S. Cliquennois, and A. Nagari are with ST-Ericsson, Grenoble, France(e-mail:[email protected];[email protected]).

A. Donida, and P. Malcovati are with the Department of Electrical Engi-neering, University of Pavia, Italy (e-mail: [email protected]; [email protected]).

A. Baschirotto is with Department of Physics G. Occhialini, University ofMilan-Bicocca, Italy (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2012.2191214

Fig. 1. Simplified block diagram of the digital SMPS.

signal processing capabilities of digital solutions, in order to

implement advanced control schemes, including, for example,lossless current sensing [7] or non-linear algorithms [8].

In SMPS for portable devices, besides the peak efficiency,

which is an important performance parameter in conventional

applications, the efficiency at light loads is also a major issue.

Indeed, considering that a portable device is typically requiring

the peak current value for short periods and spends most of the

time in low-power standby state, the efficiency at light loads is

affecting the battery life at least as much as the peak efficiency.

Therefore, SMPS for portable applications have to maintain a

reasonable efficiency even for load currents as low

as 1% of the peak current, without significantly degrading the

voltage regulation performance, thus requiring some sort of ef-ficient low-power operating mode. The minimization of the size

of off-chip components, especially of inductors, is also quite im-

portant in portable applications, since PCB area is becoming as

significant as chip area in determining the device cost. This can

be achieved using a higher switching frequency.

This paper proposes a digital SMPS in 65-nm CMOS

technology, designed for portable applications, in which area

occupation is reduced by using a multi-function SAR ADC

to achieve the required functionalities with minimum power

consumption. Moreover, using a single multi-function SAR

ADC in a digital SMPS enables to digitize with a time-sharing

scheme both the battery voltage and the regulated

0018-9200/$31.00 2012 IEEE


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CLIQUENNOIS et al.: A 65-nm, 1-A BUCK CONVERTER WITH MULTI-FUNCTION SAR-ADC-BASED CCM/PSK DIGITAL CONTROL LOOP 1547

Fig. 2. Simplified timing diagram of the digital SMPS in CCM.

voltage [9]. In particular, data enhances the

line-transient performance, while allowing the implementation

of additional control and estimation schemes needing this infor-

mation. Other solutions presented in the literature, such as [10],which exploit the information on , include an additional

dedicated ADC for this purpose, that requires extra area and

power consumption. The proposed digital SMPS switches at

6.4 MHz and can operate both in Continuous-Conduction Mode

(CCM) and Pulse-Skipping (PSK) mode, thus maintaining the

efficiency relatively high also at light loads. Automatic mode

switching allows flawless transitions between the two modes.

The development of the proposed device is based on real-

life specifications of an SMPS for portable application, and,

therefore, it does not focus solely on transient performance op-

timization, as most of the other digital SMPS ICs described in

the literature. Indeed, the proposed SMPS involves a completeoptimization of the system, including support for a wide range of

power supplies (thanks to the feedforward), introduction

of a digital variable reference, and automated-mode switching

between PSK and CCM. All these features are available (for the

controller part) with a silicon area almost one order of magni-

tude smaller than the state-of-the-art.

The paper is organized as follows. Section II describes the

digital SMPS architecture, including CCM and PSK control

loops, as well as automatic mode switching. The proposed

SAR ADC is then illustrated in Section III. Section IV reports

the achieved experimental results and, finally, Section V draws

some conclusions.

II. DIGITAL SMPS ARCHITECTURE

Fig. 1 shows a simplified block diagram of the proposed dig-

ital SMPS, showing both CCM and PSK mode control loops,

while Fig. 2 shows a simplified timing diagram for the system

operating in CCM.

A single 7-bit SAR ADC embedded in the system is used

in time-sharing to digitize both and with different

timings. The larger bandwidth requires that is dig-

itized with a higher sampling frequency . On

the other hand, the lower bandwidth allows us to digitize

at a data rate equal to , thus reducing

the ADC and clock generator power consumption of about 50%

with respect to the case in which is digitized with sam-

pling rate equal to , without degrading the system perfor-

mance.

A. Continuous-Conduction Mode (CCM)

In CCM, a closed-loop mixed-signal system controls the

output voltage . Bandwidth, stability, and accuracy

are optimized by exploiting the 65-nm CMOS high-speed

capability, for operating the digital SMPS with a 307.2-MHz

master clock.

The digital wordrepresenting issubtracted from a 7-bit

set-point ( , corresponding to the desired voltage level

), to obtain a digital representation of the error

. Reference is digitally filtered, to smooth

the dynamic voltage scaling behavior. On the other hand, the

digital word relative to allows the implementa-

tion of a feedforward path in the control-loop for optimizing the

system response and stability [10]. Both digital words are fed to

a digital controller, whose block diagram is shown in Fig. 3, in-

cluding a non-linear PID [11] and a divider, which calculate the

next 11-bit duty-cycle value. A multi-bit modulator dithers

the 11-bit signal into a 48-level signal , coded on 6 bits,

fed into a simple counter-based Digital Pulse-Width Modulator

(DPWM) [12]. The DPWM generates the 1-bit signal which

drives the integrated power stage buffers, as well as the clock

signals for the ADC and the PID controller.

The DPWM and clock generator consists of a simple 48-level

ripple-counter operated at 307.2 MHz. From the counter output

, several signals are obtained:

the PWM signal, which is rising to 1 when

and falling back to 0 when ;

the SAR ADC conversion clock , obtained by

gating with the counter the 307.2-MHz clock divided by

2, so that is only present for 7 periods for

and 4 periods for ;

the SAR ADC sampling clock , directly gener-

ated from counter.

An additional 5-bit counter operated at 6.4 MHz (307.2

MHz/48) is gating the related clocks ( and

), allowing the sampling frequency to range

from (i. e. the same rate as ) to .


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Fig. 3. Block diagram of the digital controller.

Fig. 4. Digital controller coefficient values as a function of the error signal.

The PID controller implements the classical discrete-time

transfer function

(1)

where is the signal coming from the ADC, coded with

four signed bits, and is the duty-cycle, coded with 18 bits,

as required to avoid saturation. As proposed in [12], coefficients

, , and are implemented as lookup tables (LUTs). The

coefficients depend on the value of , thus making the re-

sponse non-linear and allowing a faster transient response, while

keeping stability. The coefficient values as a function of

are plotted in Fig. 4. Unlike in [11], where coefficients are ana-

lytically chosen, the proposed approach starts from a manually-

designed compensator, which is then fed into an optimization

loop, aiming at minimizing the over-voltage and maximizing

the phase margin, over the whole range of , tran-

sistor on-resistance , inductance , capacitance ,

and equivalent series resistance .

The feedforward path in the digital controller introduces an

additional static term in the classical open-loop con-trol-to-output transfer function of a Buck converter based on the

average model, given by

(2)

where is the steady-state duty-cycle, and

, in which the DC gain is actually proportional

to . The additional term , introduced by the feed-

forward path, effectively cancels this dependency and leads to

a constant DC gain in the transfer function, thus allowing the

use of a more aggressive compensation over the wholerange. It can also be shown [9] that with such a scheme, at least

at first order, at DC. This is actually not

completely true when second order and quantization effects are

considered, but it clearly shows the benefits of the feedforward

path in the digital controller on the line regulation performance.

In order to preserve the phase margin, the digital SMPS must

minimize the loop-delay, i. e. the time spent between sampling

and applying the correction to the system. To optimize

this timing, a 153.6-MHz burst clock signal is used for the ADC,

derived from the master clock, allowing a fixed latency. More-

over, as already mentioned, the calculations in the digital PID

are done with mere lookup tables, adders and multipliers, onlyneeding a single clock edge to determine the duty-cycle [13].

The DPWM is sampling this result 16.2 ns later, in order to ac-

count for worst-case signal propagation in the control circuit.

B. Pulse-Skipping (PSK) Mode

The SMPS power stage and switching frequency are designed

to offer maximum 85% efficiency at minimum drop-out for high

currents, but this efficiency degrades very steeply when the load

is such that the current in the inductance is inverting, adding

extra losses to the already dominant switching losses. In order

to alleviate this issue, a Pulse-Frequency Modulation (PFM)

scheme can be used. A fixed-duration (fixed ) pulse is ap-

plied to the output stage, which then goes to high-impedance


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Fig. 5. Simplified automatic-mode switching finite-state machine.

state until the output voltage drops below the set-point. An al-

ternative solution is synchronizing the output voltage tracking

with a clocked comparator [2]. However, while this scheme of-

fers excellent efficiency performance, its reduced bandwidth,

due to thelower clock frequency, makes it a good candidate only

for dedicated ultra-low current modes, but it cannot be used for

medium to low current modes (i. e. below critical conduction),

where transient performance requirements are expected to be

similar to CCM.

The solution implemented in the proposed SMPS, called

Pulse-Skipping (PSK) mode, is a synchronized fixed-on-time

PFM scheme, which exploits the same ADC as in

CCM to compare the output voltage with a digital set-point.

In order to generate a value of which minimizes losses,

a digital adaptive scheme is used. An initial digital value

, where is the

number of DPWM levels, is calculated using look-up tables

for fast and efficient implementation of the required division.

The value of corresponds to the time required for the

current to reach zero after a conduction period for a lossless

power stage. Because of losses, the actual value of will

be necessarily larger. Therefore, at the end of each conduction

cycle, a current sensing circuit detects if the inductance cur-

rent is negative (conventional zero crossing method [14]). If

this is the case, is increased by 1 LSB, until a positive

inductance current is detected. After a conduction period, if the

ADC detects that the output voltage is still below the set-point,

another pulse is generated, or, otherwise, the output stage goes

in high-impedance state, until the output voltage drops again

below the set-point.

C. Automatic Mode Switching

A key feature for a SMPS is the ability to automatically select

the optimal operating mode for efficiency: if the load current

is such that the current in the inductance is in-

verting before the end of the switching period, PSK mode must

be used, whereas CCM is required for higher values of .

The transition between the operating modes is managed by

the Finite-State Machine (FSM) shown in Fig. 5. Two variables

are used for choosing the operating mode: the output code of

the SAR ADC , which is a digital image of the

output voltage error, and the digital signal , provided by

the current sensing circuit, whose function is to sense whether

the current in the inductance is positive or negative at the end of

every conversion period. The current sensing circuit runs at the

power stage frequency, using as clock.

The SMPS is starting in open-loop configuration, by pro-

gressively incrementing the internal value of the PID accumu-

lator, while the saturated output of the ADC remains discon-

nected from the digital compensator. When the output voltage

approaches the set-point , the output of the ADC is

connected to the PID input and the system starts operating in

closed-loop configuration, always in CCM mode. In order to

avoid oscillation between modes, because of potential wrong

decisions taken during transients, the FSM waits until

for consecutive periods (i. e. the SMPS is in stable con-

dition), before allowing entering PSK mode, if needed (in a

low-load condition). Moreover, the decision to eventually enter

PSK mode is taken when the inductance current is inverted

for consecutive periods. The value of

is chosen so that the system is settled in worst-case con-

ditions.

The state PSKOpen SW corresponds to the situation

in which both power transistors are open, leading to high

impedance at node . When entering this state (always

after a conduction period of the bottom power transistor), the

value of is detected and the value of for the next

conduction period is calculated. The state PSKClose SW

corresponds to a full conduction period, with duty-cycle given

by .

To be less sensitive to the offset of the current sensing circuit

and provide hysteresis, the condition to quit PSK mode is based

on the ADC output value: as long as the output voltage remains

within 1 LSB around the set-point , the system stays in


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Fig. 6. Operating principle of the current sensing circuit.

PSK mode, otherwise it switches back to CCM . In case

of fast load transients, which create an important output voltage

drop, the SMPS switches back at once to CCM and can quickly

react to the transient. In case of slow increase of the load current,

the system switches back to CCM only when needed. Indeed, if

the load current is slightly larger than the maximum current that

the system can supply in PSK mode, the output voltage slowly

drops and reaches the condition , for which it switches

back to CCM.

A necessary condition for the FSM to be stable is that

, where is the threshold value, for

which the current sensing circuit detects that the inductance

current is inverted, and is the critical output current

(the steady-state output current for which the inductance

current becomes negative during the conduction period). If

and the output current is such that

, the system will enter PSK mode,

not being able to provide enough current. Therefore, the output

voltage drops and the FSM continuously oscillates between the

two modes. Although the transient and regulation characteris-

tics of the SMPS are not affected by this situation, unwanted

low frequency oscillations with period larger than will

occur.

In order to avoid this condition, an offset is added in the

current sensing circuit, such that , even for

worst-case process variations. As a consequence of this offset,

when , the system still remains in

CCM, although the current in the inductance is inverting. There-

fore, the efficiency slightly drops in this zone, as evident in the

measured efficiency curve reported in Fig. 16.

D. Current Sensing Circuit

The operating principle and the schematic of the current

sensing circuit are shown in Fig. 6 and Fig. 7, respectively. The

function of this circuit is to determine, at the end of each con-

duction period, whether the inductance current is inverted

and is flowing back to ground. This information is used in

CCM, to determine if the system should switch to PSK mode,

and in PSK mode, to evaluate if the applied is too short.

The inductance current detection is performed indirectly, by

sensing the voltage . As shown

in Fig. 6, if is inverting before the end of the conduction

period of transistor , then voltage is becoming pos-

itive, because the current is now flowing from node to node

. On the other hand, if remains positive, the sign of

voltage is not changing and remains negative. More-

over, since after is turned off, either diode or

diode is conducting, in both cases the sign of voltage

is actually reinforced (i. e. in phases and ).

The sensing circuit shown in Fig. 7 basically amplifies

voltage ( , being the transconductance

of transistors and ), which is then further amplified by

a chain of inverters and sampled by a flip-flop on the

falling edge of the driving signal of . Since the clock


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Fig. 7. Schematic of the current sensing circuit.

Fig. 8. Schematic of the multi-function SAR ADC.

signal of the sampling flip-flop is then buffered to

generate the driving signal of the power transistor itself, it is

guaranteed that switching always occurs after sampling, thus

not disturbing the measurement.

The drawback of this structure is that the PWM duty-cycle

has to be such that conduction occurs in transistor (i.

e. the duty-cycle has to be lower than 95%, considering digital

clamping). However, in actual portable applications, where the

input voltage is provided by a battery and the output voltage

is lower than 1.8 V, a duty-cycle value larger than 95% never

occurs in steady-state.

The speed of decision impacts the precision of the threshold

current , which is important to avoid oscillation between

modes. Therefore, a fairly significant current in each

branch of the circuit shown in Fig. 7 is required. However, the

current sensing circuit is only activated during conduction pe-

riods and, therefore, its power consumption leads to less than

0.1% efficiency loss at the limit between PSK mode and CCM,

while in PSK mode the average power consumption scales lin-

early with the output current, thus not impacting significantly

the overall efficiency even for smaller currents.

III. MULTI-FUNCTION SAR ADC

The functionality of the complete digital SMPS is achieved

with a customized 7-bit SAR ADC, operated at 153.6 MHz

(19.2-MHz maximum sampling frequency). The SAR ADC per-

forms three functions: it acts as a DAC for , as a 4-bit

windowed ADC for and as a 7-bit full-range ADC for

. The implementation of these three functions in a single

device allows a significant overall power consumption and area

reduction. However, it requires different input conditioning cir-

cuits for and . The proposed architecture can fur-

ther scale: control of several power stages can be multiplexed

keeping a single ADC and controller by simply adding some

phases to the clock generator and to the DPWM.

Two different Successive Approximation Registers (SARs),

as well as two different voltage dividers, placed in front of the

ADC core have been implemented. A resistive divider by a

factor 5 is used for and a capacitive divider by a factor

1.27 is adopted for . Considering that the maximum value

of is 4.8 V, the choice of a resistive divider in this case

is mandatory, in spite of the additional power consumption,


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Fig. 9. Timing diagram of the multi-function SAR ADC.

to avoid using high voltage transistors in the ADC. By con-

trast, a capacitive divider can be used for , since the max-

imum output voltage is within the operating range of standard

mid-oxide transistors (2.5 V). Moreover, different accuracies

are required for and . The digital word is

representing only the error signal with respect to . Thus,

is coded with only 4-bit resolution around the reference

value set by (set-point). The ADC resolution while pro-

ducing is a major design parameter of the circuit, since

it is directly linked to the SMPS DC regulation performance

and has a direct effect on potential stability issues. Indeed, a

small LSB causes stability problems (due to the DPWM reso-

lution) [15], while a large LSB leads to regulation performance

issues. A reasonable trade-off is to use a 10-mV LSB. Lower

LSB values cannot be achieved with the proposed architecture

in the used technology, since the 11-bit resolution of the DPWM

is the maximum achievable with a simple counter implemen-

tation (to achieve higher resolution a DLL would be required,

with a large area and power consumption penalty). On the other

hand, the LSB for conversion is 39 mV to cover the full

range with 7 bits of resolution.

The complete schematic and the timing diagram of the multi-

function 7-bit SAR ADC are shown in Fig. 8 and Fig. 9, re-

spectively. The ADC operates with 1.2-V power supply and 1-V

reference voltage . The 1.2-V power supply for the ADC is

generated by a small auxiliary voltage regulator (LDO). This so-

lution is fully compatible with actual power management units

(PMUs) for portable applications, where a LDO is often used

to power an always-on small domain in the digital processor.

This LDO is always turned-on first and, hence, it can be used to

power the ADC and the logic within the SMPS.

Fig. 10. Microphotograph of the chip and layout of the controller.

The input signals and , scaled by the corre-

sponding voltage dividers, are sampled (actually is


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Fig. 11. Line regulation measurement for different values of the load current.

Fig. 12. Line transient measurement.

Fig. 13. Load transient measurement.

sampled by the capacitive divider itself) and applied to the

comparator input. The DAC voltage , controlled by the

SARs, is connected to the other comparator input. This choice

allows sampling while the ADC is converting and

vice-versa, thus increasing the time slot available for sampling,

without degrading the conversion speed of the ADC. For sam-

pling the input signal directly on the DAC, as typically done

in SAR ADCs, a specific time slot would have been required,

leading to a larger latency in the feedback control loop.

The analog part of the SAR ADC consists of a latched com-

parator and a DAC, realized with a charge redistribution ca-

Fig. 14. Transient measurement during automatic mode switching from CCMto PSK.

Fig. 15. Transient measurement during automatic mode switching from PSKto CCM.

Fig. 16. Efficiency measurement.

pacitive structure. The 7-bit array is split in two parts (4 and

3 bits, respectively) with a bridge capacitor , to reduce

the total capacitance and, hence, the power consumption. In

fact, a binary weighted DAC is chosen instead of a thermo-

metric DAC, that would lead to lower reference voltage power

consumption, but also to larger digital power consumption and


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TABLE IPERFORMANCE SUMMARY

area, with an overall disadvantage. Before each con-

version, the capacitive array is pre-charged with a fixed offset

, to adjust the intrinsic ADC voltage range

(0 V 1 V), determined by the value of , to cover the whole

required range (0.6 V 1.35 V, which becomes 0.47

V 1.1 V after scaling). Basically, voltage is added to

by pre-charging, during reset, capacitors and to

and discharging the other capacitors of the DAC to ground

. During conversion the reference

word is added to the SAR output before feeding it to the

DAC, in order to center the 4-bit conversion around the required

voltage level (windowed ADC operation).

IV. EXPERIMENTAL RESULTS

The proposed digital SMPS circuit has been fabricated in a

65-nm CMOS technology. Fig. 10 shows a microphotograph of

the chip, whose area, without considering the power transistors,

is 0.038 .

The line regulation measurements for different values of the

load current are illustrated in Fig. 11. The achieved

performance is limited by the ADC LSB (10 mV), as expected.

Fig. 12 and Fig. 13 show the measured line and load transients,

respectively. The line transient is significantly improved by the

introduction of the feedforward path that can be implemented

thanks to the availability of the information on , guaran-

teed by the multi-function SAR ADC.

The behavior of the system during the automatic transition

from CCM toPSKmode,resultingfrom a steep drop of ,

is illustrated in Fig. 14. When drops, rises, since

there is an excess of charge, coming from the inductance, that

cannot be evacuated by the load and, hence, accumulates on the

capacitance . When has been detected to be

steadily inverted, the system enters in the PSKOpen SW

state, leaving the output in high-impedance condition, until

and, hence, the ADC output reaches the value ( ,

corresponding to ) for which the normal

PSK sequence starts. The mode-transition overshoot, in this

case, is around 25 mV. Fig. 15 shows the automatic transition

from PSK mode to CCM, resulting from a load current step

of 400 mA. The system is leaving PSK mode when the output


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voltage drop is more than 15 mV and the non-linear

PID takes over. The resulting undershot is limited to about

20 mV, in line with the load transient measurement shown in

Fig. 13.

Fig. 16 shows the efficiency measurement. The input power

has been accurately measured using a 4-wire source meter on

(which is supplying the power stage and the buffers), and

another 4-wiresource meter on the 1.2-V supply. Themaximum

efficiency achieved, equal to 85%, is in line with expectations,

considering that the power stage has not been optimized for this

particular application, nor in terms of transistor sizes, nor in

terms of dead-time. This efficiency value could appear fairly

low compared to [3] and [6], but the high switching frequency,

with the associated switching losses, explains most of the differ-

ence. The high switching frequency, on the other hand, allows

a small inductance value to be used, which is

important in portable applications (a 470-nH inductor occupies

about 50% of the area of a 1- inductor with the same fea-

tures). The automatic mode switching allows us to maintain the

efficiency higher than 70% down to , while,

considering CCM only, at the efficiency would

be around 13%.

The main features of the proposed digital SMPS are summa-

rized in Table I and compared with the state-of-the-art [3], [6].

The adopted system and circuit solutions achieve similar perfor-

mance as [3], with smaller die area (1/3 factor) and lower power

consumption (1/8 factor), while using a 6.4-MHz switching fre-

quency, which allows the use of a small 470-nH inductor, in line

with the continuous trend of shrinking portable devices PCB

sizes [6].

V. CONCLUSIONS

In this paper we presented a 1-A, 6.4-MHz switching

frequency buck digital SMPS, realized in 65-nm CMOS tech-

nology, which takes advantage of a multi-function, low-power

SAR ADC to achieve a very low area, while keeping acceptable

static and dynamic performance. The proposed SMPS, besides

the conventional continuous-conduction mode, implements a

simple, adaptive- pulse-skipping mode with automatic

mode switching, which maintains the efficiency fairly large

also at low load currents. Moreover, a feedforward path in the

control loop, implemented using the SAR ADC for convertingalso the battery voltage, leads to a significant improvement of

the line transient performance. The proposed architecture is

well suited for further developments in the digital controller,

which can take advantage of the battery voltage information

to implement, for example, current estimation algorithms or

more complex control schemes. Time-multiplexing can also be

pushed further by using the same ADC for sensing the output

voltage of several power stages.

ACKNOWLEDGMENT

The authors would like to thank Denis Cottin, Nicolas Marty,

Sandrine Majcherczak, and Catherine Popon, for the design and

the implementation of the integrated power stage and of the cur-

rent sensing circuit, as well as for the layout of the circuit and

of the test chip, Shu Wang for the design of the DPWM and for

the help in the measurements, and Christophe Prmont for sup-

porting this work.

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[7] T. Liu, H. Yeom, B. Vermeire,P. Adell,and B. Bakkaloglu, A digitallycontrolled DC-DC buck converter with lossless load-current sensingand BIST functionality, in IEEE ISSCC Dig., 2011, pp. 388398.

[8] S. Cliquennois, A. Donida, P. Malcovati, A. Baschirotto, and A. Na-gari, A 65-nm, 1-A buck converter with multi-function SAR-ADC-based CCM/PSK digital control loop, in Proc. ESSCIRC, 2011, pp.427430.

[9] B. Arbetter and D. Maksimovic, Feedforward pulse width modulatorsfor switching power converters, IEEE Trans. Power Electronics, vol.12, no. 2, pp. 361368, Mar. 1997.

[10] X. Zhang and D. Maksimovic, Digital PWM/PFM controller with

input voltage feed-forward for synchronous buck converters, in Proc.IEEE A pplied Power Electronics C onference an d Ex position (APEC),Feb. 2008, pp. 523528.

[11] V. Yousefzadeh and S. Choudhury, Nonlinear digital PID controllerfor DC-DCconverters, inProc. IEEE Applied Power Electronics Con-

ference and Exposition (APEC), Feb. 2008, pp. 17041709.[12] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, Digital pulse

width modulator architectures, in Proc. IEEE Power Electronics Spe-cialists Conf. (PESC), Jun. 2004, pp. 46894695.

[13] A. Prodic and D. Maksimovic, Designof a digital PID regulator basedon look-up tables for control of high-frequency DC-DC converters, in

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[14] C. L. Chen, W. J. Lai, T. H. Liu, and K. H. Chen, Zero current detec-tion technique for fast transient response in buck DC-DC converters,in Proc. ISCAS, 2008, pp. 22142217.

[15] H. Peng, A. Prodic, E. Alarcon, and D. Maksimovic, Modeling ofquantization effects in digitally controlled DC-DC converters, IEEETrans. Power Electronics, vol. 22, no. 1, pp. 208215, Jan. 2007.

Sbastien Cliquennois received the EngineeringDegree from Institut Suprieur dElectronique et duNumrique (ISEN), Lille, France and DEA degreefrom Lille I University both in 1998.

He held various positions at ST Microelectronicsand ST-Ericsson in computer-aided design tools de-velopment and design of mixed-signal power man-agement circuits for portable applications. He lead re-search activities on modeling, simulation and digital

control of integrated switched-mode power supplies,and is now a Technical Project Leader for ST-Eric-

sson in Grenoble, France.


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Achille Donida was born in Milano (MI), Italy, in1983. He received the Bachelor Degree in Electronicand Telecommunications Engineering from the Uni-versity of Pavia, Italy, in 2006. In 2008 he receivedtheMaster Degreein ElectronicEngineeringfrom thesame University with a thesis on RFID system de-sign. Since 2008 he is working at the Sensors andMi-crosystems Laboratory (SMS) of University of Pavia,Italy, as a Ph.D. student. His research activity is fo-cused on analog to digital converter design in collab-oration with ST-Ericsson (Grenoble).

Piero Malcovati graduated in electronic engineeringfrom the University of Pavia, Italy, in 1991. In 1992,he joined the Physical Electronics Laboratory (PEL)at the Federal Institute of Technology in Zurich(ETH Zurich), Switzerland, as a Ph.D. candidate. Hereceived the Ph.D. degree in electrical engineeringfrom ETH Zurich in 1996.

From 1996 to 2001, he was an Assistant Professorin the Department of Electrical Engineering at theUniversity of Pavia. Since 2002, he is an AssociateProfessor in the same University. His research activ-

ities are focused on microsensor interface circuits, high performance data con-verters, and power management circuits.

Dr. Malcovati is a co-recipient of the ESSCIRC 2007 best paper award. Hewas Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII from 2008 to 2010. He served as Technical Program Chairman of the IEEEPRIME 2006 Conference and as Technical Program Co-Chairman for the IEEEICECS 2009 Conference. He was and still is member of the Scientific Com-mittees for several International Conferences, including ESSCIRC, SENSORS,ICECS, DATE and PRIME. He is regional editor for Europe of the Journal ofCircuits, Systems, and Computers. He is an IEEE senior member.

Andrea Baschirotto graduated in electronic engi-neering from the University of Pavia, Italy, in 1989.In 1994, he received the Ph.D. degree in electronicengineering from the same University.

In 1994, he joined the Department of Electronicsat the University of Pavia as Assistant Professor. In1998, he joined the Department of Innovation Engi-neering at the University of Lecce, Italy, as AssociateProfessor. From 2007, he is Associate Professor atthe University of Milano-Bicocca, Italy. His researchactivity is focused on the design of CMOS mixed

analog/digital integrated circuits, in particular for low-power and/or high-speedsignal processing.

Dr. Baschirotto was Associate Editor for the IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS II for the period 20002003, and of the IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS I for the period 20042005. Hewas the technical program committee chairman of ESSCIRC 2002 and theguest editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS for ESSCIRC2003. He was the general chair of PRIME 2006, AACD 2008, and of AISEM2009. He has been or is still a member of the technical program committeesof several international conferences, including ISSCC, ESSCIRC, and DATE.Since 2006 he serves as Data Converter Sub-Committee Chair in the ESSCIRCTPC. In 2008 he has been the Secretary of the ISSCC European Committee.Since 2011 he is a member of AACD TPC. He is an IEEE SSCS DistinguishedLecturer. He is an IEEE Senior member.

Angelo Nagari was born in Cilavegna, Pavia, Italy,in 1968. He received the degree in electronic engi-neering (summa cum laude) from the University ofPavia, Italy, in 1993.

He has been with ST-Microelectronics, Milan,Italy, since 1993, where he was involved as a DesignEngineer in the analog and mixed IC developmentfor cellular telecommunications. His main researchinterests are in the fields of Nyquist-rate and over-sampled A/D converters for system-on-chip in audio,RF and auxiliary applications. Since February 2008

he is IP design manager in ST-Ericsson, Grenoble, France. His main role isto define mixed-signal architecture and partitioning for 2.5 G and 3 G mobile

phones (and beyond) and provide IP design in audio and power managementfields. He is a reviewer for several IEEE journals and conferences and, withinST-Ericsson, he holds several patents.

Documents

A 65nm, 1- Buck Converter With Multi-Function SAR-ADC-Based CCM-PSK Digital Control Loop