4.DC Biasing - BJTs (1)

7/28/2019 4.DC Biasing - BJTs (1)

http://slidepdf.com/reader/full/4dc-biasing-bjts-1 1/77

BJTs amplifier requires a knowledge of both the DC analysis(large signal) and AC analysis (small signal).

BJT need to be operate in active region used as amplifier.

The cutoff and saturation region used as a switches.

For the BJTs to be biased in its linear or active operatingregion the following must be true:

a) BE junction forward biased, 0.6 or 0.7V

b) BC junction reverse biased

DC bias analysis assume all capacitors are open circuit.

For transistor amplifiers the resulting DC current and voltage

establish an operating point that define the region that can be

employed for amplification process.

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Important basic relationships for a transistor:

V BE=0.7V

IE=(β+1)I

B≈I

C

IC = βIB

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Operating point quiescent point or Q-point

The biasing circuit can be designed to set the device operation at

any of these points or others within the active region.

The BJT device could be biased to operate outside the max limits,

but the result of such operation would be shortening of the

lifetime of the device or destruction of the device.

The chosen Q-point often depends on the intended use of the

circuit.

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7/28/2019 4.DC Biasing - BJTs (1)


replace the capacitors with an open-circuit equivalent becausethe reactance of a capacitor for dc is ∞Ω

The dc supply V cc can be separated into two supplies

Fixed bias circuit DC equivalent

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B

BECCB

R

V-VI

Write KVL equation in the

clockwise direction of the loop :

+V CC – IBR B – V BE =0

Solving the equation for the

current IB results :

Base-emitter loop B

BE cc B

R

V V I

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The magnitude of the IC is related directly to IB through

IC=βIB

Apply KVL in the clockwise directionaround the indicated close loop results:

V CE+ICR C-V CC=0 V CE = V CC-ICR C

Recall that :

V CE = V C - V E

In this case, V E = 0V, so V CE=V C

V BE=V B-V EThan V E=0V, V BE=V E

Collector –emitter loop

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Determine the following for the fixed bias configurationa) I BQ and I CQ b) V CEQ c) V B and V C d) V BC

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7/28/2019 4.DC Biasing - BJTs (1)


Determine the following for the fixed bias configurationa) IBQ and ICQ b) VCEQ c) VB d)VC e) VE

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V0V)e

V8.17VVd)V

V0.7VV)c

V17.8

k 7.22.93m-16

R I-VV) b

mA93.2u55.3290II

uA55.32k 470

7.016

R

VVI)a

E

CCEQCE

BBE

CCCCCEQ

BQCQ

B

BECCBQ

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The term saturation is applied to any system where levels have reachedtheir max values.

For a transistor operating in the saturation region, the current ismaximum value for a particular design.

Saturation region are normally avoided because the B-C junction is nolonger reverse-biased and the output amplified signal will be distorted.

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By referring to example 1 and the figure, determine thesaturation level.

Solution

limit.the

withinoperatesisIthat theconcluded becanIt.mA34.2Iin1exampleof designThe

mA45.5k 2.2

12

R

VI

CQ

CQ

C

CCCsat

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Find the saturation current for the fixed-bias configuration of figure example 2.

Solution

limit.the

withinoperatesisIthat theconcluded becan

It.mA93.2Iin2exampleof designT he

mA92.5k 7.2

16

R

VI

CQ

CQ

C

CCCsat

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We investigate how the network parameters define the possible

range of Q-points and how the actual Q-point is determined.

Refer to figure below (output loop) one straight line can be drawat output characteristics. This line is called load line.

This line connecting each separate of Q-point. At any point along the load line,

values of IB, IC and V CE can be picked

off the graph.

The process to plot the load line

as follows:

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Step 1:

Refer to circuit, V CE=V CC – ICR C (1)

Choose IC= 0 mA. Subtitute into (1), we get

V CE=V CC (2)

located at X axis Step 2:

Choose V CE=0V and subtitute into (1), we get

IC=V CC/R C (3) located at Y-axis

Step 3: Joining two points defined by (2) + (3), we get straight line that

can be drawn as Fig.

L d Li A l i

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Load-Line Analysis

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Case 1: • Level IB changed by varying the value of RB.

• Q-point moves up and down

L d Li A l i

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Case 2:

• VCC fixed and RC change

the load line will shift as

shown in Fig 5.8

• IB fixed, the Q-point will

move as shown in the same

figure.

Load-Line Analysis

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Case 3:

• RC fixed and VCC varied,

the load line shifts as

shown in Fig.

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Given the load line of Fig. 5.10 and defined Q-point, determine therequired values of V CE, R C and R B for a fixed bias configuration.

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kohm2311

17

7.040I

VV

R

R

V-VI

kohm67.2m15

40

I

VR

0V.VatR VI

mA0IatV40VV

B

BECC

B

B

BECCB

C

CCC

CE

C

CCC

CCCCE

:2Step

:1Step

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Determine the value of Q-point for this figure. Also find the new value

of Q-point if change to 150.

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The DC bias network below contains an emitter resistor to

improve the stability level of fixed-bias configuration. The analysis consists of two scope:

- Examining the base-emitter loop (input loop)

- Use the result to investigate the collector-emitter loop (output

loop)

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7/28/2019 4.DC Biasing - BJTs (1)


7/28/2019 4.DC Biasing - BJTs (1)


For the emitter-bias network for Fig.4.22 determine:

a)IB b)IC c)V CE d)V C e)V E f)V B g)V BC

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required)as biased(reverse

V27.1398.1571.2VVV)g

V71.201.27.0VVV)f

V01.2k 1m01.2R IR IV

OR

V01.297.1398.15VVV)e

V98.1502.420

k 2m01.220R IVV)d

V97.13

03.620k 1k 2m01.220

R R I-VVc)

mA01.21.4050II b)

A1.40k 1150k 430

7.020

R 1R

V-V Ia)

CBBC

EBEB

ECEEE

CEEE

CCCCC

ECCCCCE

BC

EB

BECCB

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The saturation current for an emitter-bias configuration is:

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Determine the saturation current for the network of example 7.

Solution:

This value is about three times the level of ICQ (2.01mA =50)

for the example 7. Its indicate the parameter that been used in

example 7 can be use in analysis of emitter bias network.

mA67.6k 3

20

k 1k 2

20

R R

VI

EC

CCCsat

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Load Line Analysis

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Step 3:

Joining two points defined by (2) + (3), we get straight line that can

be drawn as Fig. 5.17:

Load-Line Analysis

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ICQ and V CEQ from the table is changing dependently the changing

of .

The voltage-divider bias configuration is designed to have a less

dependent or independent of the .

If the circuit parameter are properly chosen, the resulting levels of

ICQ and V CEQ can be almost totally independent of .

I B( A) I C (mA) V CE (V)

50 40.1 2.01 13.97

100 36.3 3.63 9.11

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Two method for analyzedthe voltage-divider biasconfiguration:

- Exact method

- Approximate method

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Step 1:

The input side of thenetwork can be redrawnfor DC analysis.

Step 2: Analysis of Theveninequivalent network to theleft of base terminal

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Step 2(a):

Replaced the voltage sources

with short-circuit equivalent

and gives the value of R TH

21 R R RTH

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Step 2(b):Determining the ETH by replacing the voltage sources andopen circuit Thevenin voltage. Then apply the voltage-divider rule.

21

CC2

2R TH

R R

VR VE

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Step 3:The Thevenin network is then redrawn and IBQ can bedetermined by KVL

0 E E BE TH BTH R I V R I E givesI1βISubtitute BE

ETH

BETH

B

R 1R

VEI

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Determine the DC bias voltage V CE and current IC for the voltage-divider configuration of network below:

47

49

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kohm3.55k 9.3k 39

k 9.3k 39

R R R 21TH

V2

k 9.3k 39

22k 9.3

R R

VR E

21

CC2

TH

A05.6

k 5.11140k 55.3

7.02

R 1R

VE

I ETH

BETH

B

mA85.005.6140II BC

V22.12

k 5.1k 10m85.022

R R IVV ECCCCCE

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For the voltage-divider biasconfiguration,determine:

IBQ, ICQ, V CEQ, V C, V E and V B.

S l ti

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kohm7.93k 1.9k 62

k 1.9k 62

R R R 21TH

V05.2

k 1.9k 62

16k 1.9

R R

VR E

21

CC2

TH

A4.21

k 68.0180k 93.7

7.005.2

R 1R

VEI

ETH

BETH

BQ

mA712.14.2180II BCQ

V16.8

k 68.0k 9.3m712.116

R R IVV ECCCCCEQ

V32.9k 9.3m712.116

R IVV CCCCC

V18.1

k 68.0m712.14.21

k 68.0II

R IV

CB

EEE

V88.1

7.018.1

VVV BEEB

Solution

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Step 1:

R E 10R 2

Step 2:

The input section can be represented by the network of figure below andR 2 can be considered in series by assuming

I1I2 and IB= 0A .

E i

i

R R

I I R R

1

212

This eqn must be satisfied. If not, approximate analysis

can’t be used , and you have to use the exact analysis

(Thevenin’s method)

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21

CC2

R2B

R R

VR VV

:determined becanvoltage baseThe

BEE

EBBE

E

V-VV

V-VV:wellascalculated becanVleveland

B

ECQ

E

E

E IIandR

VI

:determined becan

currentemitter theand

E E R R )1(R where

10R βR

:approacheapproximat

definethat willCondition

i

2E

• Step 3:

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Repeat the analysis of example 9 using the approximatetechnique and compare solution for ICQ and V CEQ.

Solution:

!satisfiedkohm39kohm210

k 9.310k 5.1140

R 10R

:Step1

2E

drawn becancct bias partialthe

:2Step

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V2

k 9.3k 39

22k 9.3

R R

VR V

:3Step

21

CC2

B

V3.17.02

VVV BEBE

mA867.0k 5.1

3.1

R

VII

E

E

ECQ

V03.12

k 5.1k 10m867.022

R R IVV ECCCCCEQ

I CQ

(mA) V CEQ

(V)

Exact

Analysis

0.85 12.22

Approximate

Analysis

0.867 12.03

ICQ and VCEQ are certainly close.

E l

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Repeat the exact analysis of example 9 if is reduced to 70.Compare the solution for ICQ and V CEQ.

Solution: kohm3.55R TH

V2ETH

A81.11

k 5.1170k 55.37.02

R 1R

VEI

ETH

BETH

B

mA83.081.1170II BC

Example

S l ti ( ti d)

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V46.12k 5.1k 10m83.022

R R IVV ECCCCCE

I CQ(mA) V CEQ(V)

140 0.85 12.22

70 0.83 12.46

Conclusion: Even though is drastically half, the level ICQ and VCEQ are essentially same.

Solution (continued)

Example

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Determine the levels of ICQ and VCEQ for the voltage-divider

configuration using the exact and approximate analysis.

Compare the solution.

Example

S l ti

7/28/2019 4.DC Biasing - BJTs (1)


Solution

kohm35.71k 22k 82

k 22k 82

R R R

:AnalysisExact

21TH

V81.3

k 22k 82

18k 22

R R

VR E

21

CC2

TH

A6.39

k 2.1150k 35.17

7.081.3

R 1R VEI

ETH

BETH

BQ

mA98.16.3950IIBCQ

V54.4

k 2.1k 6.5m98.118

R R IVV ECCCCCEQ


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satisfied)(not220kohm60kohm

k 2210k 2.150

R 10R

:AnalysiseApproximat

2E

V81.3

k 22k 82

18k 22

R R

VR EV

21

CC2

THB

V11.37.081.3

VVV BEBE

mA59.2k 2.1

11.3

R

V

II E

E

ECQ

V88.3

k 2.1k 6.5m59.218

R R IVV ECCCCCEQ



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I CQ(mA) %difference V CEQ(V) %difference

Exact

Analysis

1.98

23.5%

4.54

17%

Approximate Analysis

2.59 3.88

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The saturation collector-emitter circuit for the voltage-divider

configuration has the same appearance as the emitter-biased

configuration as shown below.

EC

CCCsat

R R VI

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The similarities with the output circuit of the emitter-biased

configuration result in the same intersections for the load line of the

voltage-divider configuration.

The load line therefore have the same appearance with:

axisYatlocated

R R

VI 0VVCE

EC

CCC

axisXatlocated VV 0mAICCCCE

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Another way to improve the stability of a bias circuit is to add a feedback

path from collector to base. In this bias circuit the Q-point is only slightly

dependent on the transistor Beta .

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Applying Kirchoff’s voltage law:

VCC – ICR C – IBR B – VBE – IERE = 0

Note: IC = IC + IB -- but usually IB << IC so IC IC

Knowing IC = IB and IE IC then:

VCC – IB R C – IBRB – VBE – IBR E = 0

Simplifying and solving for IB:

)R (R R

VVI

ECB

BECCB

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Applying Kirchoff’s voltage law: IERE + VCE + ICRC – VCC = 0

Since IC IC and IC = IB: IC(RC + RE) + VCE – VCC =0

Solving for VCE: VCE = VCC- IC(RC+RE)

)( E C C CC CE

R R I V V

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Transistor Saturation Level

EC

CCCC

R R

VmaxIsatI

Load Line Analysis

It is the same analysis as for the voltage divider bias

and the emitter-biased circuits.

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For the collectorfeedback configuration,determine IB

IC

V C

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(a) I B =

= 15.88 A

(b) I C = I

B = (120)(15.88 A)= 1.91 mA

(c)V C =

V CC

I C

RC = 16 V (1.91 mA)(3.6 k)

= 9.12 V

16 V 0.7 V( ) 470 k + (120)(3.6 k 0.51 k )

CC BE

B C E

V V R R R

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7/28/2019 4.DC Biasing - BJTs (1)


We are able to design the transistor circuit using the ideasthat we have learnt before during analyzing dc biasingcircuit.

How?

- Understand the Kirchoff’s Law and other electriccircuit law such as Ohms Law, Thevenin Laws etc

- Identify the parameters given

- Analyze into the input/output for the system and build

a loop using electric circuit’s law.

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If the transistor and supplies are specified, the designprocess will simply determine the required resistor fora particular design.

Once the theoretical values of the resistors are

determined, the nearest standard commercial valuesare normally chosen and any variations due to notusing the exact resistance values are accepted as part of the design.

R unknown=V R /IR

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Given the device characteristics in figure, determine

V cc, R B and R C for the fixed-bias configuration.

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Given that ICQ = 2 mA and V CEQ = 10V, determine R 1 and R C for the network

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The emitter resistor is ¼ to

1/10 of the supply voltage

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R E and R C cannot proceed directly from the information just specified.

R E – to provide dc bias stabilization so that the change of collector current due to leakage currents in the transistor

and the transistor beta would not cause a large shift inthe operating point.

The R E cannot be unreasonably large because the voltage

across it limits the range of swing of the voltage fromcollector to emitter.

V E – typically ¼ -1/10 from supply voltage

Determine the resistor values for the network, for the

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Determine the resistor values for the network, for theindicated operating point and supply voltage.

Use V E = 1/10 V CC

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The emitter resistor is ¼ to 1/10

of the supply voltage

To determine R1 and R2 use

10R2≤βRE

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Design a voltage divider bias network using a supply of 24V, a transistor with β = 110, and an operating point of ICQ = 4 mA and V CEQ = 8 V. choose V E = 1/8 V CC. Usestandard value.

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RE = = 0.75 k

RC

=

= = 3.25 k

V B

= V E

+ V BE

= 3 V + 0.7 V = 3.7 V

V B

= 2 unknowns!

use RE 10R2 for increased stability

( )QC

CC CE E R CC C

C C C

V V V V V V

I I I

3 V

4 mA

E E

E C

V V

I I

24 V (8 V + 3 V) 24 V 11 V 13 V

4 mA 4 mA 4 mA

2 2

2 1 2 1

(24 V)3.7 V =CC R V R

R R R R

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(110)(0.75 k) = 10R2

R2 = 8.25 k Choose R2 = 7.5 k

Substituting in the above equation:

3.7 V =

R1 = 41.15 k

Standard values:

RE = 0.75 k, RC = 3.3 k, R2 = 7.5 k, R1 = 43 k

1

7.5 k (24 V)

7.5 k R

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• Transistor works as an inverter in computer circuits.

• Operating point switch from cut-off to saturation along the

load line for proper inversion.

• In order to understand, we assume that;

IC=ICEO=0mA when IB = 0µA

VCE=Vsat=0V

• One must understand the transistor graph output and

load-line analysis to describe and discuss about thetransistor switching networks.

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uAmA I

I Therefore

mA R

V

k

V I

I I

Csat B

C

cc

I B

Csat B

8.48125

1.6,

1.6I

63uA68

7.0

that,seellwe'figure,with thecompare

thatensuremustWe

Csat

7/28/2019 4.DC Biasing - BJTs (1)


7/28/2019 4.DC Biasing - BJTs (1)


How to define and encounter transistor circuit problem?

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4.DC Biasing - BJTs (1)