Bjts Dc Biasing

The 1st transistor ever built

Transistor operation

DC biasing-BJTsS.R.R.Govt.Arts & Science College, KNR

Topics objectivesYoull learnQ-point of a transistor operationAbout DC analysis of a transistor circuitAbout Transistor biasing configurationOther available transistor biasing circuitsStability factor for transistorTransistor switching

INTRODUCTION BJTs amplifier requires a knowledge of both the DC analysis (LARGE-signal) and AC analysis (small signal).

For a DC analysis a transistor is controlled by a number of factors including the range of possible operating points.

Once the desired DC current and voltage levels have been

defined, a network must be constructed that will establish thedesired operating point.

BJT need to be operate in active region used as amplifier. The cutoff and saturation region used as a switches. For the BJTs to be biased in its linear or active operating

region the following must be true:a) BE junction forward biased, 0.6 or 0.7Vb) BC junction reverse biased

INTRODUCTION(CONTINUED)

DC bias analysis assume all capacitors are open cct.

AC bias analysis :

1) Neglecting all of DC sources2) Assume coupling capacitors are short cct. The effect of these capacitors is to set a lower cut-off frequency for the cct.3) Inspect the cct (replace BJTs with its small signal model). 4) Solve for voltage and current transfer function and i/o and o/p impedances.

For transistor amplifiers the resulting DC current and voltage establish an operating point that define the region that can be employed for amplification process.

Various operating points within the limits of operation of a transistorQ-point A:I=0A, V=0VNot suitable for

transistor to operate Q-point B: The best operating point

for linear gain and largestpossible voltage and current It is a desired condition for

a small signal analysisQ-point C: Concern on

nonlinearities due to IB curves is rapidly changes in this region.

15

18

12

9

6

3

IC(mA)

VCE(V)

IB=60 uA

10

20

30

IB=50 uA

IB=0 uA

IB=40 uA

IB=30 uA

IB=20 uA

IB=10 uA

40

A

C

B

VCEsat

PCmax

ICmax

VCEmax

Cutoff

Saturation

FIXED-BIAS CCTAC ANALYSISDC ANALYSIS

AC input signal

AC output signal

RB

RC

B

C

E

VBE

VCE

+

+

-

-

C1

C2

C1,C2 = coupling capacitors

VCC

IC

IB

VCC

RB

RC

B

C

E

VBE

VCE

+

+

-

-

VCC

IC

IB

EMITTER-STABILIZED BIAS CCT

Voltage divider bias

Vi

Vo

RC

C1

C2

VCC

R2

R1

Fig. 5.18: Voltage-divider bias configuration

RE

Forward Bias of Base-Emitter Refer to fig. 5.1. This cct also known as input loop.

Fig. 5.1 : Base-emitter loop

RB

B

C

E

VBE

VCE

+

+

-

-

+

-

IB

VCC

Collector-Emitter Loop Refer to fig. 5.2. Also known as output loop.

The value of IC, IB and VCE shows the position of Q-point at o/p graph. The notation of this value changes to ICQ, IBQ and VCEQ.

RC

Fig. 5.2 : Collector-emitter loop

C

+

-

VCE

+

-

VCC

IC

Example 1:Determine the following for the fixed bias configuration of Fig 5.3.a) IBQ and ICQb) VCEQc) VB and VC d) VBC

AC input signal

AC output signal

RB=240kohm

RC=2.2kohm

B

C

E

VBE

VCE

+

+

-

-

C1

C2

VCC=+12V

IC

IB

10uF

10uF

Fig. 5.3

Solution

Example 2:Determine the following for the fixed bias configuration of Fig 5.4.a) IBQ and ICQb) VCEQc) VB d)VC e) VE

RC=2.7kohm

B

C

E

VBE

VCE

+

+

-

-

VCC=+16V

IC

IB

RB=470kohm

Fig. 5.4

Solution

Transistor Saturation Saturation means the level of systems have reached their maximum values. For a transistor operating in the saturation region, the current is maximum value for a particular design. Saturation region are normally avoided because the B-C junction is no longer reverse-biased and the o/p amplified signal will be distorted. Fig 5.5 shows the schematic diagram to determine ICsat for the fixed-bias configuration.

The saturation current for the fixed bias configuration is:

RC

VCE=0V

+

+

-

-

VCC

VRC=VCC

ICsat

RB

Fig. 5.5

Example 3:By refering to example 1 and Fig. 5.3 determine the saturation level.

Solution:

Example 4:Find the saturation current for the fixed-bias configuration of Fig. 5.4.

Solution:

Load line analysis By refering to Fig. 5.2 (output loop) one straight line can be draw at output characteristics. This line is called load line. This line connecting each separate of Q-point. At any point along the load line, values of IB, IC and VCE can be picked off the graph. The process to plot the load line as follows:

Step 1: Refer to fig. 5.2, VCE=VCC ICRC(1)Choose IC=0 mA. Subtitute into (1), we get

VCE=VCC (2) located at X axis

Step 2: Choose VCE=0V and subtitute into (1), we getIC=VCC/RC (3) located at Y-axisStep 3: Joining two points defined by (2) + (3), we get straight line that can be drawn as Fig. 5.6.

VCC

IBQ

Q-point

VCE=0 V

Fig. 5.6

IC(mA)

VCE(V)

Load line

VCC/RC

IC=0 mA

Case 1:

Level IB changed by varying the value of RB. Q-point moves up and down

IC(mA)

VCE(V)

Q-point

VCC/RC

Q-point

IBQ3

VCC

IBQ2

Q-point

IBQ1

Fig. 5.7:Movement of Q-point with increasing levels of IB

Case 2:

VCC fixed and RC change the load line will shift as shown in Fig 5.8 IB fixed, the Q-point will move as shown in the same figure.

IC(mA)

VCE(V)

VCC/RC1

VCC

IBQ

Q-point

Fig. 5.8 : Effect of increasing levels of RC on the load line and Q-point

Q-point

Q-point

RC3 > RC2 > RC1

VCC/RC2

VCC/RC3

Case 3:

RC fixed and VCC varied, the load line shifts as shown in Fig. 5.9

IC(mA)

VCE(V)

VCC1/RC

VCC1

IBQ

Q-point

Fig. 5.9: Effect of lower values of VCC on the load line and Q-point

Q-point

Q-point

VCC2/RC

VCC3/RC

VCC2

VCC3

VCC1 > VCC2 > VCC3

Example 5:Given the load line of Fig. 5.10 and defined Q-point, determine the required values of VCE, RC and RB for a fixed bias configuration.

15

18

12

9

6

3

IC(mA)

VCE(V)

IB=60 uA

10

20

30

IB=50 uA

IB=0 uA

IB=40 uA

IB=30 uA

IB=20 uA

IB=10 uA

40

Fig. 5.10

Q-point

ICmax

Solution:

Example 6:Determine the value of Q-point for Fig. 5.11. Also find the new value of Q-point if change to 150.

Solution:The change of cause the big change ofQ-point value. This shows that fixed biased configuration is NOT stable

EMITTER-STABILIZED BIAS CCT The DC bias network of Fig 5.12 contains an emitter resistor to improve the stability level of fixed-bias configuration. The analysis consists of two scope:Examining the base-emitter loop (i/p loop)Use the result to investigate the collector-emitter loop (o/p loop)

Base-Emitter Loop (i/p loop) Refer to fig. 5.12.

Collector-Emitter Loop (o/p loop) Refer to fig. 5.13.

RC

C

VCE

+

-

VCC

IC

Fig. 5.13 : Collector-emitter loop

+

-

IE

RE

Example 7:For the emitter-bias network fo Fig.5.14 determine:a)IB b)IC c)VCE d)VC e)VE f)VB g)VBC

RC=2 kohm

RE=1 kohm

VCC=+20V

IC

IB

RB=430kohm

Fig. 5.14

IE

Solution:

Improved Bias Stability Issues: Comparison analysis for example 1 and example 7.Data from example 1 (fixed-bias configuration)Data from example 7 (emitter-bias configuration)

IB(A)IC(mA)VCE(V)5047.082.356.8310047.084.711.64

IB(A)IC(mA)VCE(V)5040.12.0113.9710036.33.639.11

Takehome exercise:For the emitter-stabilized biase cct of Fig. 5.15, determine IBQ, ICQ, VCEQ, VC, VB, VE.

RC=2.4 kohm

RE=1.5 kohm

VCC=+20V

IC

IB

RB=510kohm

Fig. 5.15

IE

The saturation current for an emitter-bias configuration is: Saturation

RC

VCE=0V

+

-

VCC

ICsat

Fig. 5.16

+

-

RE

Example 8:Determine the saturation current for the network of example 7.

Solution:

This value is about three times the level of ICQ (2.01mA =50) for the example 7. Its indicate the parameter that been used in example 7 can be use in analysis of emitter bias network.

Load line analysis The process to plot the load line as follows:

Step 1: Refer to fig. 5.13, VCE=VCC IC(RC+RE)(1)Choose IC=0 mA. Subtitute into (1), we get

VCE=VCC (2) located at X axisStep 2: Choose VCE=0V, subtitute into (1) gives

Step 3: Joining two points defined by (2) + (3), we get straight line that can be drawn as Fig. 5.17:

IC

VCE(V)

VCC/(RC+RE)

VCC

IBQ

Q-point

Fig. 5.17: Load line for the emitter-bias configuration

VCEQ

ICQ

VOLTAGE-DIVIDER BIASData from example 7ICQ and VCEQ from the table of example 7 is changing

dependently the changing of .The voltage-divider bias configuration such as in Fig.

5.18 is designed to have a less dependent or independent ofthe .If the cct parameter are properly choosen, the resulting

levels of ICQ and VCEQ can be almost totally independentof .

IB(A)IC(mA)VCE(V)5040.12.0113.9710036.33.639.11

Two method for analyzed the voltage-divider bias configuration:

Exact methodApproximate method

Vi

Vo

RC

C1

C2

VCC

R2

R1

Fig. 5.18: Voltage-divider bias configuration

RE

Exact AnalysisStep 1:The i/p side of the network of Fig. 5.18 can be

redrawn as shown in Fig. 5.19 for DC analysis.

Step 2:Analysis of Thevenin equivalent network to the left of

base terminal

Thevenin

VCC

R1

RE

R2

Fig. 5.19: Redrawn the i/p side of the network of Fig 5.18

Exact AnalysisStep 2(a):Replaced the voltage sources with short-cct equivalent as shown in Fig 5.20 and gives us the value of RTH

R1

R2

RTH

Fig. 5.20: Determining RTH

Exact AnalysisStep 2(b):Determining the ETH by replaced back the voltage sources and open cct Thevenin voltage as shown in Fig. 5.21. Then apply the voltage-divider rule.

VR2

+

-

R1

ETH

+

-

Fig. 5.21: Determining ETH

R2

VCC

Exact AnalysisStep 3:The Thevenin network is then redrawn as shown in Fig. 5.22and IBQ can be determined by KVL

Example 9:Determine the DC bias voltage VCE and current IC for the voltage-divider configuration of network below:

Solution:

Example 10: For the voltage-divider bias configuration ofFig. 5.23, determine: IBQ, ICQ, VCEQ, VC, VE and VB.

RC=3.9kohm

VCC=16V

R2=9.1kohm

R1=62kohm

Fig. 5.23

RE=0.68kohm

ICQ

IBQ

Solution:

Approximate AnalysisStep 1:RE 10R2 Step 2:The i/p section can be represented by the network of Fig.5.24. R1 and R2 can be considered in series by assumingI1I2 and IB= 0A .

R1

Ri

R2

Fig. 5.24: Partial-bias cct for calculating the approximate base voltage, VB

VCC

I1

I2

IB

VB

+

-

Approximate AnalysisStep 3:

R1

Ri

R2

Fig. 5.24: Partial-bias cct for calculating the approximate base voltage, VB

VCC

I1

I2

IB

VB

+

-

NPN Transistor simulation

Example 11:Repeat the analysis of example 9 using the approximate technique and compare solution for ICQ andVCEQ.

Solution:

ICQ and VCEQ are certainly close.

ICQ(mA)VCEQ(V)Exact Analysis0.8512.22Approximate Analysis0.86712.03

Example 12:Repeat the exact analysis of example 9 if isreduced to 70. Compare the solution for ICQ and VCEQ.

Solution:

Conclusion: Even though is drastically half, the level ICQ and VCEQ are essentially same.Solution (continued):

ICQ(mA)VCEQ(V)1400.8512.22700.8312.46

Example 13:Determine the levels of ICQ and VCEQ for the voltage-divider configuration fo Fig. 5.25 using the exact and approximate analysis. Compare the solution.

RC=5.6kohm

VCC=18V

R2=22kohm

R1=82kohm

Fig. 5.25

RE=1.2kohm

ICQ

IBQ

Solution:

Solution (continued):

Solution (continued):

ICQ(mA)%differenceVCEQ(V)%differenceExact Analysis1.9823.5%4.5417%Approximate Analysis2.593.88

The saturation collector-emitter cct for the voltage-dividerconfiguration has the same appearance as the emitter-biased configuration as shown in Fig. 5.27

RC

VCE=0V

+

-

VCC

ICsat

Fig. 5.27

+

-

RE

Load line analysis

The similarities with the o/p cct of the emitter-biased configuration result in the same intersections for the load line of the voltage-divider configuration.

The load line therefore have the same appearance with:

DC Bias with Voltage BiasingAnother way to improve the stability of a bias circuit is to add a feedback path from collector to base. In this bias circuit the Q-point is only slightly dependent on the transistor Beta .

Applying Kirchoffs voltage law: VCC ICRC IBRB VBE IERE = 0

Note: IC = IC + IB -- but usually IB

Collector-Emitter LoopApplying Kirchoffs voltage law: IE + VCE + ICRC VCC = 0

Since IC IC and IC = IB: IC(RC + RE) + VCE VCC =0

Solving for VCE:

Transistor Saturation LevelLoad Line AnalysisIt is the same analysis as for the voltage divider bias and the emitter-biased circuits.

Simulation of a NPN type common-emitter transistor

Design OperationWe are able to design the transistor circuit using the ideas that we have learnt before during analyzing dc biasing circuit.How?Understand the Kirchofs Law and other electric circuit law such as Ohms Law, Thevenin Laws etcIdentify the parameters givenAnalyze into the input/output for the system and build a loop using electric circuits law.

Miscellaneous configuration

Examples

Examples of designDesign of a bias circuit with an emitter feedback resistorDesign of a current-gain-stabilized circuit (beta independent)

Design of a bias circuit with an emitter feedback resistorThe emitter resistor is to 1/10 of the supply voltage

Design of a current-gain-stabilized circuit (beta independent)

Transistor as switching networksTransistor works as an inverter in computer circuits.Operating point switch from cut-off to saturation along the load line for proper inversion.In order to understand, we assume that;IC=ICEO=0mAVCE=Vsat=0VOne must understand the transistor graph output and load-line analysis to describe and discuss about the transistor switching networks.

Transistor as a switch

Time interval

Time interval continued

Troubleshooting?How to define and encounter transistor circuit problem?

PNP configuration

Bias stabilizationStability of a system is a measure of the sensitivity of a network to variation in its parameter. increases with increase in temperatureVBE decreases 7.5mV every degree celciusICO doubles every 10 oC increase in temperature

Effect of non-stability circuit/systemRoom temperature100oC temperatureWell find that increase after 100OC, base current is same but not suitable to use due it is very near to the saturation region.

Stability factorsEmitter bias configuration

S(ICO)

Fixed bias configuration

Voltage divider bias configuration

S(ICO)

Feedback bias configuration

S(ICO)Physical impact

Fixed bias configuration ; IC=IB+(+1)ICO...IC increase but IB maintain, so its not stableEmitter bias configuration ; Increase IC will increase ICO. It affect VE since VE=IERE=ICRE. In turn, the output loop will inform that IB will decrease if VE is increase, thus affect to reduce the collector current.Feedback bias configuration ; same as result of emitter bias configuration where IB will decrease if IC increase. (IC proportional to VRC)Voltage divider bias configuration ; Most stable where as long as 10R2>> RE, VB remain constant for any changing in IC.

S(VBE)S()

References:

Thomas L. Floyd, Electronic Devices, Sixth edition, Prentice Hall, 2002. Robert Boylestad, Electronic Devices and Circuit Theory, Eighth edition, Prentice Hall, 2002.

3. Puspa Inayat Khalid, Rubita Sudirman, Siti Hawa Ruslan, ModulPengajaran Elektronik 1, UTM, 2002.4. Website : http://www2.eng.tu.ac.th

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Bjts Dc Biasing