2 Synchronous Sequential Logic (1)

8/9/2019 2 Synchronous Sequential Logic (1)

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Synchronous

sequential logics

NCBA&E : National College of

BusinessAdministration & Economics


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Synchronous sequential logic

Key concepts and Overview• multivibrator

• Signal edge

• Synchronous sequential logic• Flip op

• S!" latch

• S!" !NAN# latch

• $% latch• Gated SR latch

• #!ipop


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here are t'o types of sequential circuits:

synchronous: outputs change only at specifc timeasynchronous: outputs change at any time use (multivibrator )

A multivibrator is an electronic circuit used to implement avariety of simple t'o!state systems such as oscillators( timersand ip!ops) *t is characteri+ed by t'o amplifying devices

,transistors( electron tubes or other devices- cross!coupled byresistors or capacitors)

.ultivibrator: a class of sequential circuits) hey can be:bistable,/ stable states-monostableor one!shot,0 stable state-

astable,no stable state-

Bistable logic devices: latchesand ip!ops)

1atches and ip!ops di2er in the method used for changing their state)

SYNCHONO!S S"#!"N$%&''O%C


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he current *ntel 3entium *4 processors have 55 million

transistors6

A fip-fop holds a single bit o memory he bit 7ip!ops8 bet'een the t'o NAN# gates

In reality, fip-fops are a bit more complicated 9ave 5 ,or so- logic gates ,transistors- per ip!op

Consider a 1 Gb memory chip

0 b ; million transistors6

In reality, those transistors are split into 9 ICs oabout 5 million transistors each

S"#!"N$%&' C%C!%$


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*N E1EC"N*CS( A S*NA1 E#E *S A "ANS**N *N A #**A1 S*NA1 E*9E"F". 1 9*9 , 0- " F". 9*9 1 ,0 -) * *S CA11E# ANDE#ED BECASE 9E SA"E A4E 9*C9 "E3"ESENS A S*NA1 9AS E#ES

A 9SE 3*NS)

A rising edge is the transition from lo' to high) *t is also named positive edge)hen a circuit is rising edge!triggered( it becomes active 'hen its cloc% signalgoes from lo' to high( and ignores the high!to!lo' transition)

A falling edge is the high to lo' transition) *t is also %no'n as the negative edge)

hen a circuit is falling edge!triggered( it becomes active 'hen the cloc% signalgoes from high to lo'( and ignores the lo'!to!high transition)

A leading edge is an event that is triggered on the front edge of a pulse) Assuminga cloc% begins at t ; ( the Grst position 'ould be triggered at t ; 0)

A trailing edge is the opposite of a leading edge) *t is triggered on the bac% edgeof a pulse) Assuming the cloc% begins at t ; ( the Grst position 'ould be triggeredat t ; )

he terms front edge or leading edge( and bac% edge or trailing edge describe therelated position of edges in a cloc% cycle) A leading edge can be a falling edge)

S%N&' ""


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1atches and ip!ops ,FFs- are the basic buildingbloc%s of sequential circuits

'atches :bistable memory device 'ith level sensitivetriggering ,no cloc%-( 'atches all of its inputs

continuously and changes its outputs( independent ofa cloc%ing signal)r

a latch is a device that after ta%ing a single input for say 0 they set theiroutput to 0 and hold its state until it resets

*ip+*op: bistable memory device 'ith edge!triggering ,'ith cloc%-( samples its inputs( andchanges its output only at times determined by acloc%ing signal)r

SYNCHONO!S S"#!"N$%&''O%C


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Flip op is a sequential circuit 'hich generallysamples its inputs and changes its outputs only atparticular instants of time and not continuously) Flipop is said to be edge sensitive or edge triggeredrather than being level triggered li%e latches)

Flip!ops can be divided into common types:the S (,set+reset,) (,data, or ,delay,-../)$ (,toggle,)

0K types are the common ones

1lip *op


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S and " stand for set and reset) *t can be constructed from a pair of cross!coupledN" logic gates) he stored bit is present on the output mar%ed )hile the S and " inputs are both lo'( feedbac% maintains the and outputs in

a constant state( 'ith the complement of ) *f S ,Set- is pulsed high 'hile ","eset- is held lo'( then the output is forced high( and stays high 'hen Sreturns to lo'H similarly( if " is pulsed high 'hile S is held lo'( then the output isforced lo'( and stays lo' 'hen " returns to lo')The ! " ! 1 combination is called a restricted combination or a orbidden statebecause, as both #$ gates then output %eros, it brea&s the logical e'uation ( !not () The combination is also inappropriate in circuits *here both inputs may go

lo* simultaneously +i)e) a transition rom restricted to &eep) The output *ouldloc& at either 1 or depending on the propagation time relations bet*een thegates +a race condition-)

S+ latch


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S+ +NAN# latch :*t is basically S!" latch using NAN# gates 'ithan additional enable input) *t is also called as level triggered S"!FF) Forthis circuit in output 'ill ta%e place if and only if the enable input ,E- is

made active) *n short this circuit 'ill operate as an S!" latch if E; 0 butthere is no change in the output if E ; )hile the S and " inputs are both lo'( feedbac% maintains the and outputs ina constant state( 'ith the complement of ) *f S ,Set- is pulsed high 'hile ","eset- is held lo'( then the output is forced high( and stays high 'hen Sreturns to lo'H similarly( if " is pulsed high 'hile S is held lo'( then the output isforced lo'( and stays lo' 'hen " returns to lo')


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O2"&$%ON


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0K latch he $I latch is much less frequently used than the $I ip!op) he $I latch follo'sthe follo'ing state table:9ence( the $I latch is an S" latch that is

made to toggle its output ,oscillatebet'een and 0- 'hen passed the inputcombination of 00) nli%e the $I ip!op(the 00 input combination for the $I latch is not very useful because there is no cloc% that directs toggling)

ated latches and conditional transparency1atches are designed to be transparent) hat is( input signal changes causeimmediate changes in outputH 'hen several transparent latches follo' each other(using the same enable signal( signals can propagate through all of them at once)Alternatively( additional logic can be added to a simple transparent latch to ma%e

it non!transparent or opaque

0K latch truth ta3le

0 K #ne4t Comment

Nochange

0 "eset

0 0 Set0 0 oggle


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Gated SR latch

A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second

level of NAN gates to the inverted SR latch (or a second level of AN gates to the direct SR

latch)! "he e#tra NAN gates further invert the inputs so the simple SR latch becomes a

gated SR latch (and a simple SR latch $ould transform into a gated SR latch $ith invertedenable)!

%ith & high (enable true)' the signals can pass through the input gates to the encapsulated

latch all signal combinations e#cept for (') * hold then immediately reproduce on the (+'+)

output' i!e! the latch is transparent!

%ith & lo$ (enable false) the latch is closed (opa,ue) and remains in the state it $as left thelast time & $as high!

"he enable input is sometimes a clock signal' but more often a read or $rite strobe

!

No action ,%eep state-

0 he same as non!cloc%ed S"latch

http://en.wikipedia.org/wiki/File:SR_(Clocked)_Flip-flop_Diagram.svg


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D flip-flop The d-ff captures the value of the D-input at a definite portion of the clockcycle (such as the rising edge of the clock). That captured value becomes the Q output. At

other times, the output Q does not change

ost D-type flip-flops in !"s have the capability to be forced to the set or reset state (#hich

ignores the D and clock inputs), much like an $% flip-flop. &sually, the illegal $ ' % '

condition is resolved in D-type flip-flops. y setting $ ' % ' *, the flip-flop can be used as

described above. +ere is the truth table for the others $ and % possible configurations

Cloc% # neKt"isingedge

"isingedge

0 0

Non!"ising

L

1lip+1lop 5rom N&N 'atch


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D flip-flop

ne of the main disadvantages of the basic sr nand gate bistable circuitis that the indeterminate input condition of 7SE8 ; logic 78 and7"ESE8 ; logic 78 is forbidden)

his state 'ill force both outputs to be at logic 708( over!riding thefeedbac% latching action and 'hichever input goes to logic level 708 Grst'ill lose control( 'hile the other input still at logic 78 controls theresulting state of the latch)But in order to prevent this from happening an inverter can beconnected bet'een the 7SE8 and the 7"ESE8 inputs to produceanother type of ip op circuit

1lip+1lop 5rom N&N 'atch


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hat inverter is Ino'n as a data latch( delay *ip*op( d+type 3ista3le( d+type *ip *op or Must simplya *ip *op as it is more generally called)

he *ip *op is by far the most important of thecloc%ed ip!ops as it ensures that ensures thatinputs S and " are never equal to one at the sametime) he d!type ip op are constructed from agated S" ip!op 'ith an inverter added bet'een

the S and the " inputs to allo' for a single # ,data-input)

hen this single data input( labelled #( is used in placeof the 7set8 signal( and the inverter is used to

generate the complementary 7reset8 input therebyma%ing a level!sensitive d!type ip!op from a level!sensitive rs!latch as no' S ; # and " ; not # assho'n)

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2 Synchronous Sequential Logic (1)