JJ Shann

Chapter 6

(Synchronous) Sequential Circuits

JJ Shann 6-2

Contents

6-1 Sequential Circuit Definitions6-2 Latches6-3 Flip-Flops6-6 Other Flip-Flop Types6-4 Sequential Circuit Analysis6-5 Sequential Circuit Design6-7 HDL Representation for Sequential Circuitsmdash

VHDL (times)6-8 HDL Representation for Sequential Circuitsmdash

Verilog (times)6-9 Chapter Summary

JJ Shann 6-3

6-1 Sequential Circuit Definitions

Combinational circuit no memory elements(inputs) rArr (outputs)

Sequential circuit

mdash storage elements devices capable of storing binary information (state)

mdash (inputs present state) rArr (outputs next state)

JJ Shann 6-4

Logic structures for storing informationmdash Egs

JJ Shann 6-5

Types of Sequential Circuits

Classificationmdash depends on the timing of their signals

Two main types1 Synchronous seq ckt

ndash Its behavior can be defined from the knowledge of its signals at discrete instants of time

ndash Storage elements eg flip-flops

2 Asynchronous seq ckt (補充資料)ndash Its behavior depends upon the input signals at any instant of

time and the order in which the inputs changendash Storage elements eg latches feedback pathsndash Disadv may be unstable amp difficult to design

JJ Shann 6-6

Synchronous Sequential Circuits

Clocked seq ckts most commonly used sync seq cktsmdash is syn seq ckts that use clock pulses in the inputs of storage elementsmdash has a master-clock generator to generate a periodic train of clock

pulsesThe clock pulses are distributed throughout the systemStorage elements are affected only w the arrival of each pulse

mdash Adv seldom manifest instability problemsmdash Storage elements flip-flops

flip-flop a binary cell capable of storing one bit of informationThe state of a flip-flop can change only during a clock pulse transition rArr The transition from one state to the next occurs only at

predetermined time intervals dictated by the clock pulses

JJ Shann 6-7

Clock pulses

Flip-flops

Block diagram of a sequential ckt

(Optional)

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-2

Contents

6-1 Sequential Circuit Definitions6-2 Latches6-3 Flip-Flops6-6 Other Flip-Flop Types6-4 Sequential Circuit Analysis6-5 Sequential Circuit Design6-7 HDL Representation for Sequential Circuitsmdash

VHDL (times)6-8 HDL Representation for Sequential Circuitsmdash

Verilog (times)6-9 Chapter Summary

JJ Shann 6-3

6-1 Sequential Circuit Definitions

Combinational circuit no memory elements(inputs) rArr (outputs)

Sequential circuit

mdash storage elements devices capable of storing binary information (state)

mdash (inputs present state) rArr (outputs next state)

JJ Shann 6-4

Logic structures for storing informationmdash Egs

JJ Shann 6-5

Types of Sequential Circuits

Classificationmdash depends on the timing of their signals

Two main types1 Synchronous seq ckt

ndash Its behavior can be defined from the knowledge of its signals at discrete instants of time

ndash Storage elements eg flip-flops

2 Asynchronous seq ckt (補充資料)ndash Its behavior depends upon the input signals at any instant of

time and the order in which the inputs changendash Storage elements eg latches feedback pathsndash Disadv may be unstable amp difficult to design

JJ Shann 6-6

Synchronous Sequential Circuits

Clocked seq ckts most commonly used sync seq cktsmdash is syn seq ckts that use clock pulses in the inputs of storage elementsmdash has a master-clock generator to generate a periodic train of clock

pulsesThe clock pulses are distributed throughout the systemStorage elements are affected only w the arrival of each pulse

mdash Adv seldom manifest instability problemsmdash Storage elements flip-flops

flip-flop a binary cell capable of storing one bit of informationThe state of a flip-flop can change only during a clock pulse transition rArr The transition from one state to the next occurs only at

predetermined time intervals dictated by the clock pulses

JJ Shann 6-7

Clock pulses

Flip-flops

Block diagram of a sequential ckt

(Optional)

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-3

6-1 Sequential Circuit Definitions

Combinational circuit no memory elements(inputs) rArr (outputs)

Sequential circuit

mdash storage elements devices capable of storing binary information (state)

mdash (inputs present state) rArr (outputs next state)

JJ Shann 6-4

Logic structures for storing informationmdash Egs

JJ Shann 6-5

Types of Sequential Circuits

Classificationmdash depends on the timing of their signals

Two main types1 Synchronous seq ckt

ndash Its behavior can be defined from the knowledge of its signals at discrete instants of time

ndash Storage elements eg flip-flops

2 Asynchronous seq ckt (補充資料)ndash Its behavior depends upon the input signals at any instant of

time and the order in which the inputs changendash Storage elements eg latches feedback pathsndash Disadv may be unstable amp difficult to design

JJ Shann 6-6

Synchronous Sequential Circuits

Clocked seq ckts most commonly used sync seq cktsmdash is syn seq ckts that use clock pulses in the inputs of storage elementsmdash has a master-clock generator to generate a periodic train of clock

pulsesThe clock pulses are distributed throughout the systemStorage elements are affected only w the arrival of each pulse

mdash Adv seldom manifest instability problemsmdash Storage elements flip-flops

flip-flop a binary cell capable of storing one bit of informationThe state of a flip-flop can change only during a clock pulse transition rArr The transition from one state to the next occurs only at

predetermined time intervals dictated by the clock pulses

JJ Shann 6-7

Clock pulses

Flip-flops

Block diagram of a sequential ckt

(Optional)

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-4

Logic structures for storing informationmdash Egs

JJ Shann 6-5

Types of Sequential Circuits

Classificationmdash depends on the timing of their signals

Two main types1 Synchronous seq ckt

ndash Its behavior can be defined from the knowledge of its signals at discrete instants of time

ndash Storage elements eg flip-flops

2 Asynchronous seq ckt (補充資料)ndash Its behavior depends upon the input signals at any instant of

time and the order in which the inputs changendash Storage elements eg latches feedback pathsndash Disadv may be unstable amp difficult to design

JJ Shann 6-6

Synchronous Sequential Circuits

Clocked seq ckts most commonly used sync seq cktsmdash is syn seq ckts that use clock pulses in the inputs of storage elementsmdash has a master-clock generator to generate a periodic train of clock

pulsesThe clock pulses are distributed throughout the systemStorage elements are affected only w the arrival of each pulse

mdash Adv seldom manifest instability problemsmdash Storage elements flip-flops

flip-flop a binary cell capable of storing one bit of informationThe state of a flip-flop can change only during a clock pulse transition rArr The transition from one state to the next occurs only at

predetermined time intervals dictated by the clock pulses

JJ Shann 6-7

Clock pulses

Flip-flops

Block diagram of a sequential ckt

(Optional)

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-5

Types of Sequential Circuits

Classificationmdash depends on the timing of their signals

Two main types1 Synchronous seq ckt

ndash Its behavior can be defined from the knowledge of its signals at discrete instants of time

ndash Storage elements eg flip-flops

2 Asynchronous seq ckt (補充資料)ndash Its behavior depends upon the input signals at any instant of

time and the order in which the inputs changendash Storage elements eg latches feedback pathsndash Disadv may be unstable amp difficult to design

JJ Shann 6-6

Synchronous Sequential Circuits

Clocked seq ckts most commonly used sync seq cktsmdash is syn seq ckts that use clock pulses in the inputs of storage elementsmdash has a master-clock generator to generate a periodic train of clock

pulsesThe clock pulses are distributed throughout the systemStorage elements are affected only w the arrival of each pulse

mdash Adv seldom manifest instability problemsmdash Storage elements flip-flops

flip-flop a binary cell capable of storing one bit of informationThe state of a flip-flop can change only during a clock pulse transition rArr The transition from one state to the next occurs only at

predetermined time intervals dictated by the clock pulses

JJ Shann 6-7

Clock pulses

Flip-flops

Block diagram of a sequential ckt

(Optional)

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-6

Synchronous Sequential Circuits

Clocked seq ckts most commonly used sync seq cktsmdash is syn seq ckts that use clock pulses in the inputs of storage elementsmdash has a master-clock generator to generate a periodic train of clock

pulsesThe clock pulses are distributed throughout the systemStorage elements are affected only w the arrival of each pulse

mdash Adv seldom manifest instability problemsmdash Storage elements flip-flops

flip-flop a binary cell capable of storing one bit of informationThe state of a flip-flop can change only during a clock pulse transition rArr The transition from one state to the next occurs only at

predetermined time intervals dictated by the clock pulses

JJ Shann 6-7

Clock pulses

Flip-flops

Block diagram of a sequential ckt

(Optional)

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-7

Clock pulses

Flip-flops

Block diagram of a sequential ckt

(Optional)

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-8

6-2 Latches

Latchesmdash are asynchronous seq cktsmdash are the basic ckts from which all flip-flops are

constructed

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-9

A SR and SR Latches

SR latchSR latchSR latch w control input

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-10

SR latch w NOR gates

mdash Useful states Set state Q = 1 Q = 0Reset state Q = 0 Q = 1

mdash Undefined states Q = Q

SR Latch

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

Q the normal output Q the complement output

AsyncSeq Ckt

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-11

(Case 1)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

1

rarr 0

0

1

rarr 1

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-12

(Case 2)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

0

1

0

1

rarr 0

rarr 1

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-13

(Case 3)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

1

0

1

0

1

0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 1

rarr 0

rarr 1

rarr 0

rarr 1

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-14

(Case 4)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q + 0 0 N o ch ange (Q + = Q ) 0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

1

1

0

1

0

1

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

rarr 0

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-15

(Case 4+)

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

0

0

0

0

0

0

rarr 1

rarr 1

rarr 1

rarr 1

rarr 0

rarr 0

rarrhellip

rarrhellip

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-16

Summary

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

0 00 0

0 11 0

1 1

0 11 0

0 11 0

0 0

Q+ Q+Q QS R

S R Q+ 0 0 No change (Q+ = Q) 0 1 Reset (Q+ = 0) 1 0 Set (Q+ = 1) 1 1 Indeterminate

Q+ next state of Q

)()(prime+=

prime+=+

+

QSQQRQ

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-17

Logic simulation of SR latch behavior

S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate

Q + n ext sta te o f Q

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-18

S R Latch

S R latch w NAND gates

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-19

1 01 0

0 11 0

1 0

0 10 1

0 11 0

0 1

1 11 1

0 11 0

0 0

0 11 0

0 11 0

1 1

Q+ Q+Q QS R

S R Q +

1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate)(

)(primesdot=

primesdot=+

+

QRQQSQ

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-20

SR Latch w Control Input

SR latch w control input

mdash The indeterminate condition makes this ckt difficult to manage amp it is seldom used in practice

mdash It is an important ckt (other latches amp flip-flops are constructed from it)

S

R

enable signal 1== RS

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-21

B D Latch

D latchD latch w transmission gates

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-22

D Latch

D latch (w control input)

Disadv of a latch w control inputmdash The state of latch may keep changing for as long as the

control input stays in the active level

S

R

1 (Set)1 1 01 10 (Reset)1 0 11 0Q (No change)0 X X0 X

Q+C S RC D

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-23

D latch w transmission gates

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-24

D latch w transmission gates

1

times

D Dprime

D

D

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-25

D latch w transmission gates

0

timesD Dprime

D

D+

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-26

6-3 Flip-Flops

Flip-flop vs Latchmdash Latch w control input

can change state in response to the inputs anytime the control input is in the active levelrArr The latch is controlled by the ldquolevelrdquo of its control input

mdash Flip-flopresponses only to a ldquotransitionrdquo of a triggering input called the ldquoclockrdquoPositive-edge trigger 0 rarr 1Negative-edge trigger 1 rarr 0

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-27

Clock response in latch amp flip-flop

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-28

Latch rarr Flip-flop1 Master-slave flip-flop pulse-triggered f-f

Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing

2 Edge-triggered flip-flopProduce a flip-flop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-29

A Master-Slave Flip-Flops

SR master-slave flip-flop

Slave disable

Master enabled goes to state determined by S amp R inputs

Slave enabled goes to state determined by output of master (Y)

Master disable

Slave disable

Q may change only during the negative edge of the clock

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-30

Logic simulation of an SR master-slave flip-flop

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-31

Master-slave D f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-32

B Edge-Triggered Flip-Flop

Master-slave f-f rarr Edge-triggered f-f

Negativeedge-triggered

D flip-flop

Positiveedge-triggered

D flip-flop

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-33

補充資料D-Type Positive-Edge-Triggered Flip-Flop (p6-27~6-32)

S

R

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-34

When clock is LOW

No change0

1

1

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-35

When clock is LOW

0

1

1

No change

DDprime

D

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-36

When clock goes LOW-to-HIGH data is latched

DDprime

D

D

Dprime

Dprime

D

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-37

When clock is HIGH data is held

Dprime1

D

D

Dprime

Dprime

D

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-38

Timing

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clockPropagation delay time

mdash the time interval bt the trigger edge and the stabilization of the output to a new state

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-39

Setup time G1 + G4mdash the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of the clock transition

Dprime

D

D

Dprime

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-40

Hold time max(G2 G3)mdash the minimum time for which the D input must not change

after the application of the positive transition of the clock

Dprime

D

D

Dprime

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-41

Propagation delay timemdash the time interval bt the trigger edge and the stabilization

of the output to a new state

Dprime

D

D

DprimeD

Dprime

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-42

C Flip-Flop Timing

Clock pulse width tw

Setup time ts

Hold time th

Propagation delay times tPHL tPLH tpd

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-43

D Standard Graphics Symbols

AssumptionAll flip-flops are of the positive-edge-triggered type unless otherwise indicated

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-44

E Direct Inputs

Direct inputs asynchronous inputsmdash are used to force the flip-flop to a particular state

independent of the clockWhen power is turned on in a digital system the state of the flip-flops is unknownThe direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation

mdash Types of direct inputsPreset direct set sets the f-f to 1Clear direct reset sets the f-f to 0

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-45

Eg (補充資料)

D flip-flop w asynchronous reset

0

1

1

1

0

Active LOW

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-46

Eg D f-f w direct set and reset

direct set(active LOW)

direct reset(active LOW)

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-47

6-6 Other Flip-Flop Types

JK flip-flopT flip-flop

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-48

J-K Flip-Flop

Qprime11101010Q00Q+KJ

SR flip-flop JK flip-flop

Indeterminate11101010Q00Q+RS

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-49

Qprime11101010Q00Q+KJ

JK flip-flop

01111011110110010110001011000000

Q+QKJ

Q+ = JQprime + KprimeQ

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-50

Qprime Qprime111 1010 010Q Q00D Q+KJ

JK flip-flop (Contrsquod)

Q+ = JQprime + KprimeQD = Q+ =JQprime + KprimeQ

Verification

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-51

T Flip-Flop

Q+ = TQprime + TprimeQ

Qprime1Q0Q+T

Qprime11101010Q00Q+KJ

Q+ = JQprime + KprimeQ

J = K

rArrFrom D flip-flop

Q+ = D = TQprime + TprimeQ

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-52

Flip-Flop Logic Characteristic Tables amp Equations and Excitation Tables

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-53

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt

mdash includes f-fs w the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt

mdash The behavior of a seq ckt is determined from the inputs outputs and present state of the ckt

Analysis of a seq cktmdash obtain a suitable description that demonstrates the time

sequence of inputs outputs and states

(optional)

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-54

Analysis procedure

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

(1)(1)

(2)

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-55

A Analysis w D Flip-Flops

Eg 1

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-56

ltAnalysisgt

1 Flip-flop input equations amp Output equations

2 Next state equation(Q+ = D)

BXAXDA +=

XADB =

XB)(AY +=

BXAXDtA A +==+ )1(X)1( ADtB B ==+ comb ckt

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-57

3 State tableNext state equations

Output equations XBXAY +=

BXAXtA +=+ )1(X)1( AtB =+

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-58

(One-dimensional)State table

Two-dimensionalstate table

dArr

1

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-59

4 State diagram XY

rArr1

inputoutput

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-60

Eg 2

1 Flip-Flop input equations amp Output equationsDA = AoplusXoplusYZ = A

2 Next-state equationA+ = DA = AoplusXoplusY

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-61

3 State table

4 State diagram

YXAA oplusoplus=+

AZ =

AZ

stateoutput

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-62

補充資料Analysis w JK Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-63

Example

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-64

1 Flip-flop input equations amp Output equations

JA = BKA = B xprimeJB = xprimeKB = A xprime + Aprime x

= A oplus x2 Next state equations

(Q+ = J Qprime + Kprime Q)A+ = JA Aprime + KAprime A = Aprime B + A Bprime + A xB+ = JB Bprime + KBprimeB = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-65

3 State tableA+ = Aprime B + A Bprime + A xB+ = Bprime xprime + A B x + Aprime B xprime

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-66

4 State diagram

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-67

補充資料 Analysis w T Flip-Flops

Circuit(sync seq)

Flip-flopinput

Equations

Outputequations

Nextstate

equations

Statetable

(Transition table)

Statediagram

Flip-Flop Characteristic Equation1 2 3 4

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-68

Example

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-69

1 Flip-flop input equations amp Output equations

TA = B xTB = xy = A B

2 Next state equations (Q+ = T Qprime + Tprime Q)A+ = TA Aprime + TAprime A

= A Bprime + A xprime + Aprime B xB+ = TB Bprime + TBprimeB

= x oplus B

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-70

3 State tableA+ = A Bprime + A xprime + Aprime B xB+ = x oplus B y = A B

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-71

4 State diagram

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-72

B Mealy Model vs Moore Model

Mealy modelmdash is a model of seq ckts in which the outputs depend on

both the inputs and the present states

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-73

mdash Eg 1

State Register ClockState

Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-74

Moore modelmdash is a model of seq ckts in which the outputs depend only

on the present states

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-75

mdash Eg 2

Clock

state feedback

Combinational Logic for

Next State (Flip-flop Inputs)

State Register

Comb Logic for Outputs

Z Outputs

k

X Inputs

i

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-76

Comparisonmdash Moore model

The outputs of the ckt are synchronized w the clock(lArr the outputs depend on only flip-flop outputs that are

synchronized w the clock)

mdash Mealy modelThe outputs may change if the inputs change during the clock cycle

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-77

C Sequential Circuit Timing

Analysis of a seq cktmdash analyze the function of the cktmdash analyze the performance of the ckt

max input-to-output delaythe max clock frequency fmax at which the ckt can operate

clock frequency f = 1tp tp the clock periodfmax = 1tp-min tp-min the min allowable clock period

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-78

Sequential Circuit Timing Parameters

Sequential ckt timing parametersi f-f propagation delay tpdFF

ii comb logic delay through the chain of gates along the path tpdCOMB

iii f-f setup time ts

(iv slack time tslack the extra time allowed in the clock period beyond that required by the path)

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-79

For edge-triggered flip-flopsmdash determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-80

For pulse-triggered flip-flops

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-81

Sequential Circuit Timing Paths

Sequential ckt timing paths

ti the latest time that the input changes after the positive clock edge

to the latest time that the output is permitted to change prior to the next clock edge

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-82

Propagation delay for a path of type PFFFF

)tt(ttt sCOMBpdFFpdslackp +++=

minpsCOMBpdFFpdp max t)tt (tt =++ge

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-83

Example 6-1 Clock Period and Frequency Calculations

Example 6-1Suppose that all f-fs used are the same and have tpd = 02 ns

and ts = 01 ns Then the longest path beginning and ending w a f-f will be the path w the largest tpdCOMB Further suppose that the largest tpdCOMB is 13 ns and that tp has been set to 15 ns

ltAnsgt )tt(ttt sCOMBpdFFpdslackp +++=ns 61103120ns 51 slackslack +=+++= tt

)0tion w (contradic ns 10 slackslack leminus=rArr tt

ns 61minpp =gerArr ttMHZ 625ns 611max ==rArr f

rArr tp is too small

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-84

Discussion

If tp is too large to meet the ckt specificationsmdash employ faster logic cells ormdash change the ckt design to reduce the problematic path

delays through the ckt

Hold time thmdash does not appear in the clock period

equationmdash relates to another timing constraint

equation dealing w one or both of 2 specific situations

output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-85

D Simulation

Sequential ckt simulationmdash The input patterns must be applied in a sequencemdash There must be some means to place the ckt in a known statemdash Observe the state to verify correctnessmdash Deal with the timing of application of inputs and observation of

outputs relative to the active clock edge

Function simulationmdash Objective determination or verification of the function of the ckt

rArr Assumption Ckt components has no delay or a very small delay

Timing simulationmdash Objective verification of the proper op of the ckt in terms of timing

rArr Ckt components has realistic delays

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-86

Simulation timing

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-87

6-5 (Sync) Sequential Circuit Design

Design procedure1 Specification Write a specification for the ckt2 Formulation Obtain either a state diagram or state

table from the statement of the problem State reduction Reduce the of states if necessary3 State assignment Assign binary codes to the states

and obtain the binary-coded state table4 Flip-flop input equation determination Select the

flip-flop type or types Derive the flip-flop input equations from the next-state entries in the encoded state table

5 Output equation determination Derive output equations from the output entries in the state table

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-88

6 Optimization Optimize the flip-flop input equations and output equations

7 Technology mapping Draw a logic diagram of the ckt using flip-flops ANDs ORs and inverters Transform the logic diagram to a new diagram using the available flip-flop and gate technology

8 Verification Verify the correctness of the final design

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-89

Functionaldescription

Statediagram

Statetable

Minimalstatetable

Binary-codedstatetable

Flip-Flopinput

equationsamp

Outputequations

Circuit Verify(UsedUnused

states)

Stateassignment

A

B C

DE F

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-90

A Finding State Diagrams and State Tables

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-91

Initial State

Initial statemdash Async and sync reset for D flip-flops

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-92

Example 6-2

Eg Sequence recognizer of ldquo1101rdquomdash Problem description

Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1 regardless of where it occurs in a sequence Otherwise Z equals 0The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros

ldquo1101rdquoSeq Recognizer

X Z

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-93

mdash State diagramldquo1101rdquo

Seq RecognizerX Z

Init ldquo1rdquo ldquo11rdquo ldquo110rdquo ldquo1101rdquo10 10 00 11

00

00

10

00 00

10

A B C D E

State B = State E

XZ

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-94

mdash State diagram (contrsquod)

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-95

mdash State table

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-96

Example

State tablePresent Input Next Output

state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1

Eg Sequence detector of three or more consecutive 1rsquos

Design a ckt that detects three or more consecutive 1rsquos in a string of bits coming through an input line

ltAnsgtState diagram

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-97

Example 6-3

Eg Finding a state diagram for a BCD-to-excess-3 decoder

mdash Formulation Sequence tables for code converter

LSB MSB LSB MSB

BCD-to-excess-3 decoder

X Z

0123456789

B1 B2 B3 B4

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-98

mdash State diagramB1 B2 B3 B4

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-99

mdash State diagram

B3=0 B3=1 B3=0 B3=1 B3=0 B3=1 B3=0 B3=1

B2=0 B2=1

B1=0 B1=1

Init

B2=0 B2=1

01 10

01 10 00 11

00 11 01 10 01 10 01 10

00 11 00 00 01 00 11 01 00 01

Init

B1 B2 B3 B4

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-100

mdash State diagram (contrsquod)

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-101

B State Reduction rarr Minimal State Table(補充資料)

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-102

B State Reduction rarr Minimal State Table (補充資料)

State reduction mdash Implement a seq ckt with fewest possible statesmdash Least number of flip-flops

Boundaries are power of two number of statesmdash Fewest states usually leads to more opportunities for

dont caresReduce the number of gates needed for implementation

Goalmdash Identify and combine states that have equivalent

behaviormdash Equivalent States for all input combinations

states transition to the same or equivalent states ampoutputs are the same or compatible

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-103

State Reduction Methods

State reduction methodsmdash Row matching methodmdash Implication chart method

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-104

(a) Row Matching Method

Row matching methodmdash Identify states w same output behaviormdash If such states transition to the same next state they are

equivalentmdash Combine into a single new renamed statemdash Repeat until no new states are combinedmdash Adv Straightforward to understand and easy to

implementmdash Problem does not allows yield the most reduced state

table

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-105

Eg 3-bit sequence detectormdash Single input X Single output Zmdash Output a 1 whenever the serial sequence 010 or 110 has

been observed at the inputs

ltAnsgtState diagram

S3 S4

S1 S2

S0

S5 S6

00 10

00 10 00 10

00 10 01 10 00 10 01 10

S0

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-106

State table

Reduced state table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-107

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

(S1 S2)(S3 S5)(S4 S6)

00

S3 = S5 S4 = S6

S1 = S2

S0

010

00 10

10 01 10

S0

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-108

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Next State Criterion

No way to combine states S0 and S2based on Next State Criterion

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-109

(b) Implication Chart Method

Naive Data Structurexij will be the same as xjiAlso can eliminate the diagonal

Implication Chart

Next StatesUnder all

InputCombinations

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Enumerate all possible combinations of states taken two at a time

S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5 S6

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-110

Filling in the implication chartmdash xij Row is Si Column is Sj

mdash Si is equivalent to Sj if outputs are the same and next states are equivalent Entry

If Si amp Sj have different output behavior then xij is crossed outxij contains the next states of Si amp Sj which must be equivalent if Si and Sj are equivalent

EgS0 transitions to S1 on 0 S2 on 1S1 transitions to S3 on 0 S4 on 1

S1-S3S2-S4

S1

S0

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-111

Eg 3-bit sequence detectorSingle input X Single output ZOutput a 1 whenever the serial sequence 010 or 110 has been observed at the inputs

ltAnsgtState table

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-112

Present State S 0 S 1 S 2 S 3 S 4 S 5 S 6

Input Sequence Reset

0 1

00 01 10 1 1

X =1 0 0 0 0 0 0 0

Next State Output X =0 S 1 S 3 S 5 S 0 S 0 S 0 S 0

X =1 S 2 S 4 S 6 S 0 S 0 S 0 S 0

X =0 0 0 0 0 1 0 1

S2 and S4 have differentIO behavior

dArrS1 and S0 cannot

be combined

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

Starting implication chart

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-113

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0

S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

1st marking pass

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

S1-S3

S2-S4

S1-S5

S2-S6

S3-S5

S4-S6

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S1-S0

S2-S0

S3-S0

S4-S0

S5-S0

S6-S0

S0-S0

S0-S0

S0-S0

S0-S0

rArr

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-114

Input Sequence Reset

0 or 1 00 or 10 01 or 1 1

Present State S 0 S 1 S 3 S 4

X =0 S 1 S 3 S 0 S 0

X =1 S 1 S 4 S 0 S 0

X =0 0 0 0 1

X =1 0 0 0 0

Next State Output

S0-S0

S0-S0

S3-S5

S4-S6

S0-S0S0-S0

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

2nd Pass adds no new information

S4 and S6 are equivalentS3 and S5 are equivalentrArr S1 and S2 are too

Reduced state table

(S1 S2)(S3 S5)(S4 S6)

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-115

Eg 3-state odd parity checker

No way to combine states S0 and S2based on Row matching method

No way to combine states S0 and S2based on Row matching method

Present State S 0 S 1 S 2

Next State X =0 S 0 S 1 S 2

X =1 S 1 S 2 S 1

Output 0 1 0

Implication ChartImplication Chart

S0 is equivalent to S2since nothing contradicts this assertion

S 1 S 2

S 0 S 1

S 0 - S 2 S 1 - S 1

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-116State Diagram

Symbolic State Table

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

10

0111

00

00

01

1110

10 01

1100

10

00

01

11

00

1110

01

10

1101

00

Multiple Input State Diagram Example

Eg Multiple Input State Diagram Example

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-117Implication Chart

Minimized State Table

Present State

S 0 S 1 S 2 S 3

Next State 00 S 0 S 0 S 1 S 1

01 S 1 S 3 S 3 S 0

10 S 2 S 1 S 2 S 0

1 1 S 3 S 3 S 0 S 3

Output 1 0 1 0

S1

S2

S3

S4

S5

S0-S1

S1-S3 S2-S2

S3-S4

S0-S0

S1-S1

S2-S2S3-S5

S0

S0-S1S3-S0

S1-S4

S5-S5

S0-S1

S3-S4S1-S0

S5-S5

S1

S1-S0

S3-S1

S2-S2S4-S5

S2

S1-S1

S0-S4S4-S0

S5-S5

S3 S4

Symbolic State Diagram

Present State

S 0 S 1 S 2 S 3 S 4 S 5

Next State 00 S 0 S 0 S 1 S 1 S 0 S 1

01 S 1 S 3 S 3 S 0 S 1 S 4

10 S 2 S 1 S 2 S 4 S 2 S 0

1 1 S 3 S 5 S 4 S 5 S 5 S 5

Output 1 0 1 0 1 0

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-118

Detailed Algorithm of Imp Chart Method

1 Construct implication chart one square for each combination of states taken two at a time

2 Square labeled (Si Sj) If outputs differ then square gets times Otherwise write down implied state pairs for all input combinations

3 Advance through chart top-to-bottom and left-to-right If square (Si Sj) contains next state pair Sm Sn and that pair labels a square already labeled times then (Si Sj) is labeled times

4 Continue executing Step 3 until no new squares are marked with times

5 For each remaining unmarked square (Si Sj) then Si and Sj are equivalent

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-119

C State Assignment (補充資料)

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-120

State Assignment

4 states rArr 4 choices for first state 3 for second 2 for third 1 for last= 24 different encodings (4)

Eg 4 states ⎯ HG HY FG FY

Symbolic State Names HG HY FG FY

24 state assignmentsfor the traffic light

controller

HG 00 00 00 00 00 00 01 01 01 01 01 01

HY 01 01 10 10 1 1 1 1 00 00 10 10 1 1 1 1

FG 10 1 1 01 1 1 01 10 10 1 1 00 1 1 00 10

FY 1 1 10 1 1 01 10 01 1 1 10 1 1 00 10 00

HG 10 10 10 10 10 10 1 1 1 1 1 1 1 1 1 1 1 1

HY 00 00 01 01 1 1 1 1 00 00 01 01 10 10

FG 01 1 1 00 1 1 00 01 01 10 00 10 00 01

FY 1 1 01 1 1 00 01 00 10 01 10 00 01 00

When a seq ckt implemented w gate logic gates will depend on mapping bt symbolic state names and binary encodings

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-121

State Maps similar in concept to K-maps

Q 1 Q 0 00 01 1 1 10

0

1

Q 2 S 0 S 4 S 3

S 1 S 2

State Map

State Name S 0 S 1 S 2 S 3 S 4

Assignment Q 2 0 1 1 0 0

Q 1 0 0 1 1 1

Q 0 0 1 1 0 1

Assignment

Q 1 Q 0 00 01 1 1 10 Q 2

0

1

S 0 S 1 S 3 S 2

S 4

State Map

State Name S 0 S 1 S 2 S 3 S 4

Q 2 0 0 0 0 1

Q 1 0 0 1 1 1

Q 0 0 1 0 1 1

Assignment

Assignment

State Map

S0

S1 S2

S3

S4

0 1

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-122

Guideline for State Assignment Adjacent assignments

Heuristics based on input and output behavior amp transitions

states that share a common next state(group 1s in next state map)

states that share a common ancestor state(group 1s in next state map)

states that have common output behavior(group 1s in output map)

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β

i

ii

iii

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-123

Guideline 1 states that share a common next state(group 1s in next state map)

Highest Priority

ij ik

α β Eg

rArr (A B D) (A D) (B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-124

states that share a common ancestor state(group 1s in next state map)

Medium Priority

α β

Guideline 2

Eg

rArr (A B) (A C) (C D) (A B)rArr (A B)times2 (A C) (C D)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-125

states that have common output behavior(group 1s in output map)

Lowest Priority

ij ijα β

Guideline 3

Eg

rArr (A B C D) (A B C)

0010

0010

1000

00 11

A B

D C

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-126

Eg

Guideline 1 (A B D) (A D) (B C)Guideline 2Guideline 3

(A B)times2 (A C) (C D)(A B C D) (A B C)

State MapQ1

Q0

0010

0010

1000

00 11

A B

D C

0 1

0

1

State AssignmentA = B = C = D =

State table State diagram

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-127

State Assignment 1 heuristicsA = 00B = 01C = 10D = 11

State Assignment 2 guidelinesA = 00B = 01C = 11D = 10

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Transition Table 1 Transition Table 2

A B

C D

A B

D C

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-128

Transition Table 1 heuristics Transition Table 2 guidelines

00011011

00001100

01101001

00001000

00011110

01111101

Q1Q0 Q1Q0Q1

+ Q0+ Q1

+ Q0+

Q1+

Q0+

Q1+

Q0+

Z Z

00

0 001

11

0 00 0

01

11

100

00

000

100

00

00

0

00

0 001

11

0 0 001 111

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-129

Example 3-Bit Sequence Detector

(S3 S4) times 2

01

Reset

S0

010

01010

S1prime00 10

S3prime

S4prime

Highest Priority

Medium Priority

Lowest Priority

ij ik

ij ij

α

α

α

β

β

β(S3 S4)

00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-130

Reset State = 00

Highest Priority Adjacency

Not much difference in these two assignments

Not much difference in these two assignments

Q0Q1

0

0

1

1

Srsquo1

S0

Srsquo4

Srsquo3

Q0Q1

0

0

1

1

Srsquo3

S0

Srsquo4

Srsquo1

Highest Priority (S3 S4) times 2

Medium Priority (S3 S4)

Lowest Priority 00 (S0 S1 S3)10 (S0 S1 S3 S4)

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-131

Example 4-Bit String Recognizer

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

Reset

S1

S3

S7

S2

S4

S10

010

010

00

00

10 10

10

10

1001

S0

00

00

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-132

00 = Reset = S0

Adjacent states(S7 S10)(S3 S4) (S1 S2)

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

Q1 Q0

Q2

0

1

00 01 11 10

S0 S3

S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4

S7

S10

Q1 Q0

Q2

0

1

00 01 11 10

S0

Q1 Q0

Q2

0

1

00 01 11 10

S0

S7 S10

Q1 Q0Q2

0

1

00 01 11 10

S0 S3

S4S7 S10

Q1 Q0

Q2

0

1

00 01 11 10

S0 S1 S3

S2 S4S7 S10

(a) (b)

State Map

Highest Priority (S3 S4) (S7 S10) times 2

Medium Priority(S1 S2) (S3 S4) times 2 (S7 S10)

Lowest Priority00 (S0 S1 S2 S3 S4 S7)10 (S0 S1 S2 S3 S4 S7 S10)

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-133

Effect of Adjacencies on Next State Map

First encoding exhibits a better clustering of 1s in the next state map

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1 Q 0 X

P 0

Q 2 Q 1

Q 0 X

P 1 P 2

P 1

Q 2 Q 1

Q 0 X Q 2 Q 1

Q 0 X

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

0

0

00

01

00 01 1 1 10

1 1

10

0

0

0

0

0

0 1

1 0

0

X

X

P 2

00

01

00 01 1 1 10

1 1

10

0

1

1

1

1

1

1

X

X

00

01

00 01 1 1 10

1 1

10

1

1

1

1

0

0

0

0

0

0

0

0

X

X

1

1

( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ) ( S 4 ) ( S 7 ) ( S 10 )

000 001 101 01 1 1 1 1 010 1 10

X = 0 001 01 1 1 1 1 010 010 000 000

X = 1 101 1 1 1 01 1 010 1 10 000 000

Current State

Next State

000 001 010 01 1 100 101 1 10

X = 0 001 01 1 100 101 101 000 000

X = 1 010 100 01 1 101 1 10 000 000

Current State

Next State

1

1

0

0

1

1

0

0 0

0

1

Q 2 Q 1 Q 0 X

00

01

00 01 1 1 10

1 1

10

0

0

0

0

1

0 0

1 1

1

1

1

00

01

00 01 1 1 10

1 1

10

0

0

1

X

X

0

0

0

1

00

01

00 01 1 1 10

1 1

10

1

0

0

1

0

1

1

1

0

0

X

X

1

0

0

0

X

0

0

X

0

0

0

0 1

(p6-120(a))

(Another assignment)

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-134

Construct the Binary-coded State Table

Minimal state table Transition tablemdash Unused states donrsquot-care conditions

Eg

State assignment

dArr A = 00 B = 01 C = 11 D = 10

(Binary-coded state table)

Transition table(Binary-coded

state table)

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-135

D Derive Flip-Flop Input Eqs amp Output EqsE Circuit

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-136

Flip-Flop Excitation Tables

Select the flip-flop type or typesrArr Flip-flop excitation tables (p6-46)

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-137

(a) Designing Using D Flip-Flops

Example 6-2 Sequence detector (p6-86)State diagram

State table

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-138

State assignmentA = 00 B = 01C = 11 D = 10

Binary coded state table

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-139

F-F input eqs amp output eq

)763()()1( mXBADtA A Σ==+

)7531()()1( mCBADtB B Σ==+

)5()( mXBAZ Σ=

equiv D f-f input values

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-140

Logic diagram

BXABDA +=

XDB =

XBAZ =

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-141

Designing w Unused States

Examplemdash State table

3 unused states000110111

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-142

mdash Maps for optimizing flip-flop input equations

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-143

mdash Logic diagram

C BBXAXDA ++=

XB AX C ADB +=

XDC =

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-144

(b) Design Using JK Flip-Flops (補充資料)

ExampleState diagram

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-145

minus State table and JK flip-flop inputs

0times111times01times110times000KJQ+Q

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-146

minus Maps for flip-flop input equations

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-147

minus CircuitJA = B xprime KA = B xJB = x KB = Ax + Aprime xprime = (A oplus x)prime

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-148

(c) Design Using T Flip-Flops ( 補充資料)

Example 3-bit binary counterState diagram

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-149

minus State table and T flip-flop inputs

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-150

minus Maps for flip-flop input equations

minus Circuit

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-151

F Verification

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-152

Verification of sync seq cktsmdash show that the ckt produces the original state diagram or

state tableused statesunused states

mdash Manual verification for small cktsanalyze the ckt

mdash Verification w simulationrequires a seq of input combinations and applied clocks

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-153

Example

Eg

Synthesis(A ~ F)

VerifyAnalysis

(G)

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-154

Example 6-4

Eg Verifying the sequence recognizermdash Test generation for simulation

ldquo1101rdquoSeq Recognizer

X Z

01 11 0110 01 10 001100

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-155

mdash Simulation

01 11 0110 01 10 001100

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-156

補充資料 Word Problems

Example Vending Machinedeliver package of gum after 15 cents depositedsingle coin slot for dimes nickelsno change

ltAnsgtUnderstand the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

Sensor Gum Release

Mechanism

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-157

Draw state diagram

Inputs N D reset

Output open

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-158

State Minimization

Reset

N

N

N D

[open]

15

0

5

10

D

D

reuse stateswheneverpossible

Symbolic State Table

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-159

Problems

6-38~43sect6-8 (times)6-32~6-37sect6-7 (times)

6-24 6-27 6-31sect6-6

6-14~6-23 6-25 6-26 6-28~6-30sect6-5

6-5~6-13sect6-46-3 6-4sect6-36-1 6-2sect6-2

sect6-1ExercisesSections

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-160

Homework

6-56-86-9化簡下列state diagram求出化簡後的state table

6-16mdash 新增一小題使用JK flip-

flops重做（c）小題

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines

JJ Shann 6-161

補充題

Given the following state diagram select a good state assignment Show your assignment in a state map and justify your answer in terms of the state assignment guidelines