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Georgia TechNovember 2006
J. E. Smith
Virtual Machines: Virtual Machines: Supporting Changing Technology Supporting Changing Technology
and New Applicationsand New Applications
VMs (c) 2006, J. E. Smith 2
IntroductionIntroduction
Why virtual machines?
They allow transcending of standardized interfaces (which sometimes are an obstacle to innovation)
They enable innovation in flexible, adaptive software & hardware, security, network computing (and others)
They involve computer architecture in a pure sense
Virtualization technologies will be a key part of most future computer systems
VMs (c) 2006, J. E. Smith 3
OutlineOutline
Virtualization Virtual Machine Architecture Virtual Machine Implementation Computer Architecture Applications
• Co-Designed VMs• Private Virtual Machines
VMs (c) 2006, J. E. Smith 4
AbstractionAbstraction
Computer systems are built on levels of abstraction
Higher level of abstraction hide details at lower levels
Example: files are an abstraction of a disk
filefile
abstraction
I/O devicesand
Networking
Controllers
System Interconnect(bus)
Controllers
MemoryTranslation
Execution Hardware
DriversMemoryManager
Scheduler
Operating System
Libraries
ApplicationPrograms
MainMemory
Software
Hardware
VMs (c) 2006, J. E. Smith 5
VirtualizationVirtualization
Similar to abstractionExcept• Same level of detail
Construct Virtual Disks• As files on a larger disk• Map state• Map operations
VMs: do the same thing with the whole “machine”
Key concepts: Map state; Map Operations
file file
virtualization
VMs (c) 2006, J. E. Smith 6
There are lots of “virtual machines”IBM VM/370JavaVMware products
The Family of Virtual MachinesThe Family of Virtual Machines
“The subjects of virtual machines and emulators have been treated as entirely separate. … they have much in common. Not only do the usual implementations have many shared characteristics, but this commonality extends to the theoretical concepts on which they are based”
-- Efrem G. Wallach, 1973
Including things not called “virtual machines” IA-32 EL
HP Dynamo Transmeta Crusoe
VMs (c) 2006, J. E. Smith 7
““Machines”Machines”
Different perspectives on what the Machine is:
OS developer Compiler developer Application programmer
Instruction Set Architecture• ISA• Major division between hardware
and software
Application Binary Interface• ABI• User ISA + OS calls
Application Program Interface• API• User ISA + library calls I/O devices
andNetworking
System Interconnect(bus)
MemoryTranslation
Execution Hardware
ApplicationPrograms
MainMemory
Operating System
Libraries
VMs (c) 2006, J. E. Smith 8
System Virtual MachinesSystem Virtual Machines
ISA level Provide a system
environment VMM manages
guest OS + apps Persistent Examples: IBM
VM/360, VMware, Transmeta Crusoe
guestprocess
HOST PLATFORM
virtualnetwork communication
Guest OS
VMM
guestprocess
guestprocess
guestprocess
Guest OS2
VMM
guestprocess
guestprocess
VMs (c) 2006, J. E. Smith 9
Process Virtual MachinesProcess Virtual Machines
ABI level Runtime manages guest
process Guest processes may
intermingle with host processes
Not persistent Guest and host OSes are
often the same Dynamic optimizers are
a special case Examples: IA-32 EL, FX!
32, Dynamo
HOST OS
Disk
file sharing
network communication
guestprocess
create
hostprocess
guestprocess
runtimeruntime
guestprocess
runtime
hostprocess
VMs (c) 2006, J. E. Smith 10
High Level Language Virtual MachinesHigh Level Language Virtual Machines
Constructed at API level• User higher level virtual ISA• OS abstracted as standard libraries
A form of process VM
HLL Program
Intermediate Code
Memory Image
Object Code(ISA)
Compiler front-end
Compiler back-end
Loader
HLL Program
Portable Code(Virtual ISA )
Host Instructions
Virt. Mem. Image
Compiler
VM loader
VM Interpreter/Translator
Traditional HLL VM
VMs (c) 2006, J. E. Smith 11
Virtual Machine ArchitecturesVirtual Machine Architectures
Multiprogrammed
Systems
HLL VMsCo-Designed
VMs
same ISAdifferent
ISA
Process VMs System VMs
WholeSystem VMs
differentISA
same ISA
ClassicOS VMs
DynamicBinary
Optimizers
DynamicTranslators
HostedVMs
VMs (c) 2006, J. E. Smith 12
VM Technology – State MappingVM Technology – State Mapping
VM SW re-maps virtual state to real state
• Recall virtual disk• Registers to registers• Registers to memory• Memory to memory• Memory to disk
Guest Code
Guest Data
RuntimeData
RuntimeCode
Guest Registers
Host Registers
Host ABIAddress Space
HostRegister Space
VMs (c) 2006, J. E. Smith 13
VM Technology – Operation MappingVM Technology – Operation Mapping
VM SW re-maps operations on state Instruction-level state changes
• Emulation
Protected state changes• OS operations• Done under VMM control
Key concepts: Emulation and Control
VMs (c) 2006, J. E. Smith 14
VM Technology – EmulationVM Technology – Emulation
Interpretation• Software loop
decodes and dispatches each instruction
source code
dispatchloop
interpreter
routines
"data"accesses
VMs (c) 2006, J. E. Smith 15
VM Technology – EmulationVM Technology – Emulation
Binary translation and code caching
• Translate blocks of instructions at a time
• Hold translated blocks in code cache
• This was a key enabler for VMware success
source code
binarytranslator
binary translatedtarget code
VMs (c) 2006, J. E. Smith 16
VM Technology – EmulationVM Technology – Emulation
Staged Emulation• Emulation techniques invoked in staged manner• Based on performance tradeoffs
Code Cache
Translator/Optimizer
Binary MemoryImage
Profile Data
Interpreter Emulationmanager
VMs (c) 2006, J. E. Smith 17
Code CachesCode Caches
Contain• Basic blocks• Superblocks (one entrance, multiple exits)• Optimized Superblocks
Used in many VMs• Dynamic binary translators: Intel IA-32 EL, Compaq FX!32• Dynamic binary optimizers: Dynamo family• Co-designed virtual machines: Transmeta, IBM DAISY• High performance Java virtual machines• System VMs with “inefficiently virtualizable” ISAs• “Sandboxing” secure VMs (x86 DynamoRIO)
VMs (c) 2006, J. E. Smith 18
Code Caching with ChainingCode Caching with Chaining
Chaining of blocks in code cache minimizes VM overhead
Superblock
Dispatch table
lookup code
Superblock
Superblock
Superblock
Code Cache
VMs (c) 2006, J. E. Smith 19
VM Technology – ControlVM Technology – Control
Interpretation • Fine grain control• Every dynamic instruction “inspected” before execution
Binary translation and code caching• Coarser grain control• Every static instruction inspected before execution• Jumps to VM SW can be inserted anywhere
Protection levels• Very coarse grain control• Every resource-related instruction trapped by protection system
Otherwise, use interpretation/translation techniques• Used in system VMs
VMs (c) 2006, J. E. Smith 20
Resource Control in System VMsResource Control in System VMs
Traps and interrupts (& sys calls)• Transfer to VMM• VMM determines appropriate Guest OS• VMM transfers to Guest OS
Guest OS “return” to user app.• Transfer to VMM• VMM bounces return back to Guest app.
Resource sensitive instructions• Trap to VMM• VMM checks correctness• VMM reads/modifies guest resource• Returns to Guest
privileged operation
next instruction
check privileges
perform operation
return
system call/trap
vector location:
virtual vector location:
Application
Guest OS
VMM
system return
VMs (c) 2006, J. E. Smith 21
VMs and Computer ArchitectureVMs and Computer Architecture
Use virtualization to give computer architects a layer of software
• Beneath all conventional software• Maintains vision of hardware as seen by conventional software
Performance optimizations via Co-designed VMs• VM SW can alter/enhance architecture via emulation
Resource management – Private Virtual Machines• VM SW can manage microarchitecture resources
VMs (c) 2006, J. E. Smith 22
Co-Designed Virtual MachinesCo-Designed Virtual Machines
Separate the hardware/software interface from the ISA level of abstraction Restore the ISA to its “natural” place
as an Implementation ISA that reflects actual hardware Support existing ISAs
as a Virtual ISA Let processor designers use both hardware and software A form of system VM
OS
libs.
User Applications
V-ISA
I-ISA
Hardware
Software
Hardware
OS
libs.
User Applications
ISA
VMs (c) 2006, J. E. Smith 23
VM Technology -- Concealed MemoryVM Technology -- Concealed Memory
VM software resides in memory concealed from all conventional software
This software is available to hardware designer
Source ISA Data
CodeCache
VM Code
ICacheHierarchy
DCacheHierarchy
ProcessorCore
Source ISA Code
VM Data
concealed memory
conventionalmemory
VMs (c) 2006, J. E. Smith 24
Co-Designed VMsCo-Designed VMs
Of interest to both architects and micro-architects
• Offers opportunities for performance, power saving, fault tolerance and other implementation-dependent features
• Allows transcending conventional ISAs• Don’t confuse them with VLIW!
Early examples: IBM Daisy and Transmeta Crusoe
“pioneers are the ones with arrows in their backs”
VMs (c) 2006, J. E. Smith 25
Another Way of Doing ThingsAnother Way of Doing Things
conventional
dynamic translation
Code CacheProcessor
Pipeline
Software
Translator
Main Memory
Func.Unit
Func.Unit
. ..
Main MemoryCache
HierarchyProcessor
Pipeline
TranslationUnit
(form uops)
Func.Unit
Func.Unit
Func.Unit
. ..
TranslationUnit
(form uops)
CacheHierarchy
VMs (c) 2006, J. E. Smith 26
Fused MicroarchitectureFused Microarchitecture
DecodeRenameDispatch
Wake-up
RFSelect EXEFetch MEM
cacheports
AlignFuse
Fusebit
3-1 ALUs
WBRetire
Payload RAM
Fuse dependent pairs of micro-ops to macro-ops• Current Intel approach
Use co-designed SW to achieve wider-scale fusing Process & execute fused macro-ops as single Instructions throughout the entire pipeline Allows pipelined wake-up/select issue logic
VMs (c) 2006, J. E. Smith 27
RISC-ops with unique features:
• Fuse bit per instruction fuses two dependent instructions
• Dense instruction encoding, 16/32-bit ISA design
Special Features to Support the x86 ISA
• Condition codes
• Addressing modes
• Aware of long immediate & displacement values
Fusible Instruction SetFusible Instruction Set
21 bit Immediate / Displacement10 b opcode
11b Immediate / Disp10 b opcode 5b Rds5 b Rsrc
16 bit opcode 5b Rds5b Rsrc5b Rsrc
5b op
10b Immd / Disp
F
16 bit immediate / Displacement10 b opcode 5b Rds
F
F
F
F
F
F
5b Rds5b Rsrc
5 b op
5b op
5 b Rds5b Rsrc
Core 32- bit instruction formats
Add-on 16-bit instruction formats for code density
Fusible ISA Instruction Formats
VMs (c) 2006, J. E. Smith 28
Fusing ProfileFusing Profile
About 50% of operations are fused Only 5-10% of non-fused are single-cycle ALU ops
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
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Fused
VMs (c) 2006, J. E. Smith 29
PerformancePerformance
-10
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10
20
30
40
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60
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Base + Code Cache + fusing + shorter pipe + 3-1 ALU
VMs (c) 2006, J. E. Smith 30
Virtual Private MachinesVirtual Private Machines Multi-core systems will have many hardware-
level shared resources• Multi-threaded processors• Multi-level shared caches• Shared memory ports• Spares for fault tolerance
And a number of important implementation dependences
• Non-uniform memory delays• Power optimization features• Fault tolerance features
VMs (c) 2006, J. E. Smith 31
Virtual Private MachinesVirtual Private Machines
Co-design a MicroVisor to provide software with Virtual Private Machines
• Insulates conventional software from complicated implementation-dependent features
Provides performance virtualization• Unlike classic VMs• Quality of Service (QoS)• Performance Isolation
MicroVisor
VPM
Hypervisor (VMM)
VPM
SystemVM
ConventionalOS
SystemVM
FunctionalVirtualization
PerformanceVirtualization
Multi-Core Hardware
VMs (c) 2006, J. E. Smith 32
MicroVisorMicroVisor
Virtualizes performance, not functionality Co-Designed software to support hardware resource
management• Concealed/isolated from all conventional software • Much larger than microcode, does not consume processor chip
real estate• Uses conventional instructions (extended) so there is more
likelihood of some cross-system portability
Data
μV Code ICacheHierarchy
DCacheHierarchy
ProcessorCore
Code
μV Dataconcealed memory
conventionalmemory
VMs (c) 2006, J. E. Smith 33
““Real-izing” Processors/MemoryReal-izing” Processors/Memory
Separate Real Processors from Physical Processors
• OS assigns processes to Real Processors
• MicroVisor maps real processors to physical processors
MicroVisor also maps real memory to physical memory
• Extend to cache memories
Processes
RealProcessors
PhysicalProcessors
OS Maps
MicroVisor Maps
VMs (c) 2006, J. E. Smith 34
Virtual Private MachinesVirtual Private Machines
Main Memory
L2 Cache
Proc. 0Threads
0 & 1
Proc. 1Threads
2 & 3
L1 Cache
Interconnection Net
Main Memory
L2 Cache
Proc. 0Thread 0
L1 Cache
Memory Controller
L1 Cache
MemController
VPM 0
L2 Cache
Proc. 0Thread 0
L1 Cache
MemController
VPM 1
L2 Cache
Proc. 0Thread 0
L1 Cache
MemController
L2 Cache
Proc. 0Thread 0
L1 Cache
MemController
VPM 2 VPM 3
MicroVisor maps high level requirements to hardware configuration Requires mechanisms to provide microarchitecture level QoS
VMs (c) 2006, J. E. Smith 35
ApplicationsApplications
Performance optimization• Deal with NUMA• Provide QoS and performance isolation in multi-threaded systems
Power management • Adjust resources to match power constraints• Requires inferring demand for resources
in contrast to conventional OS Fault tolerance
• Detected fault triggers MicroVisor• Diagnose, reconfigure, re-map memory/processors
VMs (c) 2006, J. E. Smith 36
SummarySummary
Many types of VMs• But common virtualization technologies
An important system component• Should be studied/taught as a discipline on its own
Alongside OS, Application SW, HW Many avenues for computer architecture
research• Co-designed VMs• Virtual Private Machines• Adaptive microarchitecture• Fault-tolerant implementations• Primitives for supporting efficient VMs
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