Design for reliability in resistive ram for ict‐enabled devices

IDC GRANT 2013

Kin Leong Pey et. al.Engineering Product Development Pillar

Singapore University of Technology and Design (SUTD)

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Design for Reliability in Resistive RAM for ICT-Enabled Devices

Objectives of Project

• To use design initiatives aimed at enhancing the reliability of resistive

switching non-volatile memory known as RRAM.

• Design Options to be considered :-

Material design.

Process design.

Architectural design.

Electrical parameter design.

• Design Methods.

Physical failure analysis (TEM, EELS, STM microscopy).

Atomistic simulations.

© KIN LEONG PEY, SUTD (2013) 2

Schematic of an RRAM

© KIN LEONG PEY, SUTD (2013) 3

Reliability Metrics to be Assessed

• RETENTION.

– Duration of data storage of binary ‘0’ or ‘1’.

• ENDURANCE.

– Number of cycles of switching that can be achieved without collapse of

the memory window.

• READ DISTURB IMMUNITY.

– Stability of data in the low and high resistance state to random telegraph

noise fluctuations in the dielectric.

© KIN LEONG PEY, SUTD (2013) 4

Design Methodology and Science

• Failure modes and effects (FMEA) analysis.

• Root cause analysis.

© KIN LEONG PEY, SUTD (2013) 5

Design Metrics for RRAM

© KIN LEONG PEY, SUTD (2013) 6