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Special GatesCombinational Logic

Gates

Lecture 2

Prof Jess Role @UEAB 2008

DeMorgan's Law

• Converting AND to OR (with some help from NOT)• Consider the following gate:

A B

0 0 1 1 1 0

0 1 1 0 0 1

1 0 0 1 0 1

1 1 0 0 0 1

BA BA BA

Same as A+B!

To convert AND to OR

(or vice versa),invert inputs and

output.


More than 2 Inputs?• AND/OR can take any number of inputs.

– AND = 1 if all inputs are 1.– OR = 1 if any input is 1.– Similar for NAND/NOR.

• Can implement with multiple two-input gates,or with single CMOS circuit.













Jess Role@UEAB 2006

Half adder

• The sum is XOR operation and the carry an AND:

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

A

B

C

S

Jess Role@UEAB 2006

Examples

• The half adder– The half adder is a circuit for adding two

single bit numbers

– Develop a truth table and Boolean expressions for the half adder

S and C are the Sum and Carry

A B S C

0 0

0 1

1 0

1 1

Prof Jess Role @UEAB 2008 Jess Role@UEAB 2006

Examples

• The full adder– Develop a truth table and Boolean

expressions for the full adder, this circuit also includes a carry in.

Cin A B S C0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

fulladder

A

B

Cin

Sum

Cout

Jess Role@UEAB 2006

Truth table for full adderC in

A B S C out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Exercise:

Complete the Karnaugh maps for the Sum and the Carry out columns

Jess Role@UEAB 2006

K maps for sum and carry

AB

C in00

01 11 10

0 1 1

1 1 1

AB

C in

00 01 11 10

0 1

1 1 1 1

Sum – 1 when odd number of inputs is 1 = XOR gate

Carry out - simplifies to 3 pairs

Sum = Cin xor A xor B C out = A.B + A.Cin + B.Cin


Full adder circuitA

B

C in

Count

Sum

Sum = Cin xor A xor B Cout = A.B + A.Cin + B.Cin


Examples• The Multiplexer

– Selects one of 2n inputs and copies it to a single output

– The selected line is determined from the bit combination (address) on the n selection lines

– e.g. 1 from 2 mutiplexer

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

sel a b out

sel ab

00 01 11 10

0

1

out =

a

b

sel

outn = 1

0

1

Jess Role@UEAB 2006

2:1 Multiplexer

sel a b out

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

sel a b out

0 0 ? 0

0 1 ? 1

1 ? 0 0

1 ? 1 1if a is selected, don’t care about b.

AB

sel 00 01 11 10

0 1 1

1 1 1

Jess Role@UEAB 2006

K map for 2:1 Multiplexer

AB

sel 00 01 11 10

0 1 1

1 1 1

output = sel.a + sel.b

Principal can be extended to

4:1 – 2 select lines and 4 data lines

8:1 – 3 select lines and 8 data lines

and so on…

data

sel

out


What you should be able to do:

•Change circuits using one set of gates (eg AND, OR, NOT) to their equivalent using NAND or NOR gates only (and vice versa).

•Be familiar with half-, full- adders and multiplexer circuits.

•Be able to construct and interpret Karnaugh maps with up to 4 input variables.
