Special Gates Combinational Logic Gates

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Special Gates Combinational Logic Gates. Lecture 2. DeMorgan's Law. Converting AND to OR (with some help from NOT) Consider the following gate:. To convert AND to OR (or vice versa), invert inputs and output. Same as A+B!. More than 2 Inputs?. AND/OR can take any number of inputs. - PowerPoint PPT Presentation

Text of Special Gates Combinational Logic Gates

  • Special GatesCombinational Logic Gates Lecture 2

    Prof Jess Role @UEAB 2008

    DeMorgan's LawConverting AND to OR (with some help from NOT)Consider the following gate:Same as A+B!To convert AND to OR (or vice versa),invert inputs and output.

    AB001110011001100101110001

    Prof Jess Role @UEAB 2008

    More than 2 Inputs?AND/OR can take any number of inputs.AND = 1 if all inputs are 1.OR = 1 if any input is 1.Similar for NAND/NOR.

    Can implement with multiple two-input gates, or with single CMOS circuit.

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

    Prof Jess Role @UEAB 2008

  • Jess Role@UEAB 2006Half adderThe sum is XOR operation and the carry an AND:

    ABSC0000011010101101

  • Jess Role@UEAB 2006Examples The half adderThe half adder is a circuit for adding two single bit numbersDevelop a truth table and Boolean expressions for the half adderS and C are the Sum and Carry

    ABSC00011011

    Prof Jess Role @UEAB 2008

    Jess Role@UEAB 2006ExamplesThe full adderDevelop a truth table and Boolean expressions for the full adder, this circuit also includes a carry in.

    fulladderABCinSumCout

  • Jess Role@UEAB 2006Truth table for full adderExercise:

    Complete the Karnaugh maps for the Sum and the Carry out columns

    C inABSC out0000000110010100110110010101011100111111

  • Jess Role@UEAB 2006K maps for sum and carrySum 1 when odd number of inputs is 1 = XOR gateCarry out - simplifies to 3 pairsSum = Cin xor A xor BC out = A.B + A.Cin + B.Cin

    ABC in00011110011111

    ABC in00011110011111

    Prof Jess Role @UEAB 2008

    Jess Role@UEAB 2006Full adder circuitABC inCountSumSum = Cin xor A xor BCout = A.B + A.Cin + B.Cin

    Prof Jess Role @UEAB 2008

    Jess Role@UEAB 2006ExamplesThe MultiplexerSelects one of 2n inputs and copies it to a single outputThe selected line is determined from the bit combination (address) on the n selection linese.g. 1 from 2 mutiplexersel ab0001111001out = abseloutn = 101

  • Jess Role@UEAB 20062:1 Multiplexerif a is selected, dont care about b.

    selabout00000010010101111000101111001111

    selabout00?001?11?001?11

    ABsel00011110011111

    Jess Role@UEAB 2006

  • Jess Role@UEAB 2006K map for 2:1 Multiplexeroutput = sel.a + sel.bPrincipal can be extended to 4:1 2 select lines and 4 data lines 8:1 3 select lines and 8 data lines and so on dataselout

    ABsel00011110011111

    Prof Jess Role @UEAB 2008

    Jess Role@UEAB 2006What you should be able to do:Change circuits using one set of gates (eg AND, OR, NOT) to their equivalent using NAND or NOR gates only (and vice versa).

    Be familiar with half-, full- adders and multiplexer circuits.

    Be able to construct and interpret Karnaugh maps with up to 4 input variables.

    Prof Jess Role @UEAB 2008

    *If there's time, perhaps discuss how all gates can be implemented with NAND (or NOR).Therefore, you can implement any truth table using only NAND (or NOR) gates.*NAND and NOR are not associative.

    Jim Conrads example:NAND(NAND(0,0), 1) = NAND(1, 1) = 0NAND(0, NAND(0,1)) = NAND(0, 0) = 1

    *ABS C0000011010101101s = notA.B + BnotA = A + Bc = A.B*Cin AB000111100010111010A BC000111100001010111SUMCout*A BC000111100001110110out = not(sel).a + sel.b

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