IntroductionThe Xilinx On-Chip Peripheral Bus Double Data Rate Syn-chronous DRAM (OPB DDR SDRAM) controller for Vir-tex™-II and Virtex-II Pro™ FPGAs provides a DDRSDRAM controller which connects to the OPB bus and pro-vides the control interface for DDR SDRAMs. It is assumedthat the reader is familiar with DDR SDRAMs and the IBMPowerPC.
FeaturesThe Xilinx DDR SDRAM Controller is a soft IP coredesigned for Xilinx FPGAs and contains the following fea-tures:
• OPB interface
• Performs device initialization sequence upon power-upand reset conditions
• Performs auto-refresh cycles
• Supports cacheline latencies of 2 or 3 set by a designparameter
• Supports various DDR data widths set by a designparameter
DDR SDRAM Controller Design ParametersTo allow the user to obtain a DDR SDRAM Controller that isuniquely tailored for their system, certain features areparameterizable in the Xilinx DDR SDRAM Controllerdesign. This allows the user to have a design that only uti-lizes the resources required by their system and runs at thebest possible performance. The features that are parame-terizable in the Xilinx DDR SDRAM Controller are shown inTable 1.
0
OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
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LogiCORE™ Facts
Core Specifics
Supported Device Family
Virtex-II Pro, Virtex-II, Virtex™, Virtex™-E, Spartan™-II
Version of Core DDR v1.00b
Resources Used. See Table 8
Min Max
Slices 278 314
LUTs 352 371
FFs 250 307
Block RAMs 0 0
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template
N/A
Reference Designs None
Design Tool Requirements
Xilinx Implementation Tools
5.1i or later
Verification N/A
Simulation ModelSim SE/EE 5.6e or later
Synthesis XST
Support
Support provided by Xilinx, Inc.
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© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any war-ranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Table 1: DDR SDRAM Controller Design Parameters
Grouping / Number
Feature / Description Parameter Name Allowable Values
Default Value VHDL Type
DDR SDRAM Controller Features
G1 Pull Resistors on DDR DQS signals(1)
C_DQS_PULLUPS 0 = DQS signals have internal or external pull down resistors
1 = DQS signals have internal or external pull up resistors
0 integer
G2 Include logic to support OPB bursts
C_INCLUDE_BURST_SUPPORT
0 = don’t include logic to support OPB bursts
0 string
G3 Include support for Registered DIMM
C_REG_DIMM 0 = DDR device is not registered DIMM
1 = DDR device is registered DIMM
0 integer
G4 Target FPGA family C_FAMILY virtex2, virtex2p virtex2p string
DDR SDRAM Device Features
G5 Load Mode Register command cycle time (ps)
C_DDR_TMRD 15000 integer
G6 Write Recovery Time (ps)
C_DDR_TWR 15000 integer
G7 Write-to-Read Command Delay (Tck)
C_DDR_TWTR 1 integer
G8 Delay after ACTIVE command before PRECHARGE command (ps)
C_DDR_TRAS 40000 integer
G9 Delay after ACTIVE command before another ACTIVE or AUTOREFRESH command (ps)
C_DDR_TRC 65000 integer
G10 Delay after AUTOREFRESH before another command (ps)
C_DDR_TRFC 75000 integer
G11 Delay after ACTIVE command before READ/WRITE command (ps)
C_DDR_TRCD 20000 integer
G12 Delay after ACTIVE command for a row before an ACTIVE command for another row (ps)
C_DDR_TRRD 15000 integer
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Allowable Parameter CombinationsThe address range specified by C_BASEADDR and C_HIGHADDR must comprise a complete, contiguous power of tworange such that range = 2n, and the n least significant bits of C_BASEADDR must be zero. The range specified by theseparameters must encompass the DDR SDRAM memory space.
The total data width of the DDR SDRAM devices must be half the data width of the OPB.
DDR SDRAM Controller I/O SignalsTable 2 provides a summary of all Xilinx DDR SDRAM Controller input/output (I/O) signals, the interfaces under which theyare grouped, and a brief description of the signal.
G13 Delay after a PRECHARGE command (ps)
C_DDR_TRP 20000 integer
G14 Average periodic refresh command interval (ps)
C_DDR_TREFI 7800000 integer
G15 Refresh command interval (ns)
C_DDR_TREFC 70300
G16 CAS Latency C_DDR_CAS_LAT 2,3 2 integer
G17 Total data width of DDR devices (2)
C_DDR_DWIDTH 16 integer
G18 DDR address width C_DDR_AWIDTH See note(3) 13 integer
G19 DDR column address width
C_DDR_COL_AWIDTH See note(3) 9 integer
G20 DDR bank address width
C_DDR_BANK_AWIDTH
See note(3) 2 integer
Address Space
G21 Base Address C_BASEADDR Valid address(4) std_logic_vector
G22 High Address C_HIGHADDR Valid address(4) std_logic_vector
OPB Bus Interface
G23 OPB Data bus width C_OPB_DWIDTH 32 32 integer
G24 OPB Address bus width
C_OPB_AWIDTH 32 32 integer
G25 OPB clock period (ps)
C_OPB_CLK_PERIOD_PS
integer
Notes: 1. The DDR DQS signals should either internal or external pull resistors. Set this parameter to indicate if these resistors are pull up
resistors or pull down resistors.2. Data width of DDR devices must be half of the OPB data width.3. C_DDR_AWIDTH + C_DDR_COL_AWIDTH + C_DDR_BANK_AWIDTH + log2(C_DDR_DWIDTH/8) must be < C_OPB_AWIDTH-1.4. The range specified by C_BASEADDR and C_HIGHADDR must comprise a complete, contiguous power of two range such that
range = 2n, and the n least significant bits of C_BASEADDR must be zero.
Table 1: DDR SDRAM Controller Design Parameters (Continued)
Grouping / Number
Feature / Description Parameter Name Allowable Values
Default Value VHDL Type
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Table 2: DDR SDRAM Controller Pin Descriptions
Grouping Signal Name Interface I/OInitial State Description
DDR SDRAM Signals
P1 DDR_Clk DDR O 0 DDR Clock
P2 DDR_Clkn DDR O 1 DDR inverted clock
P3 DDR_CKE DDR O 0 DDR Clock Enable
P4 DDR_CSn DDR O 1 Active low DDR chip select
P5 DDR_RASn DDR O 1 Active low DDR row address strobe
P6 DDR_CASn DDR O 1 Active low DDR column address strobe
P7 DDR_WEn DDR O 1 Active low DDR write enable
P8 DDR_DM DDR O 0 DDR data mask
P9 DDR_BankAddr DDR O 0 DDR bank address
P10 DDR_Addr DDR O 0 DDR address
P11 DDR_DQ_o DDR O 0 Output data to DDR
P12 DDR_DQ_i DDR I Input data from DDR
P13 DDR_DQ_t DDR O 0 3-state control for DDR data buffers
P14 DDR_DQS_o DDR O 0 Output data strobe to DDR
P15 DDR_DQS_i DDR I Input data strobe from DDR
P16 DDR_DQS_t DDR 0 1 3-state control for DDR data strobe buffers
Clock Signals
P17 Clk90_in I System bus clock phase shifted by 90 degrees
P18 DDR_Clk90_in I DDR clock feedback shifted by 90 degrees
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Parameter/Port DependenciesThere a no dependencies between the DDR design parameters and I/O signals.
Connecting to Memory
Memory Data Types and OrganizationDDR SDRAM memory can be accessed as: byte (8 bits), halfword (2 bytes),or word (4 bytes), doubleword (8 bytes),depending on the size of the bus to which the processor is attached. From the point of view of the OPB, data is organizedas big-endian. The bit and byte labeling for the big-endian data types is shown below in Figure 1.
OPB Slave Sig- nals(1)
P19 OPB_Select OPB I OPB select
P20 OPB_RNW OPB I OPB read,not write
P21 OPB_ABus[0:C_OPB_AWIDTH-1] OPB I OPB address bus
P22 OPB_DBus[0:C_OPB_DWIDTH-1] OPB I OPB data bus
P23 OPB_BE[0:C_OPB_DWIDTH/8-1] OPB I OPB byte enables
P24 OPB_seqAddr OPB I OPB sequential address
P25 Sl_xferAck OPB O 0 SDRAM Controller transfer acknowledge
P26 Sl_errAck OPB O 0 SDRAM Controller error acknowledge
P27 Sl_toutSup OPB O 0 SDRAM Controller timeout suppress
P28 Sl_retry OPB O 0 SDRAM Controller retry
P29 Sl_DBus[0:C_OPB_DWIDTH-1] OPB O 0 SDRAM Controller OPB slave data bus
P30 OPB_Clk OPB I OPB clock
P31 OPB_Rst OPB I OPB reset
Notes: 1. Please refer to the IBM OPB Bus Architecture Specification for more detailed information on these signals.
Table 2: DDR SDRAM Controller Pin Descriptions (Continued)
Grouping Signal Name Interface I/OInitial State Description
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Memory to FPGA ConnectionsThe data and address signals at the DDR controller are labeled with big-endian bit labeling (for example, D(0:31), D(0) is theMSB), whereas most memory devices are either endian agnostic (they can be connected either way) or little-endian D(31:0)with D(31) as the MSB.
Caution must be exercised with the connections to the external memory devices to avoid incorrect data and address con-nections. Table 3 shows the correct mapping of DDR controller pins to memory device pins.
Figure 1: Big-Endian Data Types
n n+1 n+2 n+3
0 1 2 3
MSByte LSByte
0 31
MSBit LSBit
Byte address
Byte label
Byte significance
Bit label
Bit significance
n n+1
0 1
MSByte LSByte
0 15
MSBit LSBit
Byte address
Byte label
Byte significance
Bit label
Bit significance
n
0
MSByte
0 7
MSBit LSBit
Byte address
Byte label
Byte significance
Bit label
Bit significance
Byte
Halfword
Word
n
0 1 2
MSB LSB
0 63
MSBit LSBit
Byte address
Byte label
Byte significance
Bit label
Bit significance
Word
n+1 n+2 n+3 n+4 n+5 n+6 n+7
3 4 5 6 7Double
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
DDR Address Mapping
An address offset is calculated based on the width of the DDR data bus. The DDR column address is then mapped to theOPB address bus, followed by the row address and bank address.
The OPB address bus bit locations for the DDR column, row, and bank addresses are calculated as shown in Table 4 andTable 5.
Table 6 and Table 7 show an example of the mapping between the OPB address and the DDR address when the data widthof the DDR is 16 and the data width of the bus is 32, the column address width is 9, the row address width is 13, and the bankaddress width is 2.
Table 3: DDR controller to memory interconnect
Description DDR Signal (MSB:LSB) Memory Device Signal (MSB:LSB)
Data Bus DDR_DQ(0:C_DDR_DWIDTH-1) DQ(C_DDR_DWIDTH-1:0)
Bank Address DDR_BankAddr(0:C_DDR_BANK_AWIDTH) BA(C_DDR_BANK_AWIDTH-1:0)
Address DDR_Addr(0:C_DDR_AWIDTH-1) A(C_DDR_AWIDTH-1:0)
Data Strobe DDR_DQS(0:C_DDR_DWIDTH/8-1) UDQS, LDQS
Data Mask DDR_DM(0:C_DDR_DWIDTH/8-1) UDM, LDM
Table 4: DDR Address offset calculations
Variable Equation
ADDR_OFFSET log2(C_DDR_DWIDTH/8)
COLADDR_STARTBIT C_OPB_AWIDTH - (C_DDR_COL_AWIDTH+ADDR_OFFSET)
COLADDR_ENDBIT COLADDR_STARTBIT + C_DDR_COL_AWIDTH- 2 (A0 is not used)
ROWADDR_STARTBIT COLADDR_STARTBIT - C_DDR_AWIDTH
ROWADDR_ENDBIT ROWADDR_STARTBIT + C_DDR_AWIDTH-1
BANKADDR_STARTBIT ROWADDR_STARTBIT - C_DDR_BANK_AWIDTH
BANKADDR_ENDBIT BANKADDR_STARTBIT + C_DDR_BANK_AWIDTH-1
Table 5: DDR - PLBOPB Address Bus Assignments
SDRAM Address PLBOPB Address Bus
Column Address OPB_ABus(COLADDR_STARTBIT to COLADDR_ENDBIT) & ’0’
Row Address OPB_ABus(ROWADDR_STARTBIT to ROWADDR_ENDBIT)
Bank Address OPB_ABus(BANKADDR_STARTBIT to BANKADDR_ENDBIT)
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
IMPORTANT: Virtex-II and Virtex-II Pro IO pairs share input and output clock signals. Since the DDR registers in the IOblocks use both of the input and output clock signals, the ports assigned to the IO pairs MUST use the same input and outputclocks. Care should be taken when making port IO assignments that the DDR_DQ and DDR_DM signals use the systemclock as the output clock and the DDR_DQS signals use a 90 degree phase shift of the system clock as the output clock.Therefore, a DDR_DQS signal should not be assigned with a DDR_DQ signal or a DDR_DM signal in an IO pair.
Since this DDR controller design utilizes the DDR registers in the Virtex-II and Virtex-II Pro FGPA IO blocks, therefore, thiscontroller is not suitable for other FPGA families.
Since the DDR_DQ and DDR_DQS busses are 3-stateable, the user should either pulldownor pullup these signals in theFPGA IO blocks or external to the FPGA in the board design and set the C_DQS_PULLUPS parameter accordingly. Notethat the DDR controller design will drive the DQS signals to a ’1’ or ’0’ as indicated by this parameter during the IDLE stateso only one DDR controller can be used to control a DDR memory, i.e., two DDR controllers can not share the same DDRmemory.
Table 6: OPB Example DDR Address offset calculations
Variable Value
ADDR_OFFSET log2(16/8) = 1
COLADDR_STARTBIT 32 - (9+1) = 22
COLADDR_ENDBIT 22 + (9-2)= 29
ROWADDR_STARTBIT 22 - 13 = 9
ROWADDR_ENDBIT 9 + 13 -1 = 21
BANKADDR_STARTBIT 9 - 2 = 7
BANKADDR_ENDBIT 7+ 2 -1 = 8
Table 7: DDR -OPB Address Bus Assignments
SDRAM Address OPB Address Bus
Column Address OPB_ABus(22: 29) & ’0’
Row Address OPB_ABus(9:21)
Bank Address OPB_ABus(7:8)
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
DDR Clocking
Clock GenerationThe clocking scheme required in the FGPA and used by the DDR controller core is shown in Figure 2.
Clk and Clk90 Generation
A DCM is required to generate the clock used internal to the FPGA as shown in Figure 2. A 90 degree phase output of theDCM is input to the DDR Controller core and is used to generate the DDR clock and DQS signals. OPB_Clk and Clk90_inare the outputs of a DCM and global buffers.
DDR Clock Generation
The clock output to the DDR SDRAMs is generated using the DDR I/O registers as shown in Figure 3 . The 90 degreephase-shift clock is used to generate the DDR_Clk (and DDR_Clkn) so that the clock is centered in the data output to theDDR.
Figure 2: DDR Clocking
CLKIN
CLKFB
CLK0
CLK90
External Clock
DCM
OPB_Clk
DDR
FPGA
DDR Core
DDR_Clk90_in
DDR_Clk
CLKIN
CLKFB
CLK0
CLK90
DCM
DD
R_C
lk_f
b
CLK CLKn DDR_Clkn
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
DDR Clock Input Synchronization
Another DCM will be required by this design to align the clock output to the DDR registers with the data from the DDR toaccurately register this data. The DDR_Clk output shown in Figure 3 will need to be connected to the DDR_Clk_fb shownin Figure 2 as an external board connection. The Clk90 output of the DDR Clock DCM is input to the DDR Controller coreand is used to clock in the DDR data.
Due to the variation in board layout, the DDR clock and the DDR data relationship can vary. Therefore, the designer shouldanalyze the time delays of the system and set all of the attributes of the phase shift controls of the DCM as needed to insurestable clocking of the DDR data.
DDR SDRAM Controller Design
Block Diagram The Xilinx DDR SDRAM controller consists of the PLB OPB IPIF to provide the bus protocol, 3 state machines to control theDDR SDRAM operation, an I/O module to instantiate the DDR I/O registers for the DDR data interface, and a clock gener-ation module.
The separation of the Command State Machine and the Data State Machine allows for the application of commands to theDDR while data reception/transmission is in progress. Overlapping the DDR commands with the data transfer when access-ing data in the same row of the same bank allows for more optimal DDR operation.
Figure 3: DDR Clock Generation
D0
D1
C0C1
Q
Clk90_in
VCC
VCC
GND
D0
D1
C0C1
QGND
DDR_Clk
DDR_Clkn
instantiated by Platgen orSysGenPro
instantiated by Platgen orSysGenPro
DDR Core
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Init State MachineDDR SDRAMs must be powered-up and initialized in a predefined manner. After all power supplies and the clock are stable,the DDR SDRAM requires a 200uS delay prior to applying an executable command.
The Init State Machine provides the 200µs delay and the sequencing of the required DDR start-up commands.It instructs theCommand State Machine to send the proper commands in the proper sequence to the DDR. This state machine starts exe-cution after Reset and returns to the IDLE state when Reset is applied.
When the initialization sequence has been completed, the INIT_DONE signal asserts.
Note that after Reset has been applied, the 200µs delay is again implemented before any commands are issued to the DDR.The 200µs delay must be accounted for in simulation as well as the delay of the command sequence.
Figure 4: DDR SDRAM Controller Block Diagram
Data State Machine
Command State Machine
Init State Machine
Clock Generation
DDR_DQ_o
DDR_DQS_o
DDR_DM
DDR_Addr
DDR_BankAddr
DDR_RASn
OPB IPIF
OP
B
IO Reg
IPIF
Inte
rfac
e
Write_data, Write_data_en
Write_dqs_en, Write_data_mask
Read_data_en
Addr
RASn, CASn, WEn
BankAddr
DDR_DQ_i
DDR_DQ_t
DDR_DQS_i
DDR_DQS_t
DDR_CASn
DDR_WEn
DDR_CSn
DDR_CKE
DDR_Clk
DDR_Clkn
Clk_DDR_RddataClkClk90 R
ead
Dat
a P
ath
OPB_CLKClk90_in DDR_Clk90_in
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Command State MachineThe Command State Machine provides the address bus and commands signals to the DDR. It sends the DATA_EN signalto the Data State Machine to start the reception/transmission of data. If a burst transaction is in progress or a secondarytransaction has been received, the Command State Machine will send the next command to the DDR while data recep-tion/transmission is still in progress to optimize the DDR operation.
A simplified version of the Command State Machine is shown in Figure 6. For readability, only the major state transitions areshown.
Figure 5: DDR Init State Machine
IDLE
PRECHARGE1
ENABLE_DLL
reset*t200us_end
RESET_DLL
PRECHARGE2
REFRESH1
REFRESH2
SET_OP_DONE
cmd_done
cmd_done
cmd_done
cmd_done
t200ck_end
cmd_donereset
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Data State MachineThe Data State Machine transfers the data to/from the DDR and determines when the specified DDR burst is complete. Itmonitors the PEND_OP signal from the Command State Machine to know if more data transmissions are required. It waitsfor CAS_LATENCY during read operations and signals when the DDR has completed the data transfer for both read andwrite operations. It provides the READ_DATA_EN signal to the input DDR registers and read data FIFO.
Figure 6: DDR Command State Machine
IDLE
ACT_CMD
WAIT_TRRD
READ_CMD WRITE_CMD
PRECHARGE_CMD
REFRESH_CMDLOAD_MR_CMD
cs
load_mr
trcd_end*rd_req trcd_end*(wr_req+write_op)
trp_end
tmrd_end trfc_end
refresh | trefi_end
precharge
done*tras_end
twr_end*tras_end*
write_op*
write_op*
same_row*trrd_end*same_bank
same_row
same_row*trrd_end*
trrd_end
burst*same_row
burst*same_row*trrd_end*
WAIT_TRAS
twr_end*tras_end
done*tras_end
tras_end*twr_end
same_bank
READ_ERR burst+cs
trefi_end+cs
WAIT_TWR
write_op*same_row*same_bank
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
I/O Registers
Control Signals
All control signals and the address bus to the DDR are registered in the IOBs of the FPGA.
Write Data
The DDR I/O registers are used to output the write data to the DDR as shown in Figure 8. Since the clock is being generatedfrom the Clk90 output of the DCM, the CLK0 output is used to clock out the data so that the DDR clock is centered in theDDR data. This also allows a full clock period for the data to get to the IOBs.
DQS is generated from the CLK90 output so that it is centered in the data.
Figure 7: DDR Data State Machine
IDLE
WRITE_DATAREAD_DATA
DONE
pend_write
ddr_brst_end*pend_read
pend_write
pend_write*ddr_brst_end
pend_writepend_read
WAIT_CASLAT
pend_read
tcaslat_end
pend_read
pend_write*pend_read
WRITE_DATA
twr_end
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Read Data
The DDR I/O registers are used to input data from the DDR as shown in Figure 10. The clock output to the DDR is used toclock the input data. This clock is input to a DCM and generates DDR_Clk90_in.
Figure 8: Write Data Path
D
D0
D1
C0C1
Q
Q
CClk
Write_data_en
Write_data[0:C_DDR_DWIDTH-1]
Write_data[C_DDR_DWIDTH to C_DDR_DWIDTH*2-1]
DDR_DQ_t
DDR_DQ_o
instantiated by Platgen orSysGenPro
D
D0
D1
C0C1
Q
Q
C
DDR_DQS_t
DDR_DQS_o
instantiated by Platgen orSysGenPro
Write_dqs_en
Clk90
GND
VCC
DQ
C instantiated by Platgen orSysGenPro
Clk
Write_data_mask DDR_DM
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
During a read cycle, the data strobe signal from the DDR (DDR_DQS) is registered on the rising edge only of DDR_Clk90_inso that it is always high while the DDR is transmitting data. This signal will be used by the Read Data Path logic as the writeenable into a FIFO.
NOTE: It is important to properly set the C_DQS_PULLUPS parameter indicating if the DDR DQS lines are pulled up orpulled down (internally or externally).
Read Data Path LogicThe Read Data Path logic consists of an asynchronous FIFO in which the DDR input data is written from the DDR_Clk90_inand read from the internal FPGA clock. The write enable to the FIFO is the DDR_RdDQS signal which will be high duringDDR data transmission.
Pulldown resistors on these signals insures that DQS is low when neither the DDR or FPGA is driving it. However, if pullupsare used, insure that the C_DQS_PULLUPS parameter is set correctly. Once the FIFO is not empty, the data is read fromthe FIFO and a read acknowledge is generated. This is shown in Figure 10.
Figure 9: DDR Input Data Registers
instantiated by Platgen orSysGenPro
D
C0C1
Q0 DDR_RdData_high
Q1 DDR_RdData_lowDDR_RdData
DQ
C
DDR_Clk90_in
DDR_DQ_i
DDR_RdDQS
CE
instantiated by Platgen orSysGenPro
DDR_DQS_i
ddr_read_data_en
CE
DQ
C
read_data_en
DDR_Clk90_in
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Design Constraints
Timing ConstraintsA timing constraint should be placed on the system clock, setting the frequency to meet the bus timing requirements. A tim-ing constraint should also be placed on the DDR feedback clock to set the frequency of this clock. An example is shown inFigure 11.
Figure 10: Read Data Path
NET "OPB_Clk" TNM_NET = "OPB_Clk";
TIMESPEC "TS_OPB_Clk" = PERIOD "OPB_Clk" 7 ns HIGH 50 %;
NET "Clk90_in" TNM_NET = "Clk90_in";
TIMESPEC "TS_CLK90" = PERIOD "Clk90_in" 7 ns HIGH 50% ;
TIMESPEC "TSCLK2CLK90" = FROM "OPB_Clk" TO "Clk90_in" 2 ns;
NET "DDR_Clk90_in" TNM_NET = "DDR_Clk90_in";
TIMESPEC "TS_DDR_Clk90_in" = PERIOD "DDR_Clk90_in" 7 ns HIGH 50 %;
Figure 11: DDR Timing Constraints
DQ
C
RdDataDIN
WREN
WRCLK
RDEN
RDCLK
DOUT
EMPTY
CLR
Clk
DDR_RdData
DDR_RdDQS
Clk_DDR_Rddata
Empty
RdenRdAck
Read_data_en
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Pin ConstraintsThe DDR I/O should be set to the SSTL2 I/O standard. If external pullups/pulldowns are not available on the DDR DQ andDQS signals, then these pins should be specified to use pullup or pulldown resistors. Pulldown resistors are preferred. Anexample is shown in Figure 12.
Design Implementation
Target TechnologyThe intended target technology is a Virtex-II Pro FPGA.
Device Utilization and Performance BenchmarksSince the DDR SDRAM Controller is a module that will be used with other design pieces in the FPGA, the utilization and tim-ing numbers reported in this section are just estimates. As the DDR SDRAM Controller is combined with other pieces of theFPGA design, the utilization of FPGA resources and timing of the DDR SDRAM Controller design will vary from the resultsreported here.
The DDR SDRAM Controller benchmarks are shown in Table 8 for a Virtex-II Pro -7 FPGA.
Reference DocumentsThe following documents contain reference information important to understanding the Xilinx DDR SDRAM Controllerdesign:
NET "DDR_DQS" IOSTANDARD=SSTL2_I;
NET "DDR_DQS" PULLDOWN;
NET "DDR_DQS" IOSTANDARD=SSTL2_I;
NET "DDR_DQS" PULLDOWN;Figure 12: DDR Pin Constraints
Table 8: DDR FPGA Performance and Resource Utilization Benchmarks (Virtex-II Pro-7)
Parameter Values
(other parameters at default values) Device ResourcesfMAX
(MHz)
C_INCLUDE_BURST_SUPPORT C_REG_DIMM Slices
Slice Flip- Flops
4-input LUTs fMAX
0 0 278 250 352 151
0 1 314 307 371 166
Notes: 1. These benchmark designs contain only the DDR SDRAM Controller without any additional logic. Benchmark
numbers approach the performance ceiling rather than representing performance under typical user conditions.
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
Revision HistoryThe following table shows the revision history for this document.
Date Version Revision
09/19/03 1.0 Initial Xilinx release.
05/20/02 1.1 Update for EDK 1.0
06/20/02 1.2 Revisions for EDK 1.0
07/23/02 1.3 Update for DDR v1_00_b
07/24/02 1.4 Add XCO parameters for System Generator
09/11/02 1.5 Added resource utilizations
10/06/02 1.6 Removed generics/ports relating to the Clk90 and DDR Clock DCMs, updated figures, added C_DQS_PULLUPS generic
01/20/03 1.7 General document cleanup and update
01/31/03 1.8 Added note and cross-reference to the Connecting to Memory section on the first page to the DDR Controller Features
07/21/03 1.9 Update to new template
09/19/03 1.9.1 Update trademarks
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OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) ControllerIntroductionFeaturesDDR SDRAM Controller Design ParametersAllowable Parameter Combinations
DDR SDRAM Controller I/O SignalsParameter/Port DependenciesConnecting to MemoryMemory Data Types and OrganizationMemory to FPGA ConnectionsDDR Address Mapping
DDR ClockingClock GenerationClk and Clk90 GenerationDDR Clock GenerationDDR Clock Input Synchronization
DDR SDRAM Controller DesignBlock DiagramInit State MachineCommand State MachineData State MachineI/O RegistersControl SignalsWrite DataRead Data
Read Data Path Logic
Design ConstraintsTiming ConstraintsPin Constraints
Design ImplementationTarget TechnologyDevice Utilization and Performance Benchmarks
Reference DocumentsRevision History