Numerical Modeling of Self-heating in
MOSFET and FinFET Basic Logic Gates Using
Effective Thermal Conductivity
by
Elham Pak Seresht
A thesis submitted in conformity with the requirements for the degree of MASc
Graduate Department of Mechanical & Industrial Engineering in the
University of Toronto
© Copyright by Elham Pak Seresht (2012)
ii
Numerical Modeling of Self-heating in
MOSFET and FinFET Basic Logic Gates Using
Effective Thermal Conductivity
Elham Pak Seresht
Master of Mechanical Engineering
Mechanical & Industrial Engineering Department
University of Toronto
2012
Abstract
Recent trend of minimization in microprocessors has introduced increasing self-heating effects
in FinFET and MOSFET transistors. To study these self-heating effects, we developed self-
consistent 3D models of FinFET and MOSFET basic logic gates, and simulated steady-state
thermal transport for the worst heating case scenario. Incorporating size-dependent effective
thermal conductivity of thin films instead of bulk values, these simulations provide a more
accurate prediction of temperature rise in the logic gates. Results of our simulations predict
higher temperature rise in FinFETs, compared to MOSFETs. Existence of buried oxide layer
and confined geometry of FinFET structure are determined to be the most contributing to this
higher temperature rise. To connect the results of our simulations to higher scale simulations, we
proposed an equivalent thermal conductivity for each basic logic gate. These values were tested
and found to be independent of the magnitude of chosen boundary conditions, as well as heat
generation rate.
iii
Acknowledgement
First and foremost, I would like to thank Professor Cristina Amon for her invaluable mentorship
and support during my MASc program, which was an exceptional learning experience for me.
This thesis would not have been possible without her help, patience, and guidance. I would like
to extend my appreciation to past and present members of ATOMS lab for their continual
support and camaraderie. Furthermore, I thank Advanced Micro Devices Inc, for funding this
research, and helpful meetings and discussions with Dr. Gamal Refai-Ahmed, Dr. Khalid
Sheltami, and Ms. Lin Zhang.
I would also like to thank my committee members, professor Javad Mostaghimi and professor
Nasser Ashgriz for their time and kind support.
Finally, I would like to thank my husband, Esmaeil Safaei, my mum, MD. Vajihe Modaresi, my
dad, PEng. Mohammad Pak Seresht, my uncle, MD. Peyman Pak Seresht, and my friend, Dr.
Sahba Ghiasi for their kind support and love.
iv
Table of contents
Abstract ...........................................................................................................................................ii
Acknowledgement ........................................................................................................................ iii
Table of contents............................................................................................................................ iv
List of tables .................................................................................................................................. vi
List of figures ................................................................................................................................vii
List of appendices .........................................................................................................................xii
Chapter 1: Introduction
1.1 Background .......................................................................................................................... 1
1.1.1 Self-heating in microelectronics .................................................................................... 1
1.1.2 Challenges in thermal modeling of microelectronics .................................................... 2
1.1.3 Hierarchical thermal modeling framework ................................................................... 3
1.2 Objectives ............................................................................................................................. 7
1.3 Contributions of this work.................................................................................................... 7
1.4 Chapter roadmap .................................................................................................................. 8
Chapter 2: Modeling
2.1 Selecting transistor technology ............................................................................................ 9
2.2 Geometry modeling ............................................................................................................ 11
2.3 Material properties ............................................................................................................. 17
2.4 Heat Generation Modeling ................................................................................................. 19
2.5 Boundary conditions .......................................................................................................... 21
2.6 Governing equations .......................................................................................................... 24
2.7 Meshing .............................................................................................................................. 24
2.8 Grid independence study .................................................................................................... 25
2.8.1 MOSFETs ................................................................................................................... 25
2.8.2 FinFETs ....................................................................................................................... 26
2.9 Approach towards finding equivalent thermal conductivity of FinFET and MOSFET basic
logic gates .................................................................................................................................... 26
v
Chapter 3: Results
3.1 Simulation results ............................................................................................................... 28
3.1.1 Temperature profile ..................................................................................................... 28
3.1.2 Dependency of maximum temperature, ���� on top face temperature, �� ................ 42
3.1.3 Variations of maximum temperature at 90 nm, 65 nm, and 45 nm technology nodes 43
3.1.4 Impact of volumetric heat generation rate magnitude on maximum temperature ...... 45
3.1.5 Impact of bulk vs. effective thermal conductivity on maximum temperature ............ 46
3.2 Results validation ............................................................................................................... 48
3.3 Heat transfer pattern ........................................................................................................... 48
3.4 Equivalent thermal conductivity ........................................................................................ 49
3.5 Dependency of equivalent thermal conductivity on boundary conditions ......................... 51
3.5.1 Equivalent thermal conductivity as a function of volumetric heat generation rate..... 52
3.5.2 Equivalent thermal conductivity as a function of sink temperature ............................ 52
3.5.3 Effect of heat generation distribution on equivalent thermal conductivity ................. 53
Chapter 4: Conclusion
4.1 Conclusion .......................................................................................................................... 55
4.2 Future work ........................................................................................................................ 58
References..................................................................................................................................... 60
Appendices ................................................................................................................................... 69
vi
List of tables
Table 2-1. MOSFET feature sizes in different technology nodes (based on [2, 37, 42, 45]). ... 14
Table 2-2. FinFET feature sizes in different technology nodes (based on [2, 34, 37, 42, 45]) .. 15
Table 3-1. Impact of buried oxide layer (BOX) layer on temperature rise ................................. 41
Table 3-2. Impact of key parameters on self-heating behavior. .................................................. 45
Table 3-3. Bulk and effective thermal conductivity of components (in W/m.K) in FinFET
NAND logic gate at 90 nm technology node [7] ....................................................... 47
Table 3-4. Calculated values for equivalent thermal conductivity (in W/m.K) of MOSFET and
FinFET basic logic gates............................................................................................ 49
Table 3-5. Effective thermal conductivity of heat generation region in FinFET and MOSFET
NAND gate ................................................................................................................ 51
Table 3-6. Impact of heat generation distribution on maximum temperature and equivalent
thermal conductivity .................................................................................................. 54
Table 4-1. Calculated values for equivalent thermal conductivity (in W/m.K) of MOSFET and
FinFET basic logic gates............................................................................................ 57
Table A-1. Effective thermal conductivity of thin films and nanowires [10, 11, 55, 59, 61, 68,
84, 95-101] ................................................................................................................. 82
Table A-2. Summary of published information about heat generation and boundary condition in
MOSFET transistors. ................................................................................................ 87
Table A-3. Summary of published information about heat generation and boundary condition in
FinFET transistors..................................................................................................... 89
Table A-4. The value of volumetric heat generation rate implemented in basic logic gates and
magnitude of total heat generated in each transistor. These values are chosen based
on information retrieved from these references [31, 73]. ......................................... 92
Table A-5. Values of maximum temperature and equivalent thermal conductivity in MOSFET
and FinFET basic logic gates at different technology nodes and with various top
boundary condition temperature. .............................................................................. 94
vii
List of figures
Fig. 1-1. (a) Atomistic level, size scale of order of 1 nm. (b) Transistor level, size scale of
order of 100 nm. This cross section of IBM POWER 6 Microprocessor chip shows
two transistors, out of 790 million that are fabricated in the chip (With permission;
Courtesy of International Business Machines Corporation. Unauthorized use not
permitted) [14]; (c) Logic gate level, size scale of order of a 1 µm. This picture
shows a schematic of a logic gate and interconnects (With permission; Courtesy of
Intel Corporation) [15]; (d) Metallization layers, size scale of order of 100 µm. This
picture shows how layers of transistors and logic gates are stacked on top of each
other, and how they are connected to higher levels by small and big copper
interconnects (colored in orange in this picture) (With permission; Courtesy of
International Business Machines Corporation. Unauthorized use not permitted) [16];
(e) Die level, size scale of order of a few centimeters (With permission; Courtesy of
Intel Corporation) [18]. Pictures of a chip on a die and a Central Processing Unit
package are available in [17, 19] respectively ............................................................ 2
Fig. 1-2. A vision of the hierarchical thermal modeling framework that can be used for
thermal modeling in microelectronics (This diagram was produced by members of
Advanced Thermal/Fluid Optimization, Modeling, and Simulation (ATOMs) lab in
University of Toronto. Pictures inside this diagram are used with permission, and
are courtesy of International Business Machines Corporation [14] and Intel
Corporation [15, 18]. Unauthorized use not permitted). This hierarchical thermal
modeling framework represents the different series of modeling and simulations that
should be performed on systems at different size scales. Through this framework,
the results of simulations at one level are translated into simpler data for use as
inputs for higher level simulations............................................................................... 6
Fig. 2-1 (a) A sketch of the first transistor, invented at Bell Laboratories in 1947; (b) A
model of Bipolar junction transistor; (c) A model of modern planar PNP transistor .. 9
Fig. 2-2. (a) A schematic of typical configuration of a MOSFET. (b) A schematic of typical
configuration of a FinFET (based on the schematic presented in ITRS [1] and Pop
[2]). S, G, and D represent source, gate and drain terminals, respectively ............... 10
viii
Fig. 2-3. Circuit layout of basic logic gates [4, 38]. (a) AND (NAND | NOT), (b) OR (NOR |
NOT), (c) NAND [43], (d) NOR, (e) NOT. ............................................................. 12
Fig. 2-4. A sketch of First MOSFET; G, D, and S, denotes gate, drain and source
respectively. (a) Top view; (b) Side view; (c) Circuit layout (sketches are based on
figures presented in [44]). ......................................................................................... 13
Fig. 2-5. A schematic of a MOSFET layout [45] .................................................................... 14
Fig. 2-6. A schematic of a FinFET layout [34]. ...................................................................... 15
Fig. 2-7. Time history of temperature in a model of transistor (based on Figure 6.29 from
[69]) .......................................................................................................................... 20
Fig. 2-8. A sketch of an example for hierarchical interconnect architecture used in 90 nm
node digital signal processor (based on a photo from Handbook of silicon
semiconductor metrology [37]) ................................................................................ 22
Fig. 2-9. Temperature map of Pentium III chip. Note that temperature varies from 300 to 362
K [75]. ....................................................................................................................... 23
Fig. 2-10. Constant boundary condition of 300 K on the top face of top interconnects (colored
in red) in MOSFET NAND logic gate. The same boundary condition is applied on
other models. ............................................................................................................. 23
Fig. 2-11. Mesh in a MOSFET logic gate. (a) Top view of mesh in MOSFET logic gate. (b)
Side view of mesh in the same gate. The passivation layer is hidden for better
visualization of gate details ....................................................................................... 25
Fig. 2-12. Grid independency in a test case on MOSFET NAND gate. (a) ���� of the logic
gate is plotted vs. the number of nodes. (b) Magnitude of maximum heat flux in z
direction on the interface of silicon substrate and passivation layer (plane 1, as
shown in Fig. A-3). ................................................................................................... 26
Fig. 2-13. Grid independency in a test case on FinFET NAND gate. (a) ���� of the logic gate
is plotted vs. the number of nodes. (b) Magnitude of maximum heat flux in z
direction on the interface of BOX substrate and passivation layer (plane 1, as shown
in Fig. A-8) ............................................................................................................... 26
Fig. 2-14. (a) FinFET NAND gate model; (b) Simple block that will replace the detailed model
in higher level simulations. The thermal conductivity of this block is equal to
calculated equivalent thermal conductivity for MOSFET NAND gate. ................... 27
ix
Fig. 3-1. Temperature profile in MOSFET AND of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut;[Unit: K] .................................................................. 29
Fig. 3-2. Temperature profile in MOSFET OR of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut; [Unit: K]. ................................................................ 30
Fig. 3-3. Temperature profile in MOSFET NAND of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut;[Unit: K] .................................................................. 31
Fig. 3-4. Temperature profile in MOSFET NOR of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut;[Unit: K] .................................................................. 32
Fig. 3-5. Temperature profile in MOSFET NOT of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut;[Unit: K] .................................................................. 33
Fig. 3-6. Temperature profile in FinFET AND of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut; [Unit: K] ................................................................. 34
Fig. 3-7. Temperature profile in FinFET OR of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut; [Unit: K] ................................................................. 35
Fig. 3-8. Temperature profile in FinFET NAND of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut; [Unit: K] ................................................................. 36
x
Fig. 3-9. Temperature profile in FinFET NOR of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut; [Unit: K] ................................................................. 37
Fig. 3-10. Temperature profile in FinFET NOT of 90 nm technology node; (a) 3D view
including all components, (b) 3D view excluding passivation and metallization
layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-
A’ cut, (e) Side view, B-B’ cut; [Unit: K] ................................................................. 38
Fig. 3-11. Maximum temperature in FinFET and MOSFET basic logic gates at 90 nm, 65 nm,
and 45 nm technology nodes, and �� = 300, 350, and400K. These data points are
available in Table A-5................................................................................................ 39
Fig. 3-12. Maximum temperature in MOSFET and FinFET basic logic gates at 90 nm
technology nodes, and �� = 300, 350, and400K. ................................................... 43
Fig. 3-13. Impact of down scaling on the maximum temperature of the modeled gates. .......... 44
Fig. 3-14. Impact of volumetric heat generation rate magnitude on maximum temperature in
MOSFET and FinFET NAND gate. .......................................................................... 46
Fig. 3-15. Temperature profile on FinFET NAND gate (unit: K) when (a) effective thermal
conductivity of thin films and nanowires was implemented in the model, and (b)
when bulk thermal conductivity of materials was implemented. Comparing the two
cases reveals the impact of bulk vs. effective thermal conductivity on the predicted
maximum temperature in FinFET NAND gate ......................................................... 47
Fig. 3-16. Contours of magnitude of heat flux in y direction in A-A' cut of FinFET NAND gate
(for top view, see Fig. 3-8) as a representative of our models. Arrows illustrate the
direction of heat flow ................................................................................................. 49
Fig. 3-17. Calculated equivalent thermal conductivity for FinFET and MOSFET basic logic
gates.. ..................................................................................................................... ....50
Fig. 3-18. Variations of thermal conductivity of heat generation region when the size of heat
generation region (made of crystalline silicon, and main heat transport path is
through in-plane direction) changes at different technology nodes. The characteristic
sizes of heat generation region in FinFETs are 15, 22, and 30 nm at 45, 65, and 90
nm technology nodes, respectively; while in MOSFET, they are 45, 65, and 90 nm
xi
for 45, 65, and 90 nm technology nodes, respectively. The thermal conductivity
value is retrieved from [9] ......................................................................................... 51
Fig. 3-19. Equivalent thermal conductivity of MOSFET NAND, and FinFET NAND as a
function of heat generation rate ................................................................................. 52
Fig. 3-20. Equivalent thermal conductivity of MOSFET NAND, and FinFET NAND when
�� = 300 , when�� = 350 , and when�� = 400 .......................................... 53
Fig. 4-1. A schematic of Pentium III Die Map; functional blocks are marked by black lines
[94] ............................................................................................................................. 58
Fig. A-1. MOSFET AND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 70
Fig. A-2. MOSFET OR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 71
Fig. A-3. MOSFET NAND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 72
Fig. A-4 MOSFET NOR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 73
Fig. A-5. MOSFET NOT gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 74
Fig. A-6. FinFET OR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer
and some of metal interconnects are hidden to provide better visualization; (d) Top
view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut;
(h) Side view, B-B’ cut ............................................................................................. 75
xii
Fig. A-7. FinFET AND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 76
Fig. A-8. FinFET NAND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 77
Fig. A-9. FinFET NOR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden for better visualization; (d) Top
view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut;
(h) Side view, B-B’ cut ............................................................................................. 78
Fig. A-10. FinFET NOT gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation
layer and some of metal interconnects are hidden to provide better visualization; (d)
Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-
A’ cut; (h) Side view, B-B’ cut ................................................................................. 79
Fig. A-11. Top wireframe view of MOSFET gate models. (a) AND; (b) OR; (c) NAND; (d)
NOR; (e) NOT .......................................................................................................... 80
Fig. A-12. Top wireframe view of FinFET gate models. (a) AND; (b) OR; (c) NAND; (d)
NOR; (e) NOT .......................................................................................................... 81
Fig. A-13. Temperature dependence of effective thermal conductivity of selected thin films and
nanowires. These materials are commonly used in logic gate and transistor
fabrication [11, 84, 98-102]. ..................................................................................... 84
Fig. A-14. Size dependence of effective thermal conductivity of selected thin films and
nanowires. These materials are commonly used in logic gate and transistor
fabrication [9-11, 55, 61, 66, 72, 77, 95, 103, 104]. ................................................. 85
Fig. A-15. Temperature dependence of bulk thermal conductivity of commonly used materials
in logic gate and transistor fabrication [84, 105]. ..................................................... 86
xiii
List of appendices
Appendix I - MOSFET and FinFET logic gate models ............................................................... 70
Appendix II - Wireframe layout of MOSFET and FinFET logic gate models ............................ 80
Appendix III - Effective thermal conductivity of thin films and nanowires ............................... 82
Appendix IV - Summary of boundary condition and heat generation details available in
literature ....................................................................................................................................... 87
Appendix V - Internal heat generation implemented in models .................................................. 92
Appendix VI - Simulation results ................................................................................................ 94
1
Chapter 1: Introduction
1.1 Background
1.1.1 Self-heating in microelectronics
Applying an electric voltage on two ends of a material provides the free electrons inside that
material with enough energy to move from the end with higher electric potential towards the end
with lower electric potential. Resistance of material’s atomic structure against this motion
results in releasing some of electrons’ kinetic energy in the form of atomic lattice vibration
(heat). In other words, resistance of a material against passage of electric current through it
results in dissipation of energy by releasing heat. This phenomenon is called Joule heating, and
when it occurs in microelectronics, it is generally referred to as self-heating [1].
Recent trend of minimization in the structural elements of nano scale electronics [2],
incorporation of new materials with poor thermal conductivity [1], and the transition towards
geometrically confined device structures [1], e.g., fin field effect transistors (FinFET), has
introduced an increasing self heating rate and thus increasing local temperature in the
components with nano scale feature sizes [1, 2]. This temperature rise applies extreme thermal
stress on the material, which may result in material meltdown and thus system failure. Also,
temperature rise changes electrical resistance of the material, which affects the output electric
current of the system. Effective heat removal from these hot regions is vital for reliable
functioning of such devices. Therefore, knowledge of heat transfer inside these devices, and a
model that predicts temperature profile inside a microelectronic device are quite necessary.
2
1.1.2 Challenges in thermal modeling of microelectronics
Building a detailed model of a die that includes all the transistors and interconnects, and then
running simulations on such model is computationally impossible. This is due to multiple orders
of magnitude of length scales [3], from a few nanometers at atomistic level (see Fig. 1-1(a)), to a
few millimeters at die level (see Fig. 1-1(e)), and also because of large number of transistors that
are fabricated in a die [2] (typically of order of hundred millions). Therefore, a hierarchical
framework must be adopted through which, the outcome of simulations in one level, is
translated into simpler input data for higher level simulations. The size scale levels that are
usually considered for hierarchical thermal modeling of microprocessors, i.e., atomistic level,
transistor level, logic gate level, metallization layers level, chip level, and die level are shown in
Fig. 1-1.
© IBM
© Intel
(a) (b) (c)
© IBM
© Intel
(d) (e)
Fig. 1-1. (a) Atomistic level, size scale of order of 1 nm. (b) Transistor level, size scale of order of 100
nm. This cross section of IBM POWER 6 Microprocessor chip shows two transistors, out of 790 million
that are fabricated in the chip (With permission; Courtesy of International Business Machines
Corporation. Unauthorized use not permitted) [14]; (c) Logic gate level, size scale of order of a 1 µm.
This picture shows a schematic of a logic gate and interconnects (With permission; Courtesy of Intel
Corporation) [15]; (d) Metallization layers, size scale of order of 100 µm. This picture shows how layers
of transistors and logic gates are stacked on top of each other, and how they are connected to higher
levels by small and big copper interconnects (colored in orange in this picture) (With permission;
Courtesy of International Business Machines Corporation. Unauthorized use not permitted) [16]; (e) Die
level, size scale of order of a few centimeters (With permission; Courtesy of Intel Corporation) [18].
Pictures of a chip on a die and a Central Processing Unit package are available in [17, 19] respectively.
3
The focus of our research is on logic gate level of a microprocessor. A logic gate is a set of
transistors (acting as electronic switches) that are connected to each other by metal wires
(known as interconnects) [4]. When an electric pulse is being applied on the input terminals of
each logic gate, the logic gate creates a specific series of on and off electric pulse on its output
terminal. All logic gates are a combination of basic logic gates; AND, OR, NAND, NOR, and
NOT. Basic logic gates are considered as an elementary building block of a digital circuit [4].
1.1.3 Hierarchical thermal modeling framework
Atomistic level simulation is the first level of the thermal modeling hierarchical framework (see
Fig. 1-2). At this level, interactions of energy carriers with atomic structure are being modeled
and studied using Molecular Dynamics (MD) simulations (e.g., [5, 6], some of the results
reported in [7]), Lattice Dynamics (LD) calculations (e.g., [8-10]), Monte Carlo simulations
(e.g., [1]), and lattice Boltzmann modeling (LBM) (e.g., [11]). In metallic materials, main
energy carriers are electrons, while in semiconductor materials, phonons, which are quantum of
the vibration of atomic lattice structure, contribute most to energy transport [12, 13]. It should
be noted that Fourier equation, which is usually used to describe thermal transport in bulk
systems, fails to capture the non-continuum effects that occur in components with very small
dimensions [11] (the non-continuum effects are briefly discussed in Section 2.3).
The outcome of atomistic level simulations is the information about interactions of energy
carriers with lattice structure (see Fig. 1-2). This information is then analyzed and thermal
properties of thin films and nanowires of materials (see Fig. 1-2) are found. Studies have shown
that thermal conductivity of thin films and nanowires of a material (termed as effective thermal
conductivity) are much lower than their bulk values (e.g., [7, 13, 20]). Underlying physics of
transport phenomenon is discussed elsewhere [12, 13].
Using atomistic level modeling tools to study heat transfer in transistor and gate level is
computationally expensive, and even impossible for larger systems. Therefore, in transistor and
gate level simulations (size scale of order of 1 µm, as shown in Fig. 1-1(b) and Fig. 1-1 (c)),
other tools should be employed to study the thermal transport. According to published literature,
there are two promising tools that produce relatively accurate results in a short time: thermal
resistance network, and modified Fourier-based approach.
4
Pop et al. introduced a thermal resistance network (or circuit), in which a thermal resistance is
defined for each device portion using the portion’s size, and effective thermal conductivity [21].
Using these thermal resistances, and some information from Monte Carlo simulations for heat
generation [22], an equivalent 2D thermal circuit is built for the transistor. Pop et al. used this
model to explore the sensitivity of device temperature to the scaling of device elements [21].
Swahn and Hassoun employed the same approach and extended it to 3D thermal resistance
network [23]. Using this 3D thermal resistance network, they studied the electro-thermal
properties of a multi-fin FinFET, and investigated the effect of fin scaling, and number of fins
on device temperature [23].
Nabovati et al. introduced a modified Fourier-based approach that suggests use of effective size-
dependant thermal conductivity instead of bulk thermal conductivity in Fourier equation [24].
This modification in Fourier equation enables it to capture sub-continuum effects that occur in
systems with characteristic sizes comparable to mean free path of energy carriers [24].
As described earlier, the first step in building a thermal resistance network is assuming
determined directions to be the main directions of heat transfer (thus, ignoring the effect of other
directions in thermal transport). For each component in these main directions, a thermal
resistance is defined, which replaces the component in thermal model. Considering that
transistors are continuous systems through which heat is transferred in all directions, defining
finite directions for heat transfer is a discretization of thermal transport. Thus, a thermal
resistance network model is always associated with uncertainties and loss of data that comes
with such discretization approach.
Simulations on transistors and logic gates are considered the second level of the hierarchy. As
described earlier, thermal resistance network, Lattice Boltzmann Modeling and modified
Fourier-based approaches are the common tools that are used in thermal simulations at transistor
and logic gate level. In this research, we follow a modified Fourier-based approach, to simulate
heat transfer in our 3D models of basic logic gates, so that the results would account for
continuity of thermal transport phenomena and would consider all directions of heat transfer.
Implementing size dependent effective thermal conductivity of thin films and nanowires, we
used the outcome of atomistic level simulations, which helps providing a better prediction of
temperature rise in these basic logic gates. To connect transistor and gate level simulations to
higher levels of the thermal modeling hierarchy, results of transistor and gate level simulations
5
must be simplified. These simplified results should be such that they could be easily
incorporated in bigger systems, like die, where more than 100 million transistors are being
studied in one model. In our research, we calculate an equivalent thermal conductivity for each
basic logic gate. In higher level simulations, each logic gate can be replaced by a simple cube of
equivalent thermal conductivity that has the same volume as the logic gate, and generates the
same amount of heat.
Die level simulations are the next level of the hierarchy. In this level, the whole die, with its
millions of logic gates and wires, is the subject of study. Since modeling all the components of
these logic gate and wires is not possible, a simplified form of the logic gates should replace
them. By doing so, the effect of each logic gate is still being taken into account while the
unnecessary details are being ignored. Using Fourier and Fourier-based approaches at die level
simulations, the major effects of logic gates on one another, and their placement on the die is
being studied, so that possible solutions for optimized floor map of the die could be presented
[25-33]. Such floor map identifies the best locations for each group of logic gates on the die so
that (i) the heat that is being generated by them could be effectively removed from the die, and
(ii) this heat generation, and heat removal would affect other parts of die in the least possible.
Predicting the temperature map of the die and optimizing it is considered the main goal of die
level simulations. This temperature map can then be used for thermal management purposes at
the next level of simulations.
Package level simulations, where the control processing unit package and its fan are the subject
of study, are the last level of hierarchy. The simplified outcome of die level simulations, i.e., the
temperature map of the die, is considered as an input to package level simulations. Using
Fourier, and Fourier-based approaches, designers investigate various thermal management
techniques for proper heat removal from the die.
In this research, we are focusing on the logic gate simulations. This means that our simulations
are at the third level of the thermal modeling hierarchy. By incorporating the size-dependent
effective thermal conductivity of materials into the components of our MOSFET and FinFET
basic logic gates models, we used the outcome of lower level simulations. Studying the thermal
transport in these models, we investigate the maximum temperature of these logic gates, and by
introducing the equivalent thermal conductivity for each basic logic gate, we wish to simplify
the outcomes of our simulations for easier implementation in higher level simulations.
6
Fig. 1-2. A vision of the hierarchical thermal modeling framework that can be used for thermal modeling
in microelectronics (Pictures inside this diagram are used with permission, and are courtesy of
International Business Machines Corporation [14] and Intel Corporation [15, 18]. Unauthorized use not
permitted). This hierarchical thermal modeling framework represents the different series of modeling and
simulations that should be performed on systems at different size scales. Through this framework, the
results of simulations at one level are translated into simpler data for use as inputs for higher level
simulations.
© IBM
© Intel
© Intel
Lattice Dynamic calculation or
Molecular Dynamics simulations or
Lattice Boltzmann Modeling
Modified Fourier-based approach and/or
Lattice Boltzmann Modeling
Fourier and
Modified Fourier-based approach
Simulation tools ↓
Fourier and
Modified Fourier-based approach
die
fan
Systems under study ↓
Information and data
about interactions of
energy carriers with
lattice structure
Effective thermal
properties of thin films
and nanowires
Equivalent thermal
properties of transistors
or basic logic gates
Temperature map of die
7
1.2 Objectives
This research aims to study heat transfer at gate level of microprocessors. Metal oxide
semiconductor field effect transistors (i.e., MOSFETs), and fin field effect transistors (i.e.,
FinFETs) are the two types of transistors that are currently used in fabrication of
microprocessors [2, 34, 35]. Therefore, we aim to perform a comprehensive study of heat
transfer in 3D self consistent models of basic logic gates, i.e., AND, OR, NAND, NOR, and
NOT, that are built using MOSFETs or FinFETs. We also investigate the general pattern of heat
flux in these gates, and study the effect of scaling on self heating of the device.
To connect to higher level simulations, this research aims to use the results of study of basic
logic gates and provide data that could be easily incorporated in bigger models and would help
in predicting temperature profile in those systems.
1.3 Contributions of this work
In this research, first, we developed self consistent 3D models of MOSFET and FinFET basic
logic gates. Then, steady-state heat transfer in these models was simulated using ANSYS
software. Following the modified Fourier-based approach that was proposed by Nabovati et al.
[24], effective size-dependent thermal conductivity of thin films and nanowires was employed
in the simulations instead of bulk thermal conductivity of those materials [20]. Results of these
simulations were studied and temperature rise in each logic gate was reported. Then, each logic
gate was replaced by a simple block of the same total volume that generates the same total heat.
A thermal conductivity, hereby called equivalent thermal conductivity, was assigned to each
block such that the block would experience the same maximum temperature as its corresponding
detailed gate model.
Using this approach, we calculated equivalent thermal conductivity of ten different MOSFET
and FinFET basic logic gates. Calculated values of equivalent thermal conductivity are the
output of this research and can be used as input in higher level simulations, where each logic
gate would be replaced by a simple block of its equivalent thermal conductivity. For the sake of
method validation, we studied the dependency of calculated equivalent thermal conductivity on
the magnitude of boundary conditions, and rate of heat generation.
8
This work is novel as it is the first to employ modified Fourier approach in 3D detailed models
of ten different MOSFET and FinFET basic logic gates. Also, the approach that we took in
calculating an equivalent thermal conductivity for each basic logic gate is new, and can be used
for other logic gates of any configuration and technology.
1.4 Chapter roadmap
This thesis consists of four chapters. Chapter 1 explains self heating in microelectronics, and
introduces the background information and challenges associated with thermal modeling of
microelectronic devices. Chapter 1 also presents the objectives of this research and describes
how this work differs from similar work in this field. In Chapter 2, details of the logic gate
models, and the methodology of this study are discussed. Chapter 3 reports the results of
simulations and addresses the effect of scaling on self heating of the device. Chapter 4
concludes the outcome of this research and summarizes the contributions of present work. Some
suggestions are also presented for improving this work.
9
Chapter 2: Modeling
2.1 Selecting transistor technology
The basic configuration of the first bipolar junction transistor, built in 1947 [36], is shown in
Fig. 2-1, to represent the main components of a transistor. Emitter (E), base (B), and collector
(C) are the three terminals of a transistor. In modern transistors, these terminals are named as
source (S), gate (G), and drain (D), respectively. The wires that apply electric voltage on these
terminals are known as connectors or interconnects.
(a)
(b)
(c)
Fig. 2-1 (a) A sketch of the first transistor, invented at Bell Laboratories in 1947; (b) A model of Bipolar
junction transistor; (c) A model of modern planar PNP transistor.
10
Since 1947, much research works has been done on improving the design of transistor layout,
configuration, thermal and electrical properties of materials used in its fabrication, and tools that
can ease the manufacturing process. Prior to 32 nm technology, transistors with planar
configuration, such as metal oxide semiconductor field effect transistors (MOSFET) were
commonly fabricated in microprocessors. As semiconductor technology improves, smaller and
more geometrically confined devices are built [36, 37]. Transistors with planar configuration are
incapable of such miniaturization, and show degraded functionality (high leakage current, and
degraded switching characteristics for example) [34-37]. Therefore, researchers proposed
hundreds of different innovative configurations, and new materials that can overcome the
limitations of planar configuration. Transistors with non planar configuration, such as FinFETs
are the modern transistors that are commonly fabricated in recent microprocessors. Studies
predict that FinFETs enables device down scaling to 20 nm technology node.
In this research, we selected MOSFETs, as a successful planar transistor configuration, and
simple FinFETs, as successful non-planar transistor configuration that are widely used in
manufacturing microprocessors and CPUs [4, 34, 37]. A schematic of typical configuration of a
MOSFET as well as a FinFET are shown in Fig. 2-2. The area colored in red is channel
extension region close to drain, where most of heat generation occurs [4, 36, 38-41]. In field
effect transistors, the electrical conductivity of the channel is controlled by the electric field
induced by the voltage that is applied on source and drain [34, 36, 37].
(a) (b)
Fig. 2-2. (a) A schematic of typical configuration of a MOSFET. (b) A schematic of typical
configuration of a FinFET (based on the schematic presented in ITRS [1] and Pop [2]). S, G, and D
represent source, gate and drain terminals, respectively.
11
2.2 Geometry modeling
To the best of author’s knowledge, published works in this field generally lack the detailed
information about the dimensions, and exact configuration of their model. Therefore, building
models that are exactly the same as the previously published models is not possible. Moreover,
the present research is the only published research that has done a comprehensive study of heat
transfer in all FinFET and MOSFET basic logic gates. Therefore, by putting together available
information from different sources, we found the best approximations for the dimensions and
sizes that were not available in literature.
Depending on the general circuit architecture of each microelectronic device, details of circuit
layouts of a logic gate may be slightly different in each device. However, the general
configuration of each logic gate remains the same for all different systems. In this work, we
focused on most geometrically confined structures (which would result in most severe self
heating) for each gate. The most geometrically confined structure refers to the configuration in
which the components have the least spacing from one another. Figure 2-3 shows the circuit
layout of basic logic gates AND, OR, NAND, NOR, and NOT, where source and drain of each
transistor is denoted by S and D respectively. It should be noted that circuit layout of FinFET
and MOSFET structures is the same, while the physical layout is different due to differences in
the transistor structure.
Based on the circuit layout design of a microelectronic device, the physical layout of the device
is built. In this research, we built the three dimensional models of basic logic gates using the
same strategies and rules that are generally used in this field [2, 4, 37, 42], and will be briefly
introduced here.
12
(a) (b) (c)
(d) (e)
Fig. 2-3. Circuit layout of basic logic gates [4, 38]. (a) AND (NAND | NOT), (b) OR (NOR | NOT), (c) NAND [43], (d) NOR, (e) NOT.
D
S
D
S
D S D S
S D D S
D
S
D
S
D
S
D
S
D
S
D
S
D
S
D
S
D
S
D
S
S
D
D
S
D
S
D
S
D
S
D
S
13
Figure 2-4 displays the first MOSFET along with the transistor’s side view, and its circuit layout
[44]. Transistor features are colored for better recognition. Using the information presented in
Fig. 2-4, we could visualize the physical layout of a gate by its circuit layout.
(a) (b) (c)
Fig. 2-4. A sketch of First MOSFET; G, D, and S, denotes gate, drain and source respectively. (a) Top
view; (b) Side view; (c) Circuit layout (sketches are based on figures presented in [44]).
The next step is sizing these different features in the physical layouts. As explained before, each
logic gate is a combination of transistors linked together by a specific pattern (circuit layout).
Therefore, sizing a typical MOSFET and FinFET transistor is the next step in modeling. Feature
sizes in semiconductor technology depend on the technology node that the device is being built
on. In other words, size of a component in one technology node is different than the size of the
same component in another technology node. Semiconductor technology generally uses half
pitch, which is approximately half of the distance between source and drain in a transistor, to
identify a technology node [2]. Ratio of different dimensions of a gate with respect to one
another remains approximately constant in different technology nodes. Therefore, normalized
length, width, and height of features are usually used to show the general layout of a transistor.
In semiconductor technology, Lambda (�), which is one half of the “minimum” mask dimension
(typically the length of a transistor channel in FinFETs, and transistor gate in MOSFETs), is
used to normalize the length of different features [2, 36]. As shown in Fig. 2-5, half pitch in
each technology node is approximately equal to 3�.
D
S
G
G
D S
G
D S
14
Fig. 2-5. A schematic of a MOSFET layout [45].
Table 2-1. MOSFET feature sizes in different technology nodes (based on [2, 37, 42, 45]).
Year of introduction 2002 2006 2008
Technology node, (≅ 3� ) [nm] 90 65 45
Lambda, ( � ) [nm] 30 22 15
Sidewall spacer thickness , ���, (≅ 0.63�) [nm] 19 14 10
Extension junction depth, Xj, (≅ �) [nm] 30 22 15
Contact junction depth, Xjc, (≅ 3�) [nm] 90 65 45
Gate length, (≅2�), [nm] 60 44-45 30
Source or drain length, (≅3�), [nm] 90 65-66 44-45
Channel extension length, (≅3.5�), [nm] 90-105 65-77 45-52.5
Metal path (a.k.a. interconnect) length, and width
(≅ �), [nm]
30 22 15
The features of a typical FinFET transistor structure are shown in Fig. 2-6 and the sizing
information is reported in Table 2-2.
Xj Xjc
Polysilicon gate
Silicon dioxide side wall spacer (isolator) Metal path
tsp Gate length, LG
Pitch
Channel
extension
15
Fig. 2-6. A schematic of a FinFET layout [34].
Table 2-2. FinFET feature sizes in different technology nodes (based on [2, 34, 37, 42, 45]).
Year of introduction 2002 2006 2008
Technology node, ( ≅ 3� ) [nm] 90 65 45
Lambda,( � ) [nm] 30 22 15
Gate length, (≅ 3�), [nm] 90-125 55-65 38-45
Gate height, (≅ 3.5�), [nm] 105-110 75 55-65
Gate oxide height, (≅ 0.5 �), [nm] 14-15 11-13 7-8
Fin width, (≅ � -1.5 � ) [nm] 30-45 22-36 15-25
Fin height, (≅2.5� -3.5 � ) [nm] 75-90 55-72 38-60
Fin pitch (a.k.a. Fin spacing), (≅ � ) [nm] 30 22 15
Source or drain length, (≅3�), [nm] 90 65-66 44-45
Metal path (a.k.a. tungsten contact) length, and
width (≅ �), [nm]
30 22 15
Interconnect height, (≅ 3�), [nm] 90 65 45
Fin spacing (fin pitch)
Fin width, WFin
Gate length, LG
Fin height, HFin
16
The relations between size, and spacing of different features, are generally referred to as
Lambda rules (also known as physical layout design rules) [36, 37, 42, 46]. Based on Lambda
rules, the minimum spacing of each two separate electrically active components should be no
less than�, and usually filled with silicon dioxide as an isolator. The length and width of active
electric regions that are in contact with metal paths (i.e., source, grain, and gate pads) should be
about 3 times the length and width of metal path. Since metal paths length and width are usually
chosen to be �, the length and width of source, drain, and gate pads are close to 3�. In order to
create a uniform electric field inside the active region (that begins from source, and continuing
through channel, and channel extension, and ending in drain), and to avoid affecting electric
fields on neighbouring transistors, metal paths are usually placed in the middle of the top surface
of source and drain. The depth of source and drain, and their doping concentration are dictated
by the electric voltage of the device. The gate components, both in MOSFETs and in FinFETs,
are designed to keep the shape of the electric field inside the active region, and control leakage
current, and the height of active region of the gate is not smaller than0.5�. For constructing a
logic gate, multiple transistors, all of the same size, shape, and material, were first modeled in a
silicon substrate and then connected to each other by copper interconnects. The Lambda rules
that were discussed here were based on the information available in [43, 45, 47-53]. These rules
were the rules that we used to build our models of basic logic gates. We modeled our gates
based on the most geometrically confined sets of Lambda rules so that the most severe case of
self heating (worst case scenario) would be simulated.
The configuration of FinFET devices allows placement of multiple source-channel-drain pairs,
(termed as fin in FinFETs) in one FinFET transistor. The number of fins in our models was
chosen consistent with those previously repeated in Singh et al. [31]. However, Swahn et al.
studied how the maximum temperature of device changes when number of fins increases [23].
In this study, however, we do not intent to study the effect of number of fins on our results.
Table 2-1, and Table 2-2 report the size of transistor feature, chosen based on Lambda rules and
available information in literature [2, 37, 42, 45]. Figures A-1 to A-10 display our MOSFET and
FinFET basic logic gate models. Top wireframe view of all gates is available in Fig. A-11, and
Fig. A-12 of appendix.
17
2.3 Material properties
Thermal conductivity of nanoscale thin film or nanowires of materials are found to be much
lower than their bulk values [24]. The sub continuum effects that occur at these nanoscale size
result in this lower thermal conductivity. These sub continuum effects are briefly introduced in
this section, and thermal conductivities of thin films and nanowires of materials, which are used
in our models, are reported in Table A-1.
In semiconductor materials, heat is transported through the vibration of atoms [12, 54]. In
metallic materials, however, electrons are the dominant energy carriers [12, 54-57]. In nanoscale
electronic devices (e.g., transistors), length scales of a device becomes comparable to the mean
free path of energy carriers (i.e., phonons and/or electrons, whose mean free paths are of order
of nanometer) [20, 21, 56]. In order to predict thermal transport in such small systems, the study
of energy carriers’ behavior becomes important [54, 11]. In such devices, sub-continuum
effects, such as a temperature jump at the system boundaries and reduced thermal conductivity,
are observed [20, 58, 59].
Conventional methods for modeling bulk thermal transport, such as the Fourier heat equation,
fail to capture these sub-continuum effects. To address this issue, atomistic-level numerical
methods have been developed to model transport of energy carriers [54, 60-62]. However, the
complex nature and high computational costs of these methods have hindered their use in
problems with multiple length scales. The huge computational costs of these methods prevent us
from applying them to any system larger than a few tens of micrometers. Therefore, a multi-
scale modified Fourier heat equation, which is capable of capturing sub-continuum effects and
yet keeps its superior position in the diffuse regime, is very desirable in many industrial
applications [11]. Furthermore, the wide selection of commercially available Fourier-based
packages, which are more efficient at large length scales, emphasizes on the importance of
modified Fourier-based methods.
The sub-continuum effects impact the nanoscale thermal transport in two different ways: (i)
reduced heat flux, and (ii) boundary temperature jump [24]. The reduced heat flux is formulated
in terms of an effective thermal conductivity. Using this effective thermal conductivity in the
Fourier heat equation predicts a heat flux that includes sub-continuum effects and is comparable
to that predicted from atomistic-level techniques. It is important to note that the effective
18
thermal conductivity and observed temperature jump at the system boundaries are different
manifestations of the effect of the systems boundaries [24]. We provided a review of available
data and relations in the literature for effective thermal conductivity of thin films and nanowires
of material here, and this information enables designers to introduce an effective thermal
conductivity into the Fourier-based steady-state simulations.
In order to accurately model thermal transport in an electronic device that includes nano-scale
parts of different materials (e.g., thin films and nanowires), we should determine the effective
thermal conductivity of thin films and nanowires as a function of their characteristic sizes.
However, finding the size- and temperature- dependence of thermal conductivity of thin films
and nanowires of materials is a challenging problem. Our research group has done an extensive
work on predicting the size-dependent effective thermal conductivity of silicon thin films and
nanowires. Details of our research is explained in Turney et al. [60], Sellan et al. [9], Turney et
al. [63], Turney et al. [8, 64, 65], Sellan et al. [66], and McGaughey et al. [10].
In this work, we reviewed most recent available data and relations from literature to find
effective thermal conductivity of copper (Cu), silicon (Si), polyimide, and silicon dioxide (SiO2)
thin films, as well as copper and tungsten nanowires, as a function of their characteristic length
and/or temperature. Details of these relations and data are available elsewhere [11]. Details of
effective thermal conductivity of selected materials that were implemented in our models are
reported in Table A-1, and also plotted in Fig. A-13 and Fig. A-14 in appendix.
As reported in Table A-1, thermal conductivity of thin films of materials depends on their
characteristic sizes, and is much lower than their bulk thermal conductivity. This is because in
films with such small characteristic sizes (film thickness is close or smaller than the mean free
path of energy carriers), the energy carriers interactions with film boundaries has an important
effect on the resistance of film against motion of energy carriers. In other words, in films with
such small thickness, an energy carrier would experience more collisions (representative of
resistance against motion), both with other energy carriers and with the boundaries of the film,
than it would have experienced in a bulk of material, where boundaries are far apart. The
general pattern of effective thermal conductivity of thin films shows that as film thickness
increases, effect of boundaries becomes less important, and thus effective thermal conductivity
of the film increases. By increasing the film thickness, the effective thermal conductivity of thin
films approaches the bulk thermal conductivity.
19
The effect of temperature on mean free path of main energy carriers in a material, determines
how effective thermal conductivity would vary as temperature changes. In copper, the main
energy carriers are electrons, and their mean free path slightly decreases as temperature
increases [55]. As a result, effective thermal conductivity slightly decreases (see Fig. A-3). In
semiconductors, the main energy carriers are phonons. As temperature increases in crystalline
silicon thin films, mean free path of phonons slightly decreases and thus effective thermal
conductivity decreases. In silicon dioxide on the other hand, mean free path of phonons slightly
increases when temperature increases, resulting in slightly higher effective thermal conductivity
at higher temperatures. The underlying physics of this behavior is available in details elsewhere
[54]. As shown in Fig. A-3, the change in effective thermal conductivity of material within the
range of temperature that our models are working, is very small, and thus negligible. Therefore,
in our models, we implemented size-dependent effective thermal conductivity. Figure A-14
displays bulk thermal conductivities of copper, tungsten, crystalline silicon, crystalline silicon
dioxide, and amorphous silicon dioxide as a function of temperature.
2.4 Heat Generation Modeling
Electric charge transport in a semiconductor device is strongly coupled with thermal transport
[20, 67, 68]. In other words, when electrical charges transport through transistors, their
interactions with atomic lattice releases heat (i.e., self heating).
When electric pulses (on/off discharge) is brought to transistors via interconnects, the electric
charges move away from the source region and towards drain. When the electrical discharge
happens in the rapid switching of the electric pulses, the heat generation rate changes from zero
to its peak value (see Fig. 2-7) [1, 33]. As a result, the temperature of the device increases with
the first on/off cycle and then begins to cool down when the next on/off cycle occurs and
increases the temperature again (see Fig. 2-7). This time, temperature rises to a temperature
slightly higher than the last peak temperature (that occurred in previous on/off cycle). The rate
of this increase, however, decreases over time. As a result, if the system is given enough time,
the maximum temperature of on/off cycle will become similar to one another. Implementing
maximum heat generation rate in our models, it is this state, and this maximum temperature that
20
we aim to model in our simulations because this maximum temperature represents the worst
case scenario of self heating in a transistor, which we intend to model.
One of the main challenges of present research was that published works in 3D models of
transistor generally lack detailed information about exact magnitude, size, and location of heat
generation source. Moreover, coupled electro-thermal nature of this problem adds to challenges
in heat generation modeling [1]. Literature review reveals that the main location of heat
generation both in MOSFETs and FinFETs is in the channel extension region close to drain [20,
67, 68, 73]. Therefore, in our simulations, we assumed a uniform lumped volumetric heat
generation source in the channel extension region in both types of logic gates.
Fig. 2-7. Time history of temperature in a model of transistor (based on Figure 6.29 from [69]).
In order to calculate the heat generation rate, Singh et al. used TAURUS device simulator, and
reported the volumetric heat generation rate due to self-heating in FinFET NOT, NAND, and
NOR logic gates [31]. Based on device simulations, Sinha et al. estimated the peak power
density inside a transistor at 90 nm technology node, to be approximately 5 × 10��W/m� and
focused in channel extension region close to drain [70]. Sinha et al. expects this number to reach
65 × 10��W/m� in an 18 nm ultra thin body SOI device [70]. Using Monte Carlo simulation
Over time, the maximum temperature of on/off cycle will become the same
Temperature
increases with
each pulse
t
T
21
results of a two dimensional model of ballistic diodes, Pop reported range of 1 × 10�� to
4 × 10�� W/m�, 1 × 10�� to 1 × 10�� W/m� , and 1 × 10�� to 3 × 10�� W/m� for heat
generation in FinFET transistor of channel length of 500 nm, 100 nm, and 20 nm, respectively
[1, 21, 71]. Using coupled electro-thermal tools, Kolluri et al. reported heat generation of
1.5 × 10�� to 4 × 10�� W/m� in the channel extension region of FinFET transistor [72]. Table
A-2 and Table A-3 summarize published information about heat generation and boundary
condition in MOSFET and FinFET transistors. A review of this information reveals that for a
transistor at a technology node, 90 nm for example, reported heat generation rates are of the
same order, and in acceptable agreement with each other. In our FinFET simulations we relied
on the data reported by Singh et al. because of the similarity of their study to ours and the fact
that they reported more detailed information of heat generation in each logic gate [31]. Based on
this information, we calculated the heat generation rate in our FinFET models, which was found
to be in agreement with aforementioned values. In each logic gate model, total heat generation is
assumed to be the same for each gate at all technology nodes. Thus, the heat generation rate
changes with size cubed. Assuming that a logic gate of MOSFET transistors have similar power
consumption to that of FinFET transistors [93], the total heat generation of a MOSFET
transistor is considered to be the same as its corresponding FinFET transistor in the similar gate.
Table A-4 reports the heat generation values that were implemented in our models.
2.5 Boundary conditions
Inside a die package, transistors are fabricated in stacked layers and are connected to each other
and via interconnect (see Fig. 2-8) [36, 37]. As shown in Fig. 2-8, the top face of the upmost
interconnects (last level of metallization) in this hierarchy is in contact with the heat removal
accessories (e.g., fins). Interconnects are made of metal, usually copper, that have much higher
thermal conductivity than their surrounding materials (i.e., silicon, silicon dioxide). We expect
this high thermal conductivity, and thus low thermal resistance, to results in: (i) most of heat to
get transferred via these wires towards the top face of the die, (ii) within acceptable error, an
isothermal surface get created at each cross section of the interconnect hierarchy at steady state
condition. Therefore, in our simulation, we assumed the top face of interconnects (at first level
metallization) to be isothermal.
22
To find the magnitude of temperature at the isothermal surfaces, first, we should study the
temperature profile on the top face of the upmost interconnects, i.e., the top face of the die.
Romero et al. presented the temperature floor plan of Pentium VI chip, varying from 308 to 348
K, simulated based on chip power consumption floor plan [74]. Similarly, Akturk et al.
presented the temperature floor plan of Pentium III chip, varying from 300 to 362 K [75] (see
Fig. 2-9). Based on this information, the temperature of the top face of each interconnect can be
as low as 300 K, and as high as 360 K, depending on the location of the interconnect. To cover
all the possible situations, we ran three cases of boundary conditions for each gate model. First,
the case where top face is set to 300 K; second, the case where top face is set to 350 K; and
finally, the case where top face is set to 400 K. It should be noted that all the other boundaries
are assumed to be adiabatic due to existence of silicon dioxide isolators and presence of
neighbor transistors.
Fig. 2-8. A sketch of an example for hierarchical interconnect architecture used in 90 nm node digital
signal processor (based on a photo from Handbook of silicon semiconductor metrology [37]).
Transistor
Metal
interconnects
Top face of the die; This surface is in contact with heat sink (cooling fins, which transfer heat to fan)
23
© 2005 IEEE (with permission)
Fig. 2-9. Temperature map of Pentium III chip. Note that temperature varies from 300 to 362 K [75].
To provide better visualization of this boundary condition, Fig. 2-10 shows MOSFET NAND
logic gate, having the top of its metallization layer (i.e., metal interconnects) set to room
temperature, TS = 300 K (cases of TS = 350 K, and TS = 400 K are not shown here). As reported
in Table A-2 and Table A-3, similar assumptions for boundary conditions have been reported in
literature (e.g., [23, 31, 33, 69, 72, 73, 76, 77]).
Fig. 2-10. Constant boundary condition of 300 K on the top face of top interconnects (colored in red) in
MOSFET NAND logic gate. The same boundary condition is applied on other models.
Isothermal boundary condition
on top face of top interconnects
Adiabatic boundary condition
on all the other walls
24
2.6 Governing equations
The models that we have been built for each basic logic gate are of the same configuration and
have the same boundary condition in all technology nodes. In other words, models at different
technology nodes are in fact scaled versions of a reference case (set to be 90 nm technology
node case in our simulations), and have the same boundary conditions. This means that models
of a specific gate at different technology nodes are analogous, and the same set of equations, Eq.
2-1 subject to the same set of boundary condition, is being solved in their simulations,
!"!# $ %&'�&(' + &
'�&*' + &'�&+', + -. /// = 0�0(, *, +123�4�56 = ��
-. ///789:6;<=34�5��6 = %�=64.5��6�5��6 ,� . -. ///789:6;<=349:6=64.5��6> (2-1)
where T is temperature of a node located at ((, *, +), -. ′′′ is the volumetric heat generation rate,
�� is the top surface temperature, HGR represents the heat generation region (i.e. the channel
extension close to the drain),�5��6 is the lambda length in the case under study, and �=64.5��6 is
lambda in the reference case, which in our simulation is set to 90 nm technology node case.
Using ANSYS as the solver and following modified Fourier-based approach that was proposed
by Nabovati et al.[24], we implemented values of effective thermal conductivity (instead of bulk
thermal conductivity) in Fourier equation and solved it. By doing so, the results would account
for sub-continuum effects that conventional Fourier equation fails to capture. As mentioned in
previous section, the top face on interconnects are set to constant temperature, and all the other
walls are considered to be adiabatic. These two boundary conditions are the only boundary
conditions imposed on all the models.
2.7 Meshing
The idealized structure of both FinFET and MSOFET logic gates mostly consist of cubic shaped
sections with sharp edges and flat plates. Therefore, the mesh was created using hexahedra grid.
The models are created with approximately one million nodes, with higher number of nodes in
25
the areas close to heat generation region, where higher temperature gradients are expected to
occur. A sample of this meshing is shown in Fig. 2-11.
Fig. 2-11. Mesh in a MOSFET logic gate. (a) Top view of mesh in MOSFET logic gate. (b) Side view of
mesh in the same gate. The passivation layer is hidden for better visualization of gate details.
2.8 Grid independence study
2.8.1 MOSFETs
As a representative of MOSFET logic gates, the NAND gate is chosen for grid study. It should
be noted that in our simulations, the same approach is adopted for meshing all logic gates, and
thus grid independency in NAND gate can represent the grid indecency of results in all other
MOSFET gates that have been modeled in this work.
To study the dependency of maximum temperature on the node count and grid size, we
simulated heat transfer in 7 sample cases. Needless to say, all parameters, except the mesh, are
the same in all 7 cases. As shown in Fig. 2-12 (a), we could observe that maximum temperature
of the logic gate is independent of grid size after 1 million nodes. Temperature is a scalar
variable and mostly self-consistent and fast converging in thermal simulations [11], compared to
heat flux, which is related to gradient of temperature. Therefore, it is not enough to study grid
independency for that variable only. In order to confirm the independency of the results on grid
size, we monitored the magnitude of maximum heat flux in z direction on the interface of silicon
substrate and passivation layer for cases with different mesh sizing (see Fig. 2-12(b)). Results
show that maximum heat flux is also independent of grid size for cases with more than 1 million
nodes.
26
(a) (b)
Fig. 2-12. Grid independency in a test case on MOSFET NAND gate. (a) ����. of the logic gate is
plotted vs. the number of nodes. (b) Magnitude of maximum heat flux in z direction on the interface of
silicon substrate and passivation layer (plane 1, as shown in Fig. A-3).
2.8.2 FinFETs
Similar to MOSFETs, NAND gate was chosen for grid study of FinFETs. The same approach
was taken to study the dependency of results on meshing. As shown in Fig. 2-13, maximum
temperature of the logic gate is independent of grid size after 1 million nodes.
(a) (b)
Fig. 2-13. Grid independency in a test case on FinFET NAND gate. (a) ����. of the logic gate is plotted
vs. the number of nodes. (b) Magnitude of maximum heat flux in z direction on the interface of BOX
substrate and passivation layer.
0 2 4 6 8 10
x 105
317.25
317.3
317.35
317.4
Number of nodes
TM
ax [
K]
317.45
0 2 4 6 8 10
x 105
3.5
4
4.5
5
5.5
6x 10
9
Number of nodes
He
at
flu
x [
W/m
2]
0 2 4 6 8 10 12
x 105
328.5
329
329.5
330
330.5
331
Number of nodes
TM
ax [
K]
0 2 4 6 8 10 12
x 105
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
5.8
6x 10
9
Number of nodes
He
at
flu
x [
W/m
2]
27
2.9 Approach towards finding equivalent thermal conductivity of FinFET and MOSFET basic logic gates
Calculating an equivalent thermal conductivity for MOSFET and FinFET basic logic gates, this
work uses the outcome of atomistic level simulations (i.e., effective size-dependent thermal
conductivities) as input data for gate-level thermal modeling. In this approach, first, steady-state
heat transfer in 3D models of each logic gate was simulated using ANSYS and employing
effective thermal conductivity of thin films and nanowires. Then, a simple block of the same
total volume that generates the same total heat was built as an equivalent model for each logic
gate (see Fig. 2-14). Finally, a thermal conductivity, hereby called equivalent thermal
conductivity, was assigned to each block such that the block would experience the same
maximum temperature as that of its corresponding detailed gate model. To find the equivalent
thermal conductivity, we followed the trial and error method, where we assigned values of
thermal conductivity to the block and checked whether or not the block would experience the
desired maximum temperature. Then, if the maximum temperature of the block was higher or
lower than desired maximum temperature, we alter the thermal conductivity to a higher or lower
value respectively. We continued this trial and error path until the assigned thermal conductivity
would make the block experience the desired maximum temperature. Using this approach, we
calculated equivalent thermal conductivity for ten different MOSFET and FinFET basic logic
gates.
(a) (b)
Fig. 2-14. (a) MOSFET NAND gate model; (b) Simple block that will replace the detailed model in
higher level simulations. The thermal conductivity of this block is equal to calculated equivalent thermal
conductivity for MOSFET NAND gate.
28
Chapter 3: Results
3.1 Simulation results
Details of geometry construction, material properties, boundary condition settings, and meshing
were explained in details in Chapter 2. In this chapter, the simulation results are presented and
discussed.
3.1.1 Temperature profile
Figures 3-1 to 3-5 present the temperature profile in AND, OR, NAND, NOR, and NOT
MOSFET logic gates, at 90 nm technology node, respectively. Figures 3-6 to 3-10 show the
temperature profile in AND, OR, NAND, NOR, and NOT FinFET logic gate, at 90 nm
technology node, respectively. In all the results presented in Fig. 3-1 to Fig. 3-10, top surface of
the gates is set to 300 K. Heat pattern and temperature profile in the other two cases, where
�� = 350K, or400K are similar and thus not plotted here. The maximum temperatures of
those cases, however, are plotted in Fig. 3-11.
29
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-1. Temperature profile in MOSFET AND of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut;[Unit: K]
A-A’
B-B’
30
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-2. Temperature profile in MOSFET OR of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut; [Unit: K].
B-B’
A-A’
31
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-3. Temperature profile in MOSFET NAND of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation
and metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut;[Unit: K]
B-B’
A-A’
32
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-4. Temperature profile in MOSFET NOR of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut;[Unit: K]
B-B’
A-A’
33
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-5. Temperature profile in MOSFET NOT of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut;[Unit: K]
B-B’
A-A’
34
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-6. Temperature profile in FinFET AND of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut; [Unit: K]
B-B’
A-A’
35
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-7. Temperature profile in FinFET OR of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut; [Unit: K]
A-A’
B-B’
36
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-8. Temperature profile in FinFET NAND of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut; [Unit: K]
A-A’
B-B’
37
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-9. Temperature profile in FinFET NOR of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut; [Unit: K]
A-A’
B-B’
38
(a)
(b)
(c)
(d)
A-A’
(e)
B-B’
Fig. 3-10. Temperature profile in FinFET NOT of 90 nm technology node; (a) 3D view including all components, (b) 3D view excluding passivation and
metallization layer, (c) Top view excluding passivation and metallization layer, (d) Side view, A-A’ cut, (e) Side view, B-B’ cut; [Unit: K]
A-A’
B-B’
39
Fig. 3-11. Maximum temperature in FinFET and MOSFET basic logic gates at 90 nm, 65 nm, and 45 nm technology nodes, and �� = 300, 350, and400K.
These data points are available in Table A-5.
45 65 90300
350
400
450
500
550
600
650
Technology node [nm]
TM
ax [
K]
45 65 90300
350
400
450
500
550
600
650
Technology node [nm]
TM
ax [
K]
FinFET AND
FinFET OR
FinFET NAND
FinFET NOR
FinFET NOT
MOSFET AND
MOSFET OR
MOSFET NAND
MOSFET NOR
MOSFET NOT
TTop
s urface
= 400 KT
Top s urface
= 400 K
TTop
s urface
= 350 K
TTop
surface
= 300 K
TTop
s urface
= 300 K
TTop
s urface
= 350 K
40
As shown in Fig. 3-1 to Fig. 3-10, heat generation regions have higher temperature than their
neighbouring components. As expected, the temperature of each point in the logic gate is
directly related to its distance from the heat generation region as well as its distance from the
copper interconnects (heat sinks).
The dominant heat removal passage, in both MOSFETs, and FinFETs, begins from the heat
generation region, through the source, or drain, then through the metal paths and end on the top
face of interconnect, where the heat sink is. Although most of the heat is being dissipated
through the metal paths and interconnects, the passivation layer also contributes to transferring
heat from the hot region towards the top heat sinks. Due to low thermal conductivity of silicon
dioxide however, this contribution is fairly small and higher temperature rise in the passivation
layer is observed. Because of high thermal conductivity of copper, much smaller temperature
gradient (compared to other components) is observed at each XY cross section of interconnects.
The role of tungsten paths (metal paths) is to transfer the heat from source, drain, or gate to the
copper interconnects. The importance of these tungsten paths becomes clear by comparing
temperature rise in the two bottom drain regions of FinFET OR (see Fig. 3-7). In the first drain
from bottom, the drain region is not in contact with metal paths, and thus the heat gets trapped in
the drain. In the second drain region, on the other hand, the drain is in contact with metal paths,
which remove heat from the drain region, resulting in lower temperature of drain compared to
that of first drain.
Due to differences in source and drain placement in different logic gates, density of heat
generation is different in each logic gates. In gates like FinFET NOR (see Fig. 3-9), drain is
shared between two adjacent transistors. Considering that heat generation occurs in the channel
extension region close to the drain, in gates like FinFET NOR, the density of heat generation in
that area is much higher than a gate like FinFET OR (its bottom transistors, for example), where
drain is placed close to one source only. In other words, where two adjacent transistors share a
drain, the heat generated by both transistors transfers to this joint drain, resulting in high heat
density, and thus higher temperature rise in this area, compared to transistors with separate
drains. Higher heat density in logic gates results in higher local temperature in this region.
The channel extension (heat generation region) in MOSFETs is fabricated directly in the silicon
substrate. Therefore heat generation region in MOSFET is in direct contact with silicon
41
substrate with relatively high thermal conductivity by the side and bottom walls. In FinFETs
however, the channel extension is fabricated on top of the buried oxide layer (BOX) layer, and
surrounded by silicon dioxide as passivation layer. Low thermal conductivity of BOX layer and
silicon dioxide passivation layer contributes to higher temperature rise in FinFETs compared to
MOSFETs.
FinFETs have two major differences from MOSFETs: i) The planar gate structure of MOSFETs,
where channel and channel extension are fabricated inside the gate and the silicon substrate, is
different than non planar gate structure of FinFETs, where channel and channel extension are
fabricated in a fin [4, 37]. The FinFET gate structure enables manufacturing of smaller, more
confined, and multi fin transistor and logic gates. ii) In FinFETs, the substrate is covered with a
thin layer of Buried oxide, on top of which the source, drain, and fin crystalline silicon are
deposited and doped, while in MOSFETs, the source and drain are directly created in the silicon
substrate by etching silicon and then doping it, or by injecting or depositing dopants into the
selected portions of silicon substrate [4, 37].
These main differences are known to contribute to more severe self heating effects in FinFETs.
Low thermal conductivity of buried oxide (BOX) layer in FinFETs creates higher resistance
against heat dissipation, compared to the bulk silicon substrate in MOSFETs [40, 78, 79].
Results of our simulation support this statement as it shows higher maximum temperature in
FinFET logic gates when compared to their corresponding MOSFET logic gates (see Table 3-1).
However, the results of a test case (at 90 nm technology node), in which the BOX layer was
replaced with bulk silicon, shows that BOX layer is not the only contributing factor in higher
maximum temperatures of FinFETs. Table 3-1 reports temperature rise in two test cases run on
FinFET NOR logic gate, one with existence of BOX layer, and one without it, as well as a test
case on their corresponding MOSFET logic gate.
Table 3-1. Impact of buried oxide layer (BOX) layer on temperature rise.
Case Temperature rise, ∆�
FinFET NOR with the BOX layer 65.67
FinFET NOR with BOX layer replaced by bulk silicon 39.67
MOSFET NOR 27.63
42
Confined configuration of components in FinFETs, and the relatively small fin spacing in multi-
fin FinFETs are also reported to lead to higher temperature rise [23, 76]. As mentioned before,
our simulation results reports higher temperature rise in FinFET logic gates compared to
MOSFET logic gates. Relying on the results of the test cases on FinFET NOR with and without
BOX layer, we believe that the more geometrically confined configuration of FinFETs is also a
contributing factor in higher temperature rises in FinFETs.
As mentioned before, energy carriers (electrons and phonons) interactions occurring in the high
electric field region in the channel extension next to the drain results in self heating (generally
called heat generation in this research) [68, 80]. Higher heat generation rates are calculated in
FinFETs [21, 31, 72] compared to MOSFETs [69, 73]. Comparing the maximum temperature in
the logic gates, in which higher heat generation rate is implemented (FinFET NAND for
example, Fig. 3-8), with the logic gates, in which lower heat generation rate is implemented
(FinFET NOT for example, Fig. 3-10), we believe heat generation rate to be an important
contributing factor to maximum temperature, compared to other contributing factors such as
thermal conductivity of material surrounding the region, and size of the region for the range of
values commonly encountered in MOSFET and FinFET logic gates.
3.1.2 Dependency of maximum temperature, ���� on top face temperature, ��
For each basic logic gate at each technology node, three cases have been considered and
simulated. These three cases are the same in all regards except the temperature of top face
boundary condition, which is set to �� = 300, 350, and400K, respectively. Note that except
the top face, which is set to constant temperature, all the other boundaries are adiabatic.
Therefore, the sets of relations stated in Eq. 2-1, is being solved in each of these simulations.
The partial differential equation we are solving is linear, with constant thermal properties (i.e.,
no thermal dependence), and constant linear boundary conditions. Hence, because of the
principle of superposition, if we increase �� by 50 degrees, ���� will also increase by the same
amount. As expected, results of our simulation display this linear increase as shown in Fig. 3-12.
43
Fig. 3-12. Maximum temperature in MOSFET and FinFET basic logic gates at 90 nm technology nodes,
and �� = 300, 350, and400K.
3.1.3 Variations of maximum temperature at 90 nm, 65 nm, and 45 nm technology nodes
Previous studies have investigated the influence of individual component’s sizing on the
maximum temperature of the device [1, 21, 23, 33, 71, 76]. These works described how the
maximum temperature of the device decreases as length, width or height of each component
increases. Sensitivity analysis of maximum temperature with respect to component scaling in
2D [1, 21], and 3D transistor models [23, 39, 76, 77], as well as 3D gate models [33], shows that
maximum temperature of the device is most sensitive to drain, and channel extension sizing in
MOSFETs [1, 21, 81] and lowering drain region thermal resistance (e.g., by incorporating
materials or dopants to raise its thermal conductivity, or by simply up scaling its cross section)
can help heat dissipation, and thus alleviate device temperature. Similarly in FinFETs, the
maximum temperature is found to be sensitive to gate and fin sizing, especially in the channel
extension part [33].
300 350 400300
320
340
360
380
400
420
440
460
480
Temperature of top surface (sink), TS [K]
TM
ax [
K]
300 350 400300
320
340
360
380
400
420
440
460
480
Temperature of top surface (sink), TS [K]
TM
ax [
K]
FinFET AND
FinFET OR
FinFET NAND
FinFET NOR
FinFET NOT
MOSFET AND
MOSFET OR
MOSFET NAND
MOSFET NOR
MOSFET NOT
44
We believe our assumption to be more realistic based on the fact that when one dimension of a
component is scaled down, the other dimensions also get scaled down according to the desired
electrical performance [82]. Therefore, instead of studying the impact of individual component’s
sizing, we investigate the effect of scaling the whole device in our simulation. This means that
the models at different technology nodes are in fact scaled versions of a reference case, which is
90 nm technology node case.
Our simulation results show that by down scaling the device technology node, from 90 nm to 65
nm, and 45 nm, maximum temperature increases. Similar results have been reported in the
literature before [33]. As shown in Fig. 3-13, this increase is found to be more dramatic in
FinFETs compared to MOSFETs.
The general non-linear trend of temperature rise is expected because, as reported in Table 3-2,
when � decreases, it affects both effective thermal conductivity of the device components and
the volumetric heat generation rate. While the change in heat generation rate is assumed to be a
function of �� in our models (as explained in Chapter 2), effective thermal conductivity of
materials changes with different rates (size-dependence of effective thermal conductivity of
incorporated materials is plotted in Fig. A-14).
Fig. 3-13. Impact of down scaling on the maximum temperature of the modeled gates.
45 65 900
50
100
150
200
250
Technology node [nm]
∆ T
[K
]
45 65 900
50
100
150
200
250
Technology node [nm]
∆ T
[K
]
FinFET AND
FinFET OR
FinFET NAND
FinFET NOR
FinFET NOT
MOSFET AND
MOSFET OR
MOSFET NAND
MOSFET NOR
MOSFET NOT
45
Table 3-2. Impact of key parameters on self-heating behavior.
Primary parameters Secondary parameters (change due
to changes in primary parameters)
Influence on self-heating
behaviour
Technology node size, � ↓ $6446597A6 ↓ -. /// ↑ ���� ↑
Silicon substrate thermal
conductivity, $CDEFG�7 ↓ HI ↑ − ���� ≅ KHLM�. Top surface temperature (heat sink
temperature), �� ↑ − ���� ↑
∆� = ���� −�� = KHLM�.
3.1.4 Impact of volumetric heat generation rate magnitude on maximum temperature
As explained in Chapter 2, there is a discrepancy in the reported values of volumetric heat
generation rates, or equivalently, the power of transistors, in the available literature (e.g., [23,
77]). The values that we used in our simulations are based on the information reported in the
previous work of Singh et al. [31], however, we decided to investigate the effect of heat
generation magnitude on maximum temperature.
MOSFET NAND logic gate and FinFET NAND logic gate are chosen as representatives of
other MOSFET and FinFET basic logic gates, respectively. Implementing volumetric heat
generation rates of various magnitudes in the active heat generating regions, variations of
maximum temperature was observed. Note that in each new case, the magnitude of volumetric
heat generation in each active heat generating regions is chosen to be double its value in the
previous case. In Fig. 3-14, ratio of heat generation rate in each case to heat generation rate in
the reference case (the first case is chosen as the reference case) represents each heating case.
The top face temperature is set to 300 K in all the cases. As shown in Fig. 3-14, when heat
generation rate magnitude increases, maximum temperature of each gate increases in a linear
pattern, as expected. This linear pattern has a different rate (slope of the line) in MOSFET gates
than in FinFET MOSFETs, which is due to differences in the structure, general layout and
configuration, and thus different values of thermal conductivity of components.
46
Fig. 3-14. Impact of volumetric heat generation rate magnitude on maximum temperature in MOSFET
and FinFET NAND gate.
3.1.5 Impact of bulk vs. effective thermal conductivity on maximum temperature
One of the main advantages of the present work over similar studies in this field is that most up
to date values for effective thermal conductivity of thin films and nanowires are implemented in
our models. As explained in Chapter 2, effective thermal conductivity of thin films and
nanowires are generally much lower than the bulk thermal conductivity due to non-continuum
effects [11, 20]. To show the importance of this choice, a FinFET NAND gate at 90 nm
technology node, is chosen as a representative of basic logic gates, and two situations were
simulated: one incorporating effective thermal conductivities of materials, and the other one
using bulk thermal conductivities. It should also be noted that all the other parameters including
choice and magnitude of boundary conditions, components’ size and configuration, and
magnitude and location of heat source are the same for the both cases. Detailed information of
the characteristic sizes of transistor components and the values of bulk and effective thermal
conductivity of materials are reported in Table 3-3 and Table A-1.
1 2 3 4 5 6 7 8300
350
400
450
500
550
q⋅′′′
case/q
⋅′′′
Reference case
TM
ax [
K]
MOSFET
FinFET
47
Fig. 3-15. Temperature profile on FinFET NAND gate (unit: K) when (a) effective thermal conductivity
of thin films and nanowires was implemented in the model, and (b) when bulk thermal conductivity of
materials was implemented. Comparing the two cases reveals the impact of bulk vs. effective thermal
conductivity on the predicted maximum temperature in FinFET NAND gate.
As shown in Fig. 3-15, when bulk thermal conductivities are employed, the gate experiences
only a 8.96 degrees temperature rise, while by employing effective thermal conductivities,
temperature rises 30.59 degrees. Having a good approximation of temperature rise is important
for effective thermal and electrical management of the system. Therefore, knowledge of most
accurate values of thermal conductivity of components, which helps providing a good
approximation of temperature rise in a component, is necessary.
Table 3-3. Bulk and effective thermal conductivity of components (in W/m.K) in FinFET NAND logic
gate at 90 nm technology node [7].
Component (characteristic size) NOPQN NRSSTUVWXT Component (characteristic size) NOPQN NRSSTUVWXT Substrate 148 - BOX layer (50 nm) 1.4 0.66
Source/Drain (75 nm) 148 33 Passivation layer (150 nm) 1.4 1.01
Channel (30 nm) 148 23.4 Channel extension (15 nm) 148 17.5
Gate oxide (15 nm) 1.4 0.45 Gate (15 nm) 105 29.8
Interconnects (90 nm) 401 205 Metal path (30 nm) 173 41.10
48
3.2 Results validation
Most of the published works in this research’s field generally lack reporting detailed
information about device dimensions, and exact magnitude, size, and location of heat generation
source. Therefore, building models that are exactly the same as models in the previously
published work is not possible. However, we can compare the range and order of magnitude of
the predicted temperature rise with published results. Result of our simulations show that the
average temperature rise in our FinFET and MOSFET logic gates are generally in good
agreement with average temperature rise that has been reported for respective gate structure
devices in literature [1, 3, 21-23, 31, 39, 73, 76, 77, 81, 85]. Shrivastava et al. modeled a 3D
FinFET logic gate (which is closest published work to this research in this regard; See Table A-
3 for a summary of the information available about their model) and reported temperature rise of
150 degrees for the device at 20 nm technology node [33]. As shown in Fig. 3-13, FinFET NOT
gate at 45 nm node, which has the most similar configuration to Shrivastava et al. model, is
experiencing temperature rise of 87.2 degrees. The pattern of temperature rise versus technology
on our models predict this number to get close to 160 degrees at 20 nm technology node, which
would be of the same order of magnitude as the temperature rise reported by Shrivastava et al.
results.
3.3 Heat transfer pattern
Several studies have investigated possible heat flow paths in FinFETs [33, 86-91]. It is obvious
that location of heat sink determines the main direction of heat flow. Based on author’s
understanding of die packaging, placing heat sink on top face is most realistic assumption. In
studies that made the same assumption, interconnects are reported to be the prime heat flow path
[33, 82, 88, 89, 91]. Kumar et al. research supports the statement that significant part of the heat
flows through gate contacts and, hence, through interconnects [89]. Kumar et al. conducted a
comprehensive study on impact of metal vs. polygate on self heating in FinFETs and found
metal gates to provide better performance [89]. As shown in Fig. 3-16, heat flux contours in
FinFET NAND gate (as a representative of our models) show the main heat flow path to be
through interconnects. This conclusion is in agreement with conclusion of similar works [33,
86-91].
49
Fig. 3-16. Contours of magnitude of heat flux in y direction in A-A' cut of FinFET NAND gate (for top
view, see Fig. 3-8) as a representative of our models. Arrows illustrate the direction of heat flow.
3.4 Equivalent thermal conductivity
Using the approach that was described in Section 2.9 of Chapter 2, we found the equivalent
thermal conductivity of MOSFET and MOSFET AND, OR, NAND, NOR, and NOT logic
gates. Table 3-4 reports the values of equivalent thermal conductivities found for FinFET and
MOSFET basic logic gates at 90 nm, 65 nm, and 45 nm technology nodes.
Table 3-4. Calculated values for equivalent thermal conductivity (in W/m.K) of MOSFET and FinFET
basic logic gates.
Technology Node AND OR NAND NOR NOT
FinFET 90 nm 3.11 2.30 4.21 2.35 2.30
65 nm 3.50 2.59 4.98 2.79 2.68
45 nm 3.80 2.87 5.41 3.02 2.95
MOSFET* 90 nm 7.80 8.00 8.18 7.58 5.95
65 nm 7.89 8.05 8.27 7.71 5.98
45 nm 8.02 8.09 8.43 7.88 6.03
* Within 5 % error, equivalent thermal conductivity of a MOSFET gate is the same at all technology
nodes.
Locations of heat
generation regions
Unit: W/m2
Isothermal
boundary
condition on top
face of
interconnects
50
Fig. 3-17. Calculated equivalent thermal conductivity for FinFET and MOSFET basic logic gates
As illustrated in Fig. 3-17, equivalent thermal conductivity of FinFET logic gates show larger
variations vs. transistor size (represented by technology node here), compared to MOSFETs.
This is because thermal conductivity of heat generation region in FinFETs has higher variations
when transistor size changes (see Fig. 3-18) at different technology nodes.
Due to the arrangement of transistor components, and the different materials that have been used
in their fabrication, the contribution of each component to temperature rise inside the device is
different. Therefore, volumetric average thermal conductivity values will not represent such
contributions. Running a sample case on FinFET NAND, where volumetric average thermal
conductivity (equal to 79.93 W/m.K) was implemented in the equivalent block, resulted in
temperature rise of 1.6 degrees, which was not comparable with the temperature rise of
corresponding detailed logic gate (equal to 30.59 degrees).
45 65 902
3
4
5
6
7
8
9
10
Technology node [nm]
k E
qu
iva
len
t [W
/m.K
]
45 65 902
3
4
5
6
7
8
9
10
Technology node [nm]
k E
qu
iva
len
t [W
/m.K
]
FinFET AND
FinFET OR
FinFET NAND
FinFET NOR
FinFET NOT
MOSFET AND
MOSFET OR
MOSFET NAND
MOSFET NOR
MOSFET NOT
51
Table 3-5. Effective thermal conductivity of heat generation region in FinFET and MOSFET NAND gate
Technology node → 90 nm 65 nm 45 nm
size
[nm]
$Z446597A6
[W/m.K]
size
[nm]
$Z446597A6
[W/m.K]
size
[nm]
$Z446597A6
[W/m.K]
MOSFET 90 22.1 65 20.3 45 19
FinFET 30 17.5 22 15.0 15 10
Fig. 3-18. Variations of thermal conductivity of heat generation region when the size of heat generation
region (made of crystalline silicon, and main heat transport path is through in-plane direction) changes at
different technology nodes. The characteristic sizes of heat generation region in FinFETs are 15, 22, and
30 nm at 45, 65, and 90 nm technology nodes, respectively; while in MOSFET, they are 45, 65, and 90
nm for 45, 65, and 90 nm technology nodes, respectively. The thermal conductivity value is retrieved
from [9].
3.5 Dependency of equivalent thermal conductivity on boundary conditions
The approach that we adopted in our research, i.e., calculating an equivalent thermal
conductivity for each logic gate that will replace the detailed model in higher level simulation,
requires proof of results independency from the parameters (as many as possible) that are
subject to change in simulations. This proof, not only shows the accuracy of the results, but also
provides powerful evidence on the wide domain that the results could be implemented [92]. In
our work, we showed how equivalent thermal conductivity is independent of boundary
conditions. We selected NAND gate as a representative of basic logic gates because it has the
complexities that all logic gates have in common.
20 40 60 80 1000
5
10
15
20
25
30
Size [nm]
k Fil
m [
W/m
.K] in FinFETs
in MOSFETs
45 nm technology node
65 nm technology node
90 nm technology node
90 nm technology node
65 nm technology node
45 nm technology node
52
3.5.1 Equivalent thermal conductivity as a function of volumetric heat generation rate
FinFET and MOSFET NAND gates are chosen as a representative of other FinFET and
MOSFET basic logic gates. Four test case simulations are done on each of these two gates,
where volumetric heat generation -. ′′′ is set to change in the same order as explained in Section
3.1.4. As shown in Fig. 3-19, calculated equivalent thermal conductivities are independent (less
than 0.5 % error, which is due to numerical errors) from the magnitude of heat generation rate.
Fig. 3-19. Equivalent thermal conductivity of MOSFET NAND, and FinFET NAND as a function of
heat generation rate.
3.5.2 Equivalent thermal conductivity as a function of sink temperature
FinFET and MOSFET NAND gates are chosen as a representative of other FinFET and
MOSFET basic logic gates. Three test case simulations are done on each of these two gates,
where top face temperature, �� is set to 300 K, 350 K, and 400 K. As shown in Fig. 3-20,
calculated equivalent thermal conductivities are independent (less than 0.5 % error which is due
to numerical errors) from the magnitude of top surface temperature, ��.
1 2 3 4 5 6 7 80
1
2
3
4
5
6
7
8
9
10
q⋅′′′
case/q
⋅′′′
Reference case
KE
qu
iva
len
t [W
/m.K
]
MOSFET
FinFET
53
Fig. 3-20. Equivalent thermal conductivity of MOSFET NAND, and FinFET NAND when �� = 300 , when�� = 350 , and when�� = 400
In conclusion, calculated equivalent thermal conductivities are independent of the magnitude of
all the boundary conditions that are being set in our simulations. Therefore, these values are
reliable substitute for FinFET and MOSFET basic logic gates at higher level simulations.
3.5.3 Effect of heat generation distribution on equivalent thermal conductivity
As explained in Chapter 2, we assumed that the total heat generation of a MOSFET transistor is
the same as its corresponding FinFET transistor in the similar gate. For example, total heat
generation in the PMOS transistor of MOSFET NOT is assumed to be equal to the total heat
generation of all the fins (2 fins in this case) of PMOS transistor of FinFET NOT, which is the
corresponding transistor in this example. Therefore, the total heat generation of a MOSFET
logic gate is equal to total heat generation of its corresponding FinFET logic gate. This strategy
was followed for modeling heat generation in all of our logic gates. This assumption enables us
to make a reasonable comparison between a FinFET and its corresponding MOSFET logic gate.
Since all the transistors in a MOSFET logic gate have the same configuration, another
reasonable assumption for modeling heat generation is to keep the total heat generation of a
300 350 4000
1
2
3
4
5
6
7
8
9
10
TTop
face
(sink)
[K]
KE
qu
iva
len
t [W
/m.K
] MOSFET
FinFET
54
FinFET logic gate equal to its corresponding MOSFET logic gate, but, this time, distribute the
heat evenly between all the transistors of a MOSFET gate.
A test case on MOSFET NAND was simulated to investigate the results of this assumption. As
reported in Table 3-6, MOSFET NAND with evenly distributed total heat generation
experiences lower temperature rise, compared to MOSFET NAND with total heat generation in
each transistor set to be equal to total heat generation of its corresponding transistor in FinFET
NAND. As a result, equivalent thermal conductivity is different (10 % difference). This
difference in temperature rise, temperature profile, and equivalent thermal conductivity is more
severe where the difference between total heat generations of different transistors in a logic gate
is larger.
Table 3-6. Impact of heat generation distribution on maximum temperature and equivalent thermal
conductivity.
Case Temperature rise, ∆� $Z[D7A�E689 of logic gate
MOSFET NAND with evenly distributed total heat
generation 15.76 9.04
MOSFET NAND with total heat generation in each
transistor set to be equal to total heat generation of
its corresponding transistor in FinFET NAND
17.43 8.18
55
Chapter 4: Conclusion
4.1 Conclusion
Developing 3D models of MOSFET and FinFET basic logic gates, i.e., AND, OR, NAND,
NOR, and NOT, this research conducted a comprehensive study of self-heating in these self
consistent models. Building these 3D models of basic logic gate was quite challenging because
many of the resources wish to preserve their intellectual properties and do not reveal details of
their designs. Relying on the information and design rules that we could collect from various
publications and resources, we built the basic logic gate models, and reported the details of these
structures in this thesis. These details of basic logic gate models, and the scope of present study
are, to the best of author’s knowledge, one of the few published researches in this field.
Results of our simulations show that self-heating in both types of logic gates results in a
significant temperature rise in the device, which would adversely affect its electrical
performance. Existence of buried oxide layer in between the silicon substrate and the transistor,
56
and confined geometry of FinFET structure cause higher average temperature rise in FinFETs
compared to that of MOSFETs, i.e., self-heating effects in FinFETs are more dramatic,
compared to MOSFETs. Temperature profile in both MOSFETs and FinFETs shows that
maximum temperature occurs in the channel extension regions close to the drain. These regions
are the locations where the main charge transport, and thus the heat generation occurs.
Due to differences in terminals' placement in different logic gates, concentration of heat
generation regions is different in each logic gate, though the total heat generation is the same. In
other words, in some logic gate configurations, heat generation regions of adjacent transistors
are placed closer to each other. The closer these heat generation regions are placed, the higher
heat density is observed, which results in higher local temperature of the region.
As technology improves, technology node size decreases and transistor dimensions shrink. This
scale down causes an increase in the heat generation rate, and a decrease in the effective thermal
conductivity of the components. As a result, as the transistor size decreases, a consistent
increase in the temperature rise is observed in both MOSFET and FinFET logic gates. This
means that self-heating effects become more dramatic as transistor dimensions decreases, and
effective heat removal from these transistors become more important for device reliable
functionality.
To account for sub continuum effects that occur in transistor components, instead of the bulk
thermal conductivity, we incorporated effective size-dependent thermal conductivity of thin
films and nanowires of materials in our models. Results of a sample case show that when bulk
thermal conductivities are employed, the predicted temperature rise is 21.63 degrees lower
(more than 70 % difference) than that of the case with effective thermal conductivities.
Therefore, implementing effective thermal conductivity of thin films and nanowires of materials
instead of their bulk thermal conductivity is important for finding an accurate prediction of
temperature rise. This accurate prediction of temperature is crucial for circuit designers, because
it helps them to have an accurate estimation of temperature-dependent electrical conductivity of
transistors and interconnects.
Heat flux pattern in our MOSFET and FinFET logic gate models suggests that the dominant
heat removal passage from the heat generating region is through interconnects and towards
metallization layer. Tungsten paths play an important role in transferring heat from the source,
57
or drain to the copper interconnects (heat sink), higher temperature rise in observed in drain or
source regions without tungsten paths compared to drain and source regions that are in direct
contact with metal paths.
Calculating an equivalent thermal conductivity for each of these gates, we simplified the
outcome of this research for higher level simulation (see Table 4-1). FinFETs’ equivalent
thermal conductivities are in the range of 2.30 to 5.41 W/m.K, and MOSFET’s equivalent
thermal conductivities are in the range of 5.95 to 8.43 W/m.K. The difference between the
effective thermal conductivity of materials (in each component of a logic gate), and the
equivalent thermal conductivity of the logic gate is due to the difference in heat generation
distribution. In an actual model of a logic gate, the heat generation is concentrated in a confined
region, while in a black box model, heat generation is uniformly distributed in a much larger
volume. Forcing a similar ���� in these two cases yields a much lower equivalent thermal
conductivity for the logic gate.
Table 4-1. Calculated values for equivalent thermal conductivity (in W/m.K) of MOSFET and FinFET
basic logic gates.
Technology Node AND OR NAND NOR NOT
FinFET 90 nm 3.11 2.30 4.21 2.35 2.30
65 nm 3.50 2.59 4.98 2.79 2.68
45 nm 3.80 2.87 5.41 3.02 2.95
MOSFET* 90 nm 7.80 8.00 8.18 7.58 5.95
65 nm 7.89 8.05 8.27 7.71 5.98
45 nm 8.02 8.09 8.43 7.88 6.03
Within 5 % error, equivalent thermal conductivity of a MOSFET gate is the same at all technology
nodes.
Calculated equivalent thermal conductivities are found to be independent of the magnitude of
assumed boundary condition, and heat generation rate. Based on our results evaluations, we
propose to use our approach for finding equivalent thermal conductivity of any logic gate with
any configuration and technology, implementing their corresponding heat generation, and
material properties.
4.2 Future work
The main outcomes of present research,
conductivity of MOSFET and FinFET basic logic gates, are potential replacements for each
logic gate in higher level simulations. In other words, at die, or package level simulations, where
millions of transistors and thousands of logic gates
logic gate can be replaced with a simple cube of
heat, or a node generating the
thermal conductivity. To simplify the simulations even further, the die can be
functional blocks and an equivalent thermal conductivity can be estimated for each functional
block.
Fig. 4-1. A schematic of Pentium III Die Map; functional blocks are marke
A die consists of less than a hundred functional block chips (see
of many logic gates. A detailed circuit map of each chip provides the information about how
many of each basic logic gate is used t
equivalent thermal conductivity for each chip using Eq.
58
of present research, i.e., calculated values for equi
conductivity of MOSFET and FinFET basic logic gates, are potential replacements for each
logic gate in higher level simulations. In other words, at die, or package level simulations, where
millions of transistors and thousands of logic gates are being studied in one model, each basic
logic gate can be replaced with a simple cube of the same total volume generating
the same total heat, with its thermal conductivity set to equivalent
To simplify the simulations even further, the die can be
functional blocks and an equivalent thermal conductivity can be estimated for each functional
Pentium III Die Map; functional blocks are marked by
A die consists of less than a hundred functional block chips (see Fig. 4-1), each of which consists
of many logic gates. A detailed circuit map of each chip provides the information about how
many of each basic logic gate is used to build the chip. We believe it is feasible to calculate an
equivalent thermal conductivity for each chip using Eq. 4-1.
d values for equivalent thermal
conductivity of MOSFET and FinFET basic logic gates, are potential replacements for each
logic gate in higher level simulations. In other words, at die, or package level simulations, where
are being studied in one model, each basic
total volume generating the same total
same total heat, with its thermal conductivity set to equivalent
To simplify the simulations even further, the die can be divided into its
functional blocks and an equivalent thermal conductivity can be estimated for each functional
d by black lines [94].
), each of which consists
of many logic gates. A detailed circuit map of each chip provides the information about how
o build the chip. We believe it is feasible to calculate an
59
$6[D7A�E6894D859738�E\E35F = 1∑ 7̂7 _$6[D7A�E689` × 7̂7
(4-1)
where i = AND, OR, NAND, NOR, and NOT, and 7̂ is the number of logic gates of typea in
the functional block.
As mentioned before, this works studies the steady state heat transfer in logic gates. Although
this assumption is acceptable for the purpose of this research, it is not accurate if the thermal
stress and thermal fatigue of transistor or gate system is being studied. Rapid variations in heat
generation rate and thus temperature apply high thermal stresses on the material and may result
in component’s fatigue and thus system failure. Effective heat removal from these regions is
vital for device reliable functioning. To develop an effective thermal management method, an
accurate 3D model of logic gates should be built and transient heat generation should be
implemented, so that temperature fluctuations can be observed and investigated. To the best of
author's knowledge, only a few works have been published on 3D electro-thermal modeling of
detailed gate system [33], though promising studies have been performed on such models at
transistor level [23]. More research has been performed on similar problem using 2D models
[85].
60
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Appendices
70
Appendix I - MOSFET and FinFET basic logic gate models
(a) (b) (c) (d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A' (h) B-B'
Fig. A-1. MOSFET AND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
B-B'
A-A'
Plane 1
Plane 2
Plane 3
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Silicon dioxide
(Gate oxide)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
71
(a) (b) (c)
(d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A' (h) B-B'
Fig. A-2. MOSFET OR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
A-A'
B-B'
Plane 1
Plane 2 Plane 3
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Silicon dioxide
(Gate oxide)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
(a)
(e) Plane 2 (f) Plane 3
Fig. A-3. MOSFET NAND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal in
provide better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A
A-A'
Plane 3
Plane 2
Plane 1
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Silicon dioxide
(Gate oxide)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
72
(b) (c)
(f) Plane 3 (g) A-A'
. MOSFET NAND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal in
provide better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B
B-B'
(d) Plane 1
(h) B-B'
. MOSFET NAND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to
A’ cut; (h) Side view, B-B’ cut.
73
(a) (b) (c) (d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A'
(h) B-B'
Fig. A-4 MOSFET NOR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
Plane 1
Plane 2 Plane 3
B-B'
A-A'
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Silicon dioxide
(Gate oxide)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
74
(a) (b) (c) (d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A' (h) B-B'
Fig. A-5. MOSFET NOT gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
Plane 1
Plane 2 Plane 3
A-A'
B-B' Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Silicon dioxide
(Gate oxide)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
75
(a) (b)
(c)
(d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A'
(h) B-B'
Fig. A-6. FinFET OR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Buried oxide
(BOX layer)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
Plane 1
B-B'
A-A'
Plane 2 Plane 3
76
(a) (b)
(c)
(d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A'
(h) B-B'
Fig. A-7. FinFET AND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
Plane 1
A-A'
B-B'
Plane 2
Plane 3
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Buried oxide
(BOX layer)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
77
(a) (b) (c) (d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A' (h) B-B'
Fig. A-8. FinFET NAND gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
A-A'
B-B'
Plane 1
Plane 2
Plane 3
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Buried oxide
(BOX layer)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
78
(a) (b) (c) (d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A' (h) B-B'
Fig. A-9. FinFET NOR gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden for better
visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
B-B'
A-A'
Plane 1
Plane 2
Plane 3
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Buried oxide
(BOX layer)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
79
(a) (b) (c) (d) Plane 1
(e) Plane 2 (f) Plane 3 (g) A-A' (h) B-B'
Fig. A-10. FinFET NOT gate model. (a) Color code; (b) 3D view; (c) 3D view, passivation layer and some of metal interconnects are hidden to provide
better visualization; (d) Top view, Plane 1; (e) Top view, Plane 2; (f) Top view, Plane 3; (g) Side view, A-A’ cut; (h) Side view, B-B’ cut.
B-B'
A-A'
Plane 1
Plane 2
Plane 3
Bulk silicon
(Substrate)
Crystalline silicon
(Source, drain, channel,
and channel extension)
Polysilicon
(Gate)
Buried oxide
(BOX layer)
Silicon dioxide
(Passivation layer)
Tungsten
(Metal path)
Copper
(Interconnects)
80
Appendix II - Wireframe layout of MOSFET and FinFET logic gate models
(a)
(b)
(c)
(d)
(e)
Fig. A-11. Top wireframe view of MOSFET gate models. (a) AND; (b) OR; (c) NAND; (d) NOR; (e) NOT.
81
(a)
(b)
(c)
(d)
(e)
Fig. A-12. Top wireframe view of FinFET gate models. (a) AND; (b) OR; (c) NAND; (d) NOR; (e) NOT.
82
Appendix III - Effective thermal conductivity of thin films and nanowires
Table A-1. Effective thermal conductivity of thin films and nanowires [10, 11, 55, 59, 61, 68, 84, 95-101].
Material Length of interest
(parametric) [nm] Usage
Effective thermal conductivity of thin film or nanowires at technology node
[W/m.K]
Bulk thermal
conductivity at
300 K
[W/m.K] 45nm 65nm 90nm
Copper 3λ Metallization layer in both
MOSFET and FinFET 8.10 129 205 401
Tungsten λ Wires from transistors to
metallization layer 38.97 39.96 41.10 173
PECVD
silicon dioxide
λ
2
Gate oxide in both
MOSFET and FinFET 0.27 0.36 0.45
1.4
5λ Passivation layer in both
MOSFET and FinFET 1.01 Same for all technology nodes
Crystalline
silicon
λ
2
Channel extension in
FinFETs, IP 10.0 15.1 17.5
148 λ Channel in FinFET 16.5 18.7 20.4
3λ Source/ Drain in
MOSFET, IP 19.0 20.3 22.1
83
Polysilicon
λ
2
Gate, the part on top of
channel in FinFET and
MOSFET
27.9 28.8 29.8
105
λ Gate, the part in between
two fins in FinFET 29.8 31.6 33.6
1.5λ Gate, the front part in
FinFET 31.7 34.4 37.4
3.5λ
Gate, the part between
PMOS and NMOS in
FinFET
39.3 45.5 52.6
BOX 1.67λ Isolating layer (aka BOX
layer) in FinFET 0.66 Same for all technology nodes 1.4
Bulk Silicon Bulk Substrate in both
MOSFETs and FinFETs 148 Same for all technology nodes 148
84
Fig. A-13. Temperature dependence of effective thermal conductivity of selected thin films and nanowires.
These materials are commonly used in logic gate and transistor fabrication [11, 84, 98-102].
300 320 340 360 380 400 420 440 460 480 500
1
10
100
300
Temperature [K]
Th
erm
al
con
du
ctiv
ity
of
film
[W
/m.K
]
L = 90 nm [7]
L = 65 nm [7]
L = 45 nm [7]
L = 100 nm [98]
L = 50 nm [99]
L = 30 nm [98]
L = 100 nm [7]
L = 50 nm [7]
L = 30 nm [7]
L = 20 nm [7]
L = 1 µm [101]
L = 1 µm [101]
Undoped [7]
Doped [7]
L > 570 nm [102]
L = 180 nm [102]
L = 92 nm [102]
L = 32 nm [102]
L > 570 nm [7]
Doped polysi l icon fi lm of 1000 nm thickness
Undoped polysil icon film of 1000 nm thickness
Copper fi lm of 65 nm thickness
C-Silicon film of 100 nm thickness
Copper fi lm of 90 nm thickness
C-Silicon film of 50 nm thickness
C-Silicon film of 30 nm thickness
C-Silicon film of 20 nm thickness
Copper fi lm of 45 nm thickness
PECVD sil icon dioxide film of 570+ nm thickness
PECVD sil icon dioxide film of 180 nm thickness
PECVD si l icon dioxide fi lm of 92 nm thickness
PECVD sil icon dioxide film of 32 nm thickness
85
Fig. A-14. Size dependence of effective thermal conductivity of selected thin films and nanowires.
These materials are commonly used in logic gate and transistor fabrication [9-11, 55, 61, 66, 72, 77, 95, 103, 104].
5 10 100 10000.1
1
10
100
500
Film thickness [m]
Th
erm
al
con
du
ctiv
ity
of
film
[W
/m.K
]
X 10-9
Tungsten nanowire
PECVD silicon dioxide
Copper
BOX
In-plane crystalline silicon (McGaughy, 2011)
Cross-plane crystalline silicon (McGaughy, 2011)
86
Fig. A-15. Temperature dependence of bulk thermal conductivity of commonly used materials in logic gate and transistor fabrication [84, 105].
100
101
102
103
10-2
10-1
100
101
102
103
104
105
Copper ↓
↓ Crystal line sil icon
↑ Tungsten
↓ C-Silicon dioxide
C-Silicon dioxide ↑
perpendicular to crystal axis
A-Silicon dioxide ↑
Temperature [K]
Th
erm
al
con
du
ctiv
ity
[W
/m.K
]
parallel to crystal axis
87
Appendix IV - Summary of boundary condition and heat generation details available in literature
MO
SF
ET
Volu
metric h
eat
gen
eratio
n
[W/m
3]
Meth
od
/Solv
er
Tech
nolo
gy
nod
e or y
ear
Size of heat generation domain
Net total generated
heat in the
transistor/gate
Tm
ax
Tsin
k
Bou
nd
ary
con
ditio
ns
Tab
le A
-2.
Sum
mary
of
publish
ed
info
rmatio
n
about
heat
gen
eration
and
boundary
conditio
n in
MO
SF
ET
transisto
rs.
2D 3D 2D 3D
Details [m2] Details [m
3] [W/m] [W] [K] [K]
Sin
ha an
d G
oodso
n [7
0]
5.00×1018
Ph B
TE
90 n
m (2
005)
20 n
m circle
1.26×10−15
N/A
N/A
6.28×103
5.65×10−4
343
300
Adiab
atic to
p
wall
excep
t th
e m
etallic
parts
(insu
lating gate
oxid
e); A
diab
atic
side
boundaries
(thick
iso
lation
oxid
es
and
neig
hbourin
g
dev
ices); C
onvectiv
e
heat tran
sfer from
top m
etallic parts(ℎ
=
5×108W
/m�K
); C
onvectiv
e heat
transfer
from
botto
m
wall
(ℎ=2×
10�W
/m2K
)
Naru
man
chi et a
l. [73]
6.00×1017
FD
LB
M
Assu
med
to b
e 90 n
m
becau
se of its 1
0 n
m th
at
is similar to
our m
odel.
10 n
m x
100 n
m
1.00×10−15
N/A
N/A
6.00×102
5.40×10−5
393.1
300
Adiab
atic to
p
wall;
Constan
t tem
peratu
re of
300
K
on
all th
e oth
er
walls
88
Esco
bar [6
9]
1.00×1017−
1.00×1020
D L
BM
Assu
med
to b
e 90 n
m b
ecause o
f
its 10 n
m th
at is similar to
our
model.
20 n
m circle
1.26×10−15−
1.26×10−15
N/A
N/A
1.26×102−
1.26×105
1.13×10−5−
1.13×10−2
300.6
- 919.4
300
Adiab
atic to
p an
d botto
m w
alls.
Constan
t temperatu
re of 3
00 K
on
side w
alls.
S
inha e
t al. [7
0]
1.00×1018
MO
NE
T
Assu
med
to b
e 90 n
m b
ecause
of its 1
0 n
m th
at is similar to
our m
odel.
20 n
m circle
1.26×10−15
N/A
N/A
1.26×103
1.13×10−4
N/A
N/A
N/A
N
arum
anch
i et al. [1
06]
1.20×1018
G L
BM
Assu
med
to b
e 90 n
m
becau
se of its 2
0 n
m
circle that is sim
ilar to
Sin
ha's m
odel
20 n
m circle
1.26×10−15
N/A
N/A
1.51×103
1.36×10−4
N/A
N/A
N/A
89
Fin
FE
T
Volu
metric h
eat
gen
eratio
n
[W/m
3]
Meth
od
/Solv
er
Tech
nolo
gy
nod
e or y
ear
Size of heat generation domain
Net total
generated heat in
the transistor/gate
Tm
ax
Tsin
k
Bou
nd
ary
con
ditio
ns
Tab
le A-3
. Sum
mary
of p
ublish
ed in
form
ation ab
out h
eat gen
eration an
d b
oundary
conditio
n in
Fin
FE
T tran
sistors.
2D 3D 2D 3D
Details [m2] Details [m
3] [W/m] [W] [K] [K]
Sin
ha an
d G
oodso
n [6
7]
6.50×1019
Ph B
TE
18 n
m (2
011)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sin
gh et a
l. [31]
N/A
TA
UR
US
N/A
N/A
N/A
N/A
N/A
N/A
9.496×10−7<
�<2.0326×10−4
339
300
Botto
m face is th
e sink (p
ossib
ly co
nstan
t
temperatu
re). All o
ther w
alls are exposed
to
convectiv
e heat tran
sfer
90
Kollu
ri et a
l. [72]
Gau
ssian-p
rofile fu
nctio
n,
are under th
e functio
n=
1.91×1011�/��
Electro
therm
al simulatio
ns
(usin
g D
ES
SIS
®)
Lg=
50nm
125nm
x 1
00 n
m
1.25×10−14
125nm
x20nm
x100nm
2.5×10−22
1.91×104
3.82×10−4
380
300
A
constan
t tem
peratu
re
boundary
co
nditio
n
is
assum
ed
at th
e botto
m
of
BO
X lay
er. All o
ther w
alls
are adiab
atic.
Calcu
lations b
ased o
n tran
sistor co
unt
& T
herm
al Desig
n P
ow
er (TD
P) o
f
die
N/A
die th
ermal p
ow
er div
ided
to n
um
ber
of tran
sistors
2003-2
010
N/A
N/A
N/A
N/A
N/A
1.08×10−7<
�<5.65×10−7
N/A
N/A
N/A
P
op [1
, 21]
Area u
nder th
e functio
n=
2.81×
1010�/��
MO
NE
T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
91
Sw
ahn e
t al. [2
3]
N/A
Modified
Fourier ap
pro
ach, (so
lver:
AN
SY
S)
Lg =
50 n
m
50 n
m x
65 n
m
3.25×10−15
50 n
m x
10 n
m x
65 n
m
3.25×10−23
N/A
N/A
356.5
1
273
Constan
t temperatu
re on to
p face o
f source,
drain
, an
d
gate
pad
. A
ll oth
er w
alls are
adiab
atic.
Shriv
astava e
t al.[3
3]
N/A
Modified
Fourier ap
pro
ach, (S
olv
er: TC
AD
[107])
Stead
y-state
Lg =
22 n
m
N/A
N/A
22 n
m x
8 n
m x
30 n
m
5.28×10−24
N/A
22 n
m x
8 n
m x
30 n
m
500
300 K
(on th
e top face o
f upperm
ost in
terconnect);
450-4
70 K
on th
e top face o
f first level in
terconnects
All o
uter w
alls are isoth
ermal, T
= 3
00 K
92
Appendix V - Internal heat generation implemented in models
Table A-4. The value of volumetric heat generation rate implemented in basic logic gates and magnitude of total heat generated in each transistor. These
values are chosen based on information retrieved from these references [31, 73].
Name
of logic
gate
Name of
HGEN
region
FinFET basic logic gates MOSFET basic logic gates
Number
of fins
90 nm
[W/m3]
65 nm
[W/m3]
45 nm
[W/m3]
Total in
transistor
(all fins)
[W]
90 nm
[W/m3]
65 nm
[W/m3]
45 nm
[W/m3]
Total
[W]
AND
PMOS 1 2 9.2379E+17 2.4522E+18 7.3903E+18 6.2356E-05 1 1.2000E+18 3.1855E+18 9.6002E+18 6.2356E-05
PMOS 2 2 6.2684E+17 1.6640E+18 5.0148E+18 4.2312E-05 1 8.1428E+17 2.1615E+18 6.5142E+18 4.2312E-05
NMOS 1 2 2.4961E+17 6.6259E+17 1.9968E+18 1.6848E-05 1 3.2424E+17 8.6071E+17 2.5939E+18 1.6848E-05
NMOS 2 2 2.4961E+17 6.6259E+17 1.9968E+18 1.6848E-05 1 3.2424E+17 8.6071E+17 2.5939E+18 1.6848E-05
PMOS 3 2 2.8136E+16 7.4689E+16 2.2509E+17 1.8992E-06 1 3.6549E+16 9.7022E+16 2.9240E+17 1.8992E-06
NMOS3 1 1.0250E+17 2.7210E+17 8.2003E+17 3.4595E-06 1 6.6577E+16 1.7673E+17 5.3261E+17 3.4595E-06
Total heat [W] 1.4372E-04 1.4372E-04
OR
PMOS 1 4 1.3155E+17 3.4921E+17 1.0524E+18 1.7760E-05 1 3.4178E+17 9.0726E+17 2.7342E+18 1.7760E-05
PMOS 2 4 1.5440E+17 4.0986E+17 1.2352E+18 2.0844E-05 1 4.0114E+17 1.0648E+18 3.2091E+18 2.0844E-05
NMOS 1 1 2.4395E+18 6.4756E+18 1.9516E+19 8.2332E-05 1 1.5845E+18 4.2060E+18 1.2676E+19 8.2332E-05
NMOS2 1 2.4395E+18 6.4756E+18 1.9516E+19 8.2332E-05 1 1.5845E+18 4.2060E+18 1.2676E+19 8.2332E-05
PMOS 3 2 2.8136E+16 7.4689E+16 2.2509E+17 1.8992E-06 1 3.6549E+16 9.7022E+16 2.9240E+17 1.8992E-06
NMOS3 1 1.0250E+17 2.7210E+17 8.2003E+17 3.4595E-06 1 6.6577E+16 1.7673E+17 5.3261E+17 3.4595E-06
Total heat [W] 2.0863E-04 2.0863E-04
NAND
PMOS 1 2 9.2379E+17 2.4522E+18 7.3903E+18 6.2356E-05 1 1.2000E+18 3.1855E+18 9.6002E+18 6.2356E-05
PMOS 2 2 6.2684E+17 1.6640E+18 5.0148E+18 4.2312E-05 1 8.1428E+17 2.1615E+18 6.5142E+18 4.2312E-05
NMOS 1 2 2.4961E+17 6.6259E+17 1.9968E+18 1.6848E-05 1 3.2424E+17 8.6071E+17 2.5939E+18 1.6848E-05
NMOS 2 2 2.4961E+17 6.6259E+17 1.9968E+18 1.6848E-05 1 3.2424E+17 8.6071E+17 2.5939E+18 1.6848E-05
Total heat [W] 1.3836E-04 1.3836E-04
93
NOR
PMOS 1 4 1.3155E+17 3.4921E+17 1.0524E+18 1.7760E-05 1 3.4178E+17 9.0726E+17 2.7342E+18 1.7760E-05
PMOS 2 4 1.5440E+17 4.0986E+17 1.2352E+18 2.0844E-05 1 4.0114E+17 1.0648E+18 3.2091E+18 2.0844E-05
NMOS 1 1 2.4395E+18 6.4756E+18 1.9516E+19 8.2332E-05 1 1.5845E+18 4.2060E+18 1.2676E+19 8.2332E-05
NMOS 2 1 2.4395E+18 6.4756E+18 1.9516E+19 8.2332E-05 1 1.5845E+18 4.2060E+18 1.2676E+19 8.2332E-05
Total heat [W] 2.0327E-04 2.0327E-04
NOT PMOS 2 2.8136E+16 7.4689E+16 2.2509E+17 1.8992E-06 1 3.6549E+16 9.7022E+16 2.9240E+17 1.8992E-06
NMOS 1 1.0250E+17 2.7210E+17 8.2003E+17 3.4595E-06 1 6.6577E+16 1.7673E+17 5.3261E+17 3.4595E-06
Total heat [W] 5.3587E-06 5.3587E-06
94
Appendix VI - Simulation results
Table A-5. Values of maximum temperature and equivalent thermal conductivity in MOSFET and FinFET basic logic gates at different technology nodes
and with various top boundary condition temperature.
Gate name �� =
FinFET basic logic gates MOSFET basic logic gates
90 nm 65 nm 45 nm 90 nm 65 nm 45 nm
AND
300 K �� ! [K] 324.61 357.67 473.63 308.13 313.99 333.72
"#$%&' ()*+ [W/m.K] 3.11 3.50 3.80 7.80 7.89 8.02
350 K �� ! [K] 374.61 407.67 523.63 358.13 363.99 383.72
"#$%&' ()*+ [W/m.K] 3.11 3.50 3.80 7.80 7.89 8.02
400 K �� ! [K] 424.61 457.67 573.63 408.13 413.99 433.72
"#$%&' ()*+ [W/m.K] 3.11 3.50 3.80 7.80 7.89 8.02
OR
300 K �� ! [K] 370.95 408.74 541.24 311.45 317.37 334.29
"#$%&' ()*+ [W/m.K] 2.30 2.59 2.87 8.00 8.05 8.09
350 K �� ! [K] 420.95 458.74 591.24 361.45 367.37 384.29
"#$%&' ()*+ [W/m.K] 2.30 2.59 2.87 8.00 8.05 8.09
400 K �� ! [K] 470.95 508.74 641.24 411.45 417.37 434.29
"#$%&' ()*+ [W/m.K] 2.30 2.59 2.87 8.00 8.05 8.09
NAND
300 K �� ! [K] 330.59 364.27 482.36 317.43 333.68 359.21
"#$%&' ()*+ [W/m.K] 5.21 4.98 4.41 8.18 8.27 8.43
350 K �� ! [K] 380.59 414.27 532.36 367.43 383.68 409.21
"#$%&' ()*+ [W/m.K] 5.21 4.98 4.41 8.18 8.27 8.43
400 K �� ! [K] 430.59 464.27 582.36 417.43 433.68 459.21
"#$%&' ()*+ [W/m.K] 5.21 4.98 4.41 8.18 8.27 8.43
NOR
300 K �� ! [K] 365.67 402.92 533.54 327.63 340.23 370.60
"#$%&' ()*+ [W/m.K] 3.35 2.79 2.02 7.58 7.71 7.88
350 K �� ! [K] 415.67 452.92 583.54 377.63 390.23 420.60
"#$%&' ()*+ [W/m.K] 3.35 2.79 2.02 7.58 7.71 7.88
400 K �� ! [K] 465.67 502.92 633.54 427.63 440.23 470.60
"#$%&' ()*+ [W/m.K] 3.35 2.79 2.02 7.58 7.71 7.88
95
NOT
300 K �� ! [K] 302.14 315.66 387.21 300.74 311.07 330.37
"#$%&' ()*+ [W/m.K] 2.30 2.68 2.95 5.95 5.98 6.03
350 K �� ! [K] 352.14 365.66 437.21 350.74 361.07 380.37
"#$%&' ()*+ [W/m.K] 2.30 2.68 2.95 5.95 5.98 6.03
400 K �� ! [K] 402.14 415.66 487.21 400.74 411.07 430.37
"#$%&' ()*+ [W/m.K] 2.30 2.68 2.95 5.95 5.98 6.03