Vlsi Manual 2014

Ex No: SIMULATION OF BASIC GATES AD COMBINATIONAL GATES

711012106105

IMPLEMENTATION OF COMBINATIONAL LOGIC CIRCUITS- HALF ADDER, FULL ADDER AND 8 BIT ADDERS.

Ex No:

Date :

Aim:

To write a Verilog code and implement half adder, full adder and 8bit adder in Xilinx Spartan 3E FPGA kit.

Tools Required: Xilinx ISE 8.1, ModelSim SE 6.0

Procedure:a) Open file menu from sub menu. Click open

b) Enter the project name and select HDL.

c) Select the device family.

d) Create a new source and enter HDL file name and also the module name.e) Enter the input and the output variables.

f) Enter the coding in the program window and also save the program

g) Run the model sim simulator and enter the inputs.

h) Obtain the corresponding output waveforms.

Design

Half AdderTruth Table

Circuit Diagram Output

ABSC

0

0

1

10

1

0

10

1

1

00

0

0

1

Full AdderTruth Table Circuit DiagramABCinSCout

0

0

0

0

1

1

1

10

0

1

1

0

0

1

10

1

0

1

0

1

0

10

1

1

0

1

0

0

10

0

0

1

0

1

1

1

Half Adder:Program:

module halfadderm(a, b, sum, carry);

input a;

input b;

output sum;

output carry;

assign carry=a&b;

assign sum=a^b;

endmodule

TEST BENCHmodule halfaddert_v;

reg a;

reg b;

wire sum;

wire carry;

halfadderm uut (

.a(a),

.b(b),

.sum(sum),

.carry(carry)

);

initial begin

#10 a=1'b0;b=1'b0;

#10 a=1'b0;b=1'b1;

#10 a=1'b1;b=1'b0;

#10 a=1'b1;b=1'b1;

#10$stop;

end

endmodule

Full Adder

Program:

module fulladdm(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

wire d,e,f;

xor(sum,a,b,c);

and(d,a,b);

and(e,b,c);

and(f,a,c);

or(carry,d,e,f);

endmodule

TEST BENCHmodule fulladdt_v;

reg a;

reg b;

reg c;

wire sum;

wire carry;

fulladdm uut (

.a(a),

.b(b),

.c(c),

.sum(sum),

.carry(carry)

);

initial begin

#10 a=1'b0;b=1'b0;c=1'b0;

#10 a=1'b0;b=1'b0;c=1'b1;

#10 a=1'b0;b=1'b1;c=1'b0;

#10 a=1'b0;b=1'b1;c=1'b1;

#10 a=1'b1;b=1'b0;c=1'b0;

#10 a=1'b1;b=1'b0;c=1'b1;

#10 a=1'b1;b=1'b1;c=1'b0;

#10 a=1'b1;b=1'b1;c=1'b1;

#10$stop;

end

endmodule8 BIT ADDER

module ripplemod(a, b, cin, sum, cout);

input [07:0] a;

input [07:0] b;

input cin;

output [7:0]sum;

output cout;

wire[6:0] c;

fulladd a1(a[0],b[0],cin,sum[0],c[0]);

fulladd a2(a[1],b[1],c[0],sum[1],c[1]);






fulladd a8(a[7],b[7],c[6],sum[7],cout);

endmodule

module fulladd(a, b, cin, sum, cout);

input a;

input b;

input cin;

output sum;

output cout;assign sum=(a^b^cin);

assign cout=((a&b)|(b&cin)|(a&cin));

endmodule

TEST BENCHmodule rippleadder_b;

reg [7:0] a;

reg [7:0] b;

reg cin;

wire [7:0] sum;

wire cout;

ripplemod uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));

initial begin

#10 a=8b00000001;b=8b00000001;cin=1b0;

#10 a=8b00000001;b=8b00000001;cin=1b1;

#10 a=8b00000010;b=8b00000011;cin=1b0;

#10 a=8b10000001;b=8b10000001;cin=1b0;

#10 a=8b00011001;b=8b00110001;cin=1b0;

#10 a=8b00000011;b=8b00000011;cin=1b1;

#10 a=8b11111111;b=8b00000001;cin=1b0;

#10 a=8b11111111;b=8b00000000;cin=1b1;

#10 a=8b11111111;b=8b11111111;cin=1b0;

#10 $stop; end

endmodule

Simulated Waveform (Half Adder)

Simulated Waveform (Half Adder)

Simulated Waveform(8 bit Adder)

VIVA-VOCE Question:

1. What is a Logic Gate?

2. Write the names of Universal Gates.

3. Define half adder and full adder.

4. Define half subtractor and full subtractor.

5. What do you mean by carry propagation delay?

RESULT:

Thus the verilog code for the implementation of combinational logic circuits- half adder, full adder and 8 bit adder has been executed successfully and the output is verified.IMPLEMENTATION OF 4*1 MULTIPLEXER AND 1*4 DEMUX -TEST BENCH CREATION AND FUNCTIONAL VERIFICATION

Ex No:

Date :

Aim:

To write a Verilog code and to implement 4*1 Multiplexer and 1*4 Demultiplexer in Xilinx Spartan 3E FPGA kit.Tools Required: Xilinx ISE 8.1, ModelSim SE 6.0

Procedure:a) Open file menu from sub menu. Click open



d) Create a new source and enter HDL file name and also the module name.

e) Enter the input and the output variables.




4-to-1 line MUX (or) 4x1MUX

Logic Diagram.

Truth Table

S0S1Y

0

0

1

1

0

1

0

1I0

I1

I2

I3

Program (4:1 MULTIPLEXER)module muxm(a, s, o);

input [3:0] a;

input [1:0] s;

output o;

reg o;

always @(a or s)

begin

case (s)

2'b00:o=a[0];

2'b01:o=a[1];

2'b10:o=a[2];

2'b11:o=a[3];

default:o=0;

endcase

end

endmodule

TEST BENCHmodule muxt_v;

reg [3:0] a;

reg [1:0] s;

wire o;

muxm uut (

.a(a),

.s(s),

.o(o)

);

initial begin

#10 a=4'b1010;

#10 s=2'b00;

#10 s=2'b01;

#10 s=2'b10;

#10 s=2'b11;

#10 $stop;

end

endmodule

Logic Diagram(1:4 Demux)

Program (1:4 Demultiplexer)module demuxm(s,a,d);

input [0:1] s;

input a;

output [0:3] d;

reg [0:3] d;

always @(a or s)

begin

if(a==1)

begin

case (s)

2'b00:d=4'b1000;

2'b01:d=4'b0100;

2'b10:d=4'b0010;

2'b11:d=4'b0001;

default:d=0;

endcase

end else if(a==0)

d=0;

end

endmodule

TEST BENCHmodule demuxt_v;

reg [0:1] s;

reg a;

wire [0:3] d;

demuxm uut (

.s(s),

.a(a),

.d(d)

);

initial begin

#10 s=2'b00;a=1'b0;

#10 s=2'b00;a=1'b1;

#10 s=2'b01;a=1'b0;

#10 s=2'b01;a=1'b1;

#10 s=2'b10;a=1'b0;

#10 s=2'b10;a=1'b1;

#10 s=2'b11;a=1'b0;

#10 s=2'b11;a=1'b1;

#10 $stop;

end

endmoduleSimulated Waveform(4:1 MUX)

Simulated Waveform(1:4 Demux)

RESULT:

Thus the verilog code for the implementation of 4*1 multiplexer and 1*4 demultiplexer- test bench creation and functional verification has been executed successfully and the output is verified.DESIGN AND SIMULATION OF MULTIPLIER AND ADDRESS DECODER

Ex No:

Date:

Aim : To write a Verilog code and to implement 4 bit multiplier and address decoder .Tools Required: Xilinx ISE 8.1, ModelSim SE 6.0

Procedure.

a) Open file menu from sub menu. Click open








PROGRAM (4 BIT MULTIPLIER)module multipliermod(a, b, out);

input [4:0] a;

input [4:0] b;

output [9:0] out;

assign out=(a*b);

endmodule

TEST BENCHmodule multipliert_b;

reg [4:0] a;

reg [4:0] b;

wire [9:0] out;

multipliermod uut (.a(a),.b(b),.out(out));

initial begin

#10 a=4b1000;b=4b0010;

#10 a=4b0010;b=4b0010;

#10 a=4b0100;b=4b0100;

#10 a=4b1000;b=4b0001;

#10$stop;

end

endmodule

TRUTH TABLE:

INPUTOUTPUT

EABD0D1D2D3

1001111

0000111

0011011

0101101

0111110

Simulated Waveform(Multiplier)

2x4 DECODER

TRUTH TABLE

DECODERmodule decoderm(e, a, b, d);

input e;

input a;

input b;

output [7:0] d;

assign d[0]=(~e)&(~a)&(~b);

assign d[1]=(~e)&(~a)&(b);

assign d[2]=(~e)&(a)&(~b);

assign d[3]=(~e)&(a)&(b);

assign d[4]=(e)&(~a)&(~b);

assign d[5]=(e)&(~a)&(b);

assign d[6]=(e)&(a)&(~b);

assign d[7]=(e)&(a)&(b);

endmodule

TEST BENCHmodule decodert_v;

reg e;

reg a1;

reg a0; wire [3:0] d;

decoderm uut (

.e(EN),

.a0(A0),

.a1(A0),

.d(D)

);

initial begin

#10 e=1'b0;a=1'b0;b=1'b0;

#10 e=1'b0;a=1'b0;b=1'b1;

#10 e=1'b0;a=1'b1;b=1'b0;

#10 e=1'b0;a=1'b1;b=1'b1;

#10$stop;

end

endmodule

Simulated Waveform(2x4 Decoder)

VIVA-VOCE Question:

1.What is Multiplexer?

2.What is DeMultiplexer?

3.Give application of multiplexer?

4.What is the difference between Decoder and Demultiplexer?

5.What do you mean by encoder?

6. What is Decoder?

7.What do you mean by comparator?

8. Write a short note on priority encoder?

9. Distinguish between an encoder and decoder?

RESULT:

Thus the verilog code for the implementation of design and simulation of multiplier and address decoder has been executed successfully and the output is verified.IMPLEMENTATION OF D FLIP FLOP , JK FLIP FLOP AND T FLIP FLOP- TEST BENCH CREATION AND FUNCTIONAL VERIFICATION

EXPT NO. :

DATE:

Aim: To write a Verilog code and verify simulation of TFF JKFF and DFF.Tools Required.

Xilinix ISE 9.1, ModelSim SE 6.0Procedure.

a) Open file menu from sub menu. Click open








Program:T FFT FLIPFLOPmodule tffmod(t, clk, q);

input t;

input clk;

output q;

reg q;

initial q

Documents

Vlsi Manual 2014