ECE482 VLSI Lab Manual

ECE482 – VLSI DESIGN LABORATORY MANUAL

COURSE INSTRUCTORS Dr. T. ARIVOLI Mr. G. KARTHY

Mr. K. PANDIARAJ Mr. P. SIVAKUMAR

Mr. JENYFAL SAMPSON Mr. K. JEYA PRAKASH (COORDINATOR)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

KALASALINGAM UNIVERSITY

KALASALINGAM ACADEMY OF RESEARCH AND EDUCATION

Prepared By

Mr. K. Jeya Prakash

Copyright

© 2012

All rights reserved. This product or document is protected by copyright and distributed

under licenses restricting its use, copying and distribution. No part of this product or

document may be reproduced in any form by any means without prior written

authorization of authors, if any.

TRADEMARKS

Verilog is a registered trademark of Cadence Design Systems, Inc. ModelSim, Spartan,

Vertex and Xilinx are registered trademarks of Mentor Graphics. Quartus II, Altera,

Cyclone are registered trademarks of Altera Corporation. All other products, services, or

company names mentioned herein are claimed as trademarks and trade names by their

respective companies.

ECE482 VLSI DESIGN LABORATORY 3

SYLLABUS

ECE482 VLSI DESIGN LABORATORY L T P C

0 0 3 2

1. Study of Simulation tools 2. Study of Synthesis tools 3. Place and Route and back annotation for FPGAs 4. Study of development tool for FPGAs for schematic entry and Verilog 5. Design of traffic light controller using Verilog simulation tools 6. Design and simulation of pipelined serial and parallel adder to add/ subtract 8

number of size, 12 bits each in 2's complement 7. Design and simulation of back annotated Verilog files for multiplying two signed,

8 bit numbers in 2's complement. 8. Study of FPGA board and testing on board LEDs and switches using Verilog codes 9. Testing the traffic controller design on the FPGA board 10. Design a Real time Clock (2 digits, 7 segments LED displays each for HRS, MTS,

and SECS.) and demonstrate its working on the FPGA board

LIST OF EXPERIMENTS I CYCLE

1. Study of IC Design Methodology and HDL 2. Models for logic gates and multiplexer in Verilog 3. Study of Simulation tools 4. Models for flip-flops 5. Models for adders, multipliers 6. Models for counters 7. ALU Design 8. Design of Memories

II CYCLE 9. Study of Synthesis tools 10. State machines 11. Complex adders and complex multipliers 12. Study of tools for FPGAs for schematic entry 13. Study of Pin assignment and Configuring FPGA 14. Study of FPGA board and testing on board LEDs and switches 15. Design of LFSR and PRBS generator (Additional Experiment beyond syllabus) 16. Mini Project – Design of a real time clock

Aim of the course:

To expose the students to various design methodologies and simulation tools

To give Hands-on experience in designing Digital circuits with HDL After completing the course the student will be able to do logical design from specification and they will be able to verify individual Modules/Entity Warning: Copying is strictly prohibited.

4 ECE482 VLSI DESIGN LABORATORY

1 STUDY OF IC DESIGN METHODOLOGY AND HDL

Terminology

Integrated Circuits (ICs) may be classified in many ways.

Digital, Analog, and Mixed Signal - Technology

Standard IC or Application Specific IC (ASIC) - Commercial

Full Custom, Semi Custom (standard cell), and Gate Array (FPGA) – Design

Technique

IC Design Process consists of

Circuit design and Logic design (Front End)

Physical design (Layout – Back End)

Figure 1 - Typical Design Flow

© Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition by Samir Palnitkar

Date:


Tools used

Schematic entry, Spice export, Spice simulation, Layout editor

HDL entry, HDL simulator, Synthesizer, Timing Analysis, Layout (Auto Place and

Route)

Design Rule Check (DRC), Layout Versus Schematic (LVS), Parasitic capacitance

extraction

Tools

Pspice, Hspice, Tspice

ModelSim, Verilog-XL,

Design Compiler,

Prime Time, Pearl,

Silicon Ensemble, Encounter, ASTRO, IC design, L-edit

Vendors

Cadence, Mentor Graphics, Synopsys, Magma, Tanner, Magic, Lasi, Microwind

Basics

The electronic systems are built by connecting various electronic components (discrete

as well as integrated circuits). These designs are usually tested in the lab by giving

appropriate values in the inputs and checking the output with the expected values. The

same design can be done using software tools without physically having components.

For this, we need equivalent software models for the components and the connectors.

The electronic components can be modeled and interconnected using software

languages such as SPICE, VERILOG and VHDL. Of these, generally, Spice is used for analog

design, and called Hardware Description Languages are used for digital design.

There are four fundamental steps in all digital logic design. These consist of:

1. Design – The schematic or code that describes the circuit.

2. Synthesis – The intermediate conversion of human readable circuit description

to FPGA code (EDIF) format. It involves syntax checking and combining of all the

separate design files into a single file.

3. Place & Route – Where the layout of the circuit is finalized. This is the translation of

the EDIF into logic gates on the FPGA.

4. Program – The FPGA is updated to reflect the design through the use of programming

(.bit) files.

There are two sections of design for this lab. The first is the VHDL program design of

what the project has to do, where the circuit in question will be implemented. The

second step is the testbench simulation. As its name implies, it is used for testing the

project by simulating the result of driving the inputs and observing the outputs to verify

your design.

The software packages used are the Altera Quartus II and Mentor Graphics Modelsim.

Quartus II has the capability to do a variety of different design methodologies including:

Schematic Capture, Finite State Machine and Hardware Descriptive Language (VHDL or

Verilog). Although usually synthesis tool has its own simulation engine, Modelsim is


more powerful and provides greater functionality. ModelsimXE is used to verify the

behavioural functionality of the design prior to programming the FPGA.

Popularity of Verilog HDL

HDLs are high level languages like C, and easy to write and easy to debug. They are

portable. Behavioural HDL is preferred at lower level or within a module. Structural HDL

is usually done at inter module level. The models must be written with care. Syntax

errors will be identified by the simulator. But, the logical error has to be verified by the

designers. The systems designed using these languages can be verified using CAD tools.

This process is known as “SIMULATION”. The software modelling and simulation are

used to check the design concept. During IC design, the HDL will be converted to

electronic components, which have some physical representation. The conversion

process is known as “SYNTHESIS”.

Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers

many useful features

• Verilog HDL is a general-purpose hardware description language that is easy to

learn and easy to use. It is similar in syntax to the C programming language

• Verilog HDL allows different levels of abstraction to be mixed in the same model.

Thus, a designer can define a hardware model in terms of switches, gates, RTL, or

behavioural code. Also, a designer needs to learn only one language for stimulus and

hierarchical design.

• The Programming Language Interface (PLI) is a powerful feature that allows the

user to write custom C code to interact with the internal data structures of Verilog.

Designers can customize a Verilog HDL simulator to their needs with the PLI.

Design methodologies

There are two basic types of digital design methodologies: a top-down design

methodology and a bottom-up design methodology. In a top-down design methodology,

we define the top-level block and identify the sub-blocks necessary to build the top-level

block. We further subdivide the sub-blocks until we come to leaf cells, which are the

cells that cannot further be divided. Figure 2 shows the top-down design process

Figure 2 - Top-Down design methodology



In a bottom-up design methodology, we first identify the building blocks that are

available to us. We build bigger cells, using these building blocks. These cells are then

used for higher-level blocks until we build the top-level block in the design. Figure 3

shows the bottom-up design process.

Figure 3 - Bottom-Up design methodology


Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


2 MODELS FOR LOGIC GATES AND MULTIPLEXER IN VERILOG

Aim

To write the Verilog HDL for Logic gates and multiplexer

Preparation

Write Truth Table for Logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR).

Write Truth Table for Multiplexer using select signal. Draw schematics using basic

logic gates.

Write the behavior of the gates. Writ the behavior of multiplexer.

Theory

Structure of a module

A module is the basic building block in Verilog. A module can be an element or a

collection of lower-level design blocks. Typically, elements are grouped into modules to

provide common functionality that is used at many places in the design. A module

provides the necessary functionality to the higher-level block through its port interface

(inputs and outputs), but hides the internal implementation. This allows the designer to

modify module internals without affecting the rest of the design. In Verilog, a module is

declared by the keyword module. A corresponding keyword endmodule must appear at

the end of the module definition. Each module must have a module_name, which is the

identifier for the module, and a module_terminal_list, which describes the input and

output terminals called ports of the module.

module <module_name> (<module_terminal_list>);

...

<module internals>

<functionality of each block>

...

endmodule

Assignment Statements

Continuous Assignment Statements are the statements of assignments on nets which

are continuous and automatic. This means that whenever (something) an operand on

the right-hand side expression changes value during simulation, the whole right-hand

side is evaluated and assigned to the left-hand side after the delay. Continuous

assignments drive nets in a manner similar to the way gates drive nets. The format is

assign [delay] LHS-net = RHS-expression;

Procedural assignments are for updating register, integer, time, and memory variables.

The register holds the value of the assignment until the next procedural assignment to

that register.

The Verilog HDL contains two types of procedural assignment statements:

Blocking procedural assignment statements

Non-blocking procedural assignment statements

Date:


A blocking procedural assignment statement must be executed before the execution of

the statements that follow it in a sequential block (statements execute in sequence, one

after another). The non-blocking procedural assignment allows the assignments without

blocking the procedural flow (statements execute concurrently within a block). No

difference, if only one statement is there in the block.

Continuous assignments drive net variables and are evaluated and updated

continuously (whenever an input operand changes value).

Procedural assignments update the value of register variables under the control of

the procedural flow constructs that surround them.

The expression on the right-hand side can be thought of as a combinatorial circuit that

drives the net continuously. In contrast, procedural assignments put values in registers

a) Writing behavioral HDL for Logic gates using bit-wise operators

NAND Gate Data Flow Method

module my_and (in1, in2, out);

input in1, in2;

output out;

assign out = ~(in1 & in2);

endmodule

NAND Gate Procedural Method

module my_nand (in1, in2, out);

input in1, in2;

output out;

reg out;

always @ (in1 or in2)

out <= ~(in1 & in2);

endmodule


b) Writing behavioral HDL for Multiplexer.

Figure 4 – 2x1 Multiplexer

Conditional statements using if-else for 2 input Multiplexer

module my_mux (in0, in1, sel, out);

input in0, in1;

input sel;

output out;

reg out;

always @ (*)

if (sel ==1)

out = in1;

else

out = in0;

endmodule

Structural HDL for 2input multiplexer - Instantiation of modules


input in0, in1;

input sel;

output out;

my_and inst1 (in0, ~sel, a0);

my_and inst2 (in1, sel, a1);

my_or inst3 (a0, a1, out);

endmodule


Exercise 1 Model the following circuit. In a single module, generate outputs for all the

logic gates.

Figure 5 - Circuit diagram Exercise 2 Model a 2x1 multiplexer with one line continuous assignment statements,

Model an 8x1 multiplexer with case statements and adding propagation delay for the

gates


Exercises 1 and 2 solution with required truth tables and waveforms:


Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


3 STUDY OF SIMULATION TOOLS Aim

To study the simulation tools and write test bench for basic circuits

Preparation

Draw timing diagram for input and output signals of a NAND gate

Use of timescale

Write a test bench and instantiate Design Under Test

Add delay for signals. Give the input stimuli for DUT using delays.

ModelSim Tutorial

ModelSim is an IDE for hardware design which provides behavioural simulation of a

number of languages, i.e., Verilog, VHDL, and SystemC. There is a free, student version

of ModelSim that can be downloaded from the following location:

•http://www.model.com/resources/student_edition/download.asp

Follow the instructions on the page to install the program and obtain a student license,

which they will send to you via e-mail

1. Start ModelSim with one of the following:

for UNIX at the shell prompt: vsim

for Windows – from a shortcut icon, or from the Start menu

2. Upon opening ModelSim for the first time, you will see the Welcome to

ModelSim dialog (If this screen is not available, you can display it by selecting

Help > Welcome Menu from the Main window.). Click Close

3. Select Create a Project from the Welcome dialog (JumpStart > Create a

Project), or Main window (File > New > Project). In the Create

Project dialog, enter "Your_Project_Name" as the Project Name and select a

directory (Caution: Avoid a directory where windows located i.e. C: and its

subdirectories if you are working as non-administrator user account in windows)

where the project file will be stored. Leave the Default Library Name set to

"work." Upon selecting OK, you will see a blank Project tab in the workspace area

of the Main window and the Add Items to the Project dialog.

Figure 6 - ModelSim - New Project Window

Date:

http://www.model.com/resources/student_edition/download.asp


Figure 7 - ModelSim - New Project

4. The next step is to add the files that contain your design units. Click Add

Existing File in the Add items to the Project dialog. Click the Browse

button in the Add file to Project dialog and open the Verilog program files. Select

Reference from current location and then click OK. Close the Add

items to the Project dialog.

Figure 8 - ModelSim Add a Verilog File

5. Click your right mouse button in the Project tab and select

Compile > Compile All.

Figure 9 - ModelSim Compile


6. You can check your files are compiled into the work library by clicking the

library tab and expand the work library by clicking the + icon.

Figure 10 - ModeSim Compiled Files in work library

7. Load the design by double-clicking the topmost module on the

Library tab. Or you can also load the design by Simulate > Start

Simulation > Click + in work > Click top most module

name > OK. You’ll see a new page appear in the Workspace that displays the

structure of the design unit.

8. Bring up the Signals, Source, and Wave windows from Main MENU: View >

<window name> or by entering the following command at the VSIM prompt

within the Main window:

view signals source wave

9. In the workspace, click the right mouse button at the project name and select

Add to > Wave > All items in region.

Figure 11 - ModelSim Add signals to wave window


10. If the ‘wave’ windows is not docked within main window, dock to it by

clicking the dock/undock icon in the wave window.

11. Select the Run icon button on the Main window TOOLBAR. This causes the

simulation to run and then stop after 100 ns (the default simulation length) or in

the transcript command PROMPT: run or from MENU: Simulate > Run >

Run 100 ns.

12. Once the responses (outputs) of the design are noted by simulating the design

with the required stimuli (inputs), you need to conclude by ending the simulation

and closing the project. Select Simulate > End Simulation and confirm

that you want to quit simulating. Next, select File > Close > Project

and confirm that you want to close the project. Note that a

Your_Project_Name.mpf file has been created in your working directory. This file

contains information about the project test that was just created. This project

can be opened at any time in future sessions by selecting File > Open >

Project.

Test bench for simulation

Use of initial

module Test;

reg a; // registered signals

inital // specify simulation waveforms

begin

a = 1’b0; // at time = 0, a = 0

#50 a = 1’b1; // at time = 50, a = 1

#50 a = 1’b0; // at time = 100, a = 0

end

....

endmodule

A clock generator for testing – not synthesisable

// 10 MHz clock (50*1 ns*2) with 50% duty-cycle

always #50 clk = ~clk;

Outputs are to be listed using $monitor


Test bench for a 2x1 Multiplexer


input in0, in1;

input sel;

output out;

always @ (*)

if (sel ==1)

out = in1;

else //(sel == 0)

out = in0;

endmodule

module my_testbench ();

//declaring generated input signal and monitor output

signals

reg din0, din1, sel;

wire [7:0 dout;

My_mux dut1 (din0, din1, sel, dout); //instantiating DUT

//defining the values for input stimuli

initial

begin

sel = 0;

din0 =0;

din1=1;

#30 din0 = 1;

din1 =0;

#30 din0 = 0;

din1 =1;

end

always #50 sel = ~sel;

endmodule


Exercise 1 Model a three input “AND” gate, a two input “XOR” gate and simulate them

with your own test bench. Show the waveforms.

Exercises 1 solution with required truth tables and waveforms:

Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


4 MODELS FOR FLIP-FLOPS Aim

To Write the Verilog HDL programs for Flip-Flops (Registers) and verify the functionality

using Test bench.

Preparation

Draw timing diagram for D-Flip-flops

Types of Flip Flops

Initial Value: Synchronous Reset, Asynchronous Reset, Enabled FF Gated Clock

- Output does not change with all the signals. That is, signals such as reset, clock, and

enable cause the output to change. Hence output is registered.

Theory

Continuous Assignment statements: Assignments on nets are continuous and automatic.

This means that whenever an operand on the right-hand side expression changes value

during simulation, the whole right-hand side is evaluated and assigned to the left-hand

side after the delay. SO, FLIP FLOPS CAN NOT BE MODELED AS ASSIGNMENT

STATEMENTS.

Procedural Assignment statements: Procedural assignments are for updating register,

integer, time, and memory variables. The register holds the value of the assignment until

the next procedural assignment to that register. Procedural assignments update the

value of register variables under the control of the procedural flow constructs that

surround them.

D Flip-flop in Verilog

Figure 12 - D Flip-flop

always @ (posedge clk)

begin

a <= b & c;

end

always @ (posedge clk or

negedge rst )

begin

if (! rst) a <= 0;

else a <= b;

end

Date:


Example 1 (WRONG) Example 2 (CORRECT)

module test(clk, load1, a1, load2, a2, q);

input clk, load1, load2, a1, a2;

output q;

reg q;

always @ (posedge clk) begin

if (load1)

q <= a1;

end


if (load2)

q <= a2;

end

endmodule


if (load1)

q <= a1;

if (load2)

q <= a2;

end

Exercise 1 Model JK Flip Flop (Master Slave). Write test bench for the model and

simulate

Exercise 2 Model a D Flip-Flop with asynchronous Preset and Reset. Write test bench for

the model and simulate.

Exercise 3 Model a D Flip Flop with synchronous Reset. Write test bench for the model and

simulate.


Exercises 1, 2 and 3 solution with required truth tables and waveforms:


Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


5 MODELS FOR ADDERS, MULTIPLIERS Aim

To Write the Verilog HDL programs for Adders, and Multipliers and verify the

functionality using Test bench.

Preparation

How to represent more bits in Verilog?

Increase in bit width during add or multiplication operations

Signed, unsigned binary numbers – 2’s complement representation

Sign extension

Overflow estimation

Parameterize the signals

Binary numbers can be used to represent positive number or negative numbers.

During arithmetic operations, signed numbers will be used

An “N” bits binary number can represent 2^N unsigned numbers. Similarly, it can

represent (2^N)/2 positive and the same number of negative numbers in 2’s

complement representation. The most significant bit (MSB) will be 1 for negative

numbers. There are no special characters used to represent signed or unsigned number.

During arithmetic operations, the result may have increased bit width. For every

addition, one extra bit may be needed for the sum. If we don’t allow the extra bit, the

result may be overflowing. Allowing to overflowing is called wrap around. Sometimes,

the maximum value is set when overflowing – allowing the result to saturating value.

To calculate (A – B),

1. estimate –B my converting to 2’s complement

2. perform addition of A and (-B)

Types of Adders

The simplest adder structure (ripple carry adder) takes long time to estimate the sum.

There are other types of adders, which are quick but have more logic. If we set the

constraints properly, the synthesizer picks the best adder during verilog synthesis.

Types of Multipliers:

Similar to adders, there are many multipliers. Under normal circumstances, the

synthesizer will do the best job. However, in special cases, the designers model the

specific multiplier. Simple multipliers such as x2, x4, x8 are just left shift. Parameters or

`define are used to generalize the width. With a single stroke, all the bit width in the

design could be changed.

Date:


Example 1 (multibit registers):

module flip_flop (idata, clock, odata);

input [7:0] idata;

input clock;

output [7:0] odata;

reg [7:0] odata;

always @ (posedge clock)

odata <= din;

endmodule

module my_testbench ();

//declaring generated input signal and monitored output

signals

reg clk;

reg [7:0] din;

wire [7:0 dout;

//instantiating the DUT

flip_flop dut1_ff (din, clk, dout);

//defining the values for input stimuli

initial

begin

din =0;

# 30 din = 8’d1;

#30 din = 8’d3;

#30 din = 8’d15;

end

always #50 clk = ~clk;

endmodule

Use of Parameters

module add_sub (a, b, mode, out);

parameter width = 8;

input [width-1:0] a, b;

input mode;

output [width-1:0] out;

assign modified_b = mode ? {b[width-1],b} : ~{b[width-

1],b};

assign add_sub = {a[width-1],a} + modified_b + {{(width-

1){1'b0}},~mode};

endmodule


Representation of Multi-bit signals

module adder_Test;

reg [3:0] A, B; // registered signals

wire [3:0] out ;

// instantiate the device

initial // generate waveforms

begin

A = 0;

B = 0;

#10 A = 4’d1;

#10 B = 4’d1;

#10 A = 4’d2;

#10 B = 4’d3;

#10 A = 4’d3;

#10 B = 4’d7;

#10 A = 0;

#10 B = 0;

#10 $stop;

end

endmodule

Exercise 1 Model 8bits adder logic. Avoid overflow. Register the output. Simulate it with

a test bench.

Exercise 2 Model 8bit signed multiplier. Register the output. Simulate it with a test

bench.

Exercises 1 and 2 solution with required truth tables and waveforms:




Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


6 MODELS FOR COUNTERS Aim

To write the Verilog HDL programs for Counters and Linear Feedback Shift Register

(LFSR) and verify the functionality using Test bench.

Preparation

Types of counters

• Asynchronous (ripple) counter – changing state bits are used as clocks to

subsequent state flip-flops

• Synchronous counter – all state bits change under control of a single clock

• Decade counter – counts through ten states per stage

• Up/down counter – counts both up and down, under command of a control input

• Ring counter – formed by a shift register with feedback connection in a ring

• Johnson counter – a twisted ring counter

Example 1: To count the clock pulse @ every posedge

module count (clk,count,rst)

input clk,rst;

output [7:0] count;

reg [7:0] count;

always @(posedge clk)

if(rst==1)

count<=0;

else

count <= count + 1;

endmodule

Example 2: To count the clock pulse up/down @ every posedge

module up_down_counter (out, up_down, clk, reset);

output [7:0] out;

input [7:0] data;

input up_down, clk, reset;

reg [7:0] out;


if (reset) begin // active high reset

out <= 8'b0 ;

end else if (up_down) begin

out <= out + 1;

end else begin

out <= out - 1;

end

endmodule

Date:


Exercise 1 Design a decade counter and the write the test bench to simulate the design.

Exercise 2 Design a 4 bit ring counter

Exercises 1, and 2 solution with required truth tables and waveforms:



Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


7 ALU DESIGN Aim

To Write the Verilog HDL program for ALU and verify the functionality using Test bench.

Preparation

Typical use of ALU. Functions within ALU.

The input and outputs definition

Design an ALU and a test bench to evaluate that.

If – else if can be used; but, Case statement is better.

Use `define

Figure 13 - 32 bit ALU

ALU Design using Case Statement

always @(*)

case (???)

ÀDD, `SUB: result = sum;

ÀND: result = operand1 & operand2;

ÒR: result = operand1 | operand2;

`XOR: result = operand1 ^ operand2;

`SLL: result = operand1 << operand2[4:0];

`SRL: result = operand1 >> operand2[4:0];

`SRA: result = {{31{operand1[31]}}, operand1} >>

operand2[4:0];

endcase

ALU Design Using Structural Level

Logic Unit

`timescale 1ns / 1ps

module logic_unit(d_out1,logic_unit,s0,s1,c0,A,B);

output [3:0] d_out1;

input s0,s1,c0,logic_unit;

input [3:0] A;

Date:


input [3:0] B;

reg [3:0] d_out1;

always @(s0,s1,A,B,logic_unit)

begin

if(logic_unit== 1'b1)

begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 == 1'b0)

begin

d_out1 = ( A | B);

end

else if(s0 == 1'b0 & s1 == 1'b1)

begin

d_out1 = ( A ^ B);

end

else

begin

d_out1 = ( A ^~ B);

end

end

else

begin

d_out1 = 4'b0000;

end

end

endmodule

Arithmetic Module


module

arithmetic(d_out,A,B,cout,arithmetic_unit,s0,s1,c0,M);

inout [3:0] d_out;

output cout;

input s0,s1,c0,M,arithmetic_unit;

input [3:0] A,B;

wire [3:0] d_out;

reg cout;

wire s0,s1,c0,M,arithmetic_unit;

wire [3:0] A,B;

wire [3:0]D1;


wire D0;

wire [3:0]L1;

wire L0;

wire [3:0]K1;

wire K0;

reg [3:0] d_out2;

reg [3:0] temp;

reg en;

assign {D0,D1} = A + B;

assign {L0,L1} = (A + (~B));

assign {K0,K1} = ((~A) + B);

assign d_out = d_out2;

always @(s0,s1,c0,arithmetic_unit)

begin

if(arithmetic_unit)

begin

if(s1 == 1'b0 & s0 == 1'b0 & c0 == 1'b0)

begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 == 1'b0 & c0 == 1'b1)

begin

d_out2 = A + 1'b1;

end

else if(s1 == 1'b0 & s0 == 1'b1 & c0 == 1'b0)

begin

d_out2 = D1;

cout = D0;

end

else if(s1 == 1'b0 & s0 == 1'b1 & c0 == 1'b1)

begin

d_out2 = D1 + 1'b1;

cout = D0;

end

else if(s1 == 1'b1 & s0 == 1'b0 & c0 == 1'b0)

begin

d_out2 = L1;

cout = L0;

end

else if(s1 == 1'b1 & s0 == 1'b0 & c0 == 1'b1)

begin

d_out2 = L1 + 1'b1;


cout = L0;

end

else if(s1 == 1'b1 & s0 == 1'b1 & c0 == 1'b0)

begin

d_out2 = K1;

cout = K0;

end

else

begin

d_out2 = K1 + 1'b1;

cout = K0;

end

end

else

begin

d_out2 = 4'b0000;

end

end

endmodule

Main Module for ALU


module

alu(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,SEL2,

MODE);

output CRY_OUT;

output [3:0] DATA_OUT;

input CRY_IN;

input [3:0] DATA_IN1,DATA_IN2;

input SEL1,SEL2,MODE;

reg logic_unit;

reg arithmetic_unit;

wire [3:0] DATA_OUT1;

wire [3:0] DATA_OUT2;

assign DATA_OUT = (MODE ? DATA_OUT1 : DATA_OUT2);

logic_unit logic_unit_ins(.d_out1(DATA_OUT2),

.s0(SEL1),

.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),


.B(DATA_IN2),

.logic_unit(logic_unit)

);

arithmetic arithmetic_ins(.d_out(DATA_OUT1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.arithmetic_unit(arithmetic_unit)

);

always @(SEL1,SEL2,MODE)

begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;

end

else

begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;

end

end

endmodule

Test Bench for ALU:


module t_alu;

wire CRY_OUT;

wire [3:0] DATA_OUT;

reg CRY_IN;

reg [3:0] DATA_IN1,DATA_IN2;

reg SEL1,SEL2,MODE;

alu

alu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S

EL2,MODE);

initial


begin

DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;

#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b0;

#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;

#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;

#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;

#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;

#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;

#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;

#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;

#500 MODE = 1'b0;

#500 SEL1 = 1'b0; SEL2 = 1'b1;

#500 SEL1 = 1'b1; SEL2 = 1'b1;

#500 SEL1 = 1'b1; SEL2 = 1'b0;

#500 SEL1 = 1'b0; SEL2 = 1'b0;

end

Exercise 1 Design the 8 bit ALU to perform the above operations and the write the test

bench to simulate the design

Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


8 DESIGN OF MEMORIES

Aim

To Write the Verilog HDL programs for Memories and Test bench for read/ write file and

verify the functionality using Test bench.

Preparation

Memories: Different types of memory (RAM, ROM)

Dual port memories,

Register File

Example 1

Read and Write Operation in Register

module regfile(clk, weA, weB, dinA, dinB, destA, destB,

srcA, srcB, doutA, doutB);

input clk, weA, weB;

input [31:0] dinA, dinB;

input [4:0] destA, destB;

input [4:0] srcA, srcB;

output [31:0] doutA, doutB;

reg [31:0] rf [0:31];

assign doutA = srcA==0 ? 0 : rf[srcA];

assign doutB = srcB==0 ? 0 : rf[srcB];


begin

if ( weA )

rf[destA] <= dinA;

if ( weB )

rf[destB] <= dinB;

end

endmodule

Exercise 1 Design the memory and write the test bench to read contents in the memory.

Date:


Exercises 1 solution:

Result:

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


9 STUDY OF SYNTHESIS TOOLS Aim

To study the simulation tools and write test bench for basic circuits

Altera Quartus II Tutorial

Quartus II is an IDE used as synthesis tool. Quartus II has the capability to do a variety of

different design methodologies including: Schematic Capture, Finite State Machine and

Hardware Descriptive Language (VHDL or Verilog).

There is a free version of Quartus II called Xilinx web edition that can be downloaded

from the following location:

•https://www.altera.com/download/dnl-index.jsp

Follow the instructions on the page to install the program

To start working on a new design we first have to define a new design project.

Quartus II software makes the designer’s task easy by providing support in the form of a wizard. Create a new project as follows:

1. Select File > New Project Wizard to reach the window in Figure 4, which indicates the capability of this wizard. You can skip this window in subsequent projects by checking the box Don’t show me this introduction again. Press Next to get the window shown in figure13

Figure 14 – Quartus II - Creation of new project

2. Set the working directory to be introtutorial; of course, you can use some other

directory name of your choice if you prefer. The project must have a name,

which is usually the same as the top-level design entity that will be included in

the project. Choose light as the name for both the project and the top-level

entity, as shown in Figure 5. Press Next. Since we have not yet created the

directory introtutorial, Quartus II software displays the pop-up box in Figure 14

asking if it should create the desired directory. Click Yes, which leads to the

window in Figure 15.

Date:

https://www.altera.com/download/dnl-index.jsp


Figure 15 - Quartus II - Create new directory

Figure 16 - Quartus II - Add Verilog source files

3. The wizard makes it easy to specify which existing files (if any) should be included

in the project. Assuming that we do not have any existing files, click Next, which

leads to the window in Figure 16.

Figure 17 - Quartus II - Choose device family

4. We have to specify the type of device in which the designed circuit will be

implemented. Choose CycloneTM II as the target device family. We can let

Quartus II software select a specific device in the family, or we can choose the

device explicitly. We will take the latter approach. From the list of available


devices, choose the device called EP2C35F672C6 which is the FPGA used on

Altera’s DE2 board. Press Next, which opens the window in Figure 17.

Figure 18 - Quartus II - Specify other EDA tools

5. The user can specify any third-party tools that should be used. A commonly

used term for CAD software for electronic circuits is EDA tools, where the

acronym stands for Electronic Design Automation. This term is used in Quartus II

messages that refer to third-party tools, which are the tools developed and

marketed by companies other than Altera. Since we will rely solely on Quartus II

tools, we will not choose any other tools. Press Next.

6. A summary of the chosen settings appears in the screen shown in Figure 18.

Press Finish, which returns to the main Quartus II window, but with light

specified as the new project, in the display title bar, as indicated in Figure 19.

Figure 19 - Quartus II - Summary of project settings


Figure 20 - Quartus II - Display of created project

7. Integrated Synthesis generates netlists that enable you to perform functional

simulation or gate-level timing simulation, timing analysis, and formal

verification.

8. Place a copy of the file light.v, (i.e. Verilog source file) which you created using some other text editor, into the directory introtutorial. To add this file to the project, click on the File name: button in Figure 20 to get the pop-up window in Figure 21. Select the light.v file and click Open. The selected file is now indicated in the Files window of Figure 20. Click OK to include the light.v file in the project. We should mention that in many cases the Quartus II software is able to automatically find the right files to use for each entity referenced in Verilog code, even if the file has not been explicitly added to the project. However, for complex projects that involve many files it is a good design practice to specifically add the needed files to the project, as described above.

Figure 21 - Quartus II - Settings windows


Figure 22 - Quartus II - Select the Verilog source file

The Verilog code in the file light.v is processed by several Quartus II tools that analyze

the code, synthesize the circuit, and generate an implementation of it for the target

chip. These tools are controlled by the application program called the Compiler.

Run the Compiler by selecting Processing > Start Compilation, or by clicking on the

toolbar icon that looks like a purple triangle. As the compilation moves through

various stages, its progress is reported in a window on the left side of the Quartus II

display. Successful (or unsuccessful) compilation is indicated in a pop-up box.

Acknowledge it by clicking OK, which leads to the Quartus II display in Figure 22. In the

message window, at the bottom of the figure, various messages are displayed. In case of

errors, there will be appropriate messages given.

Figure 23 - Quartus II - Display after a successful compilation

When the compilation is finished, a compilation report is produced. A window showing


this report is opened automatically, as seen in Figure 22. The window can be resized,

maximized, or closed in the normal way, and it can be opened at any time either by

selecting Processing > Compilation Report or by clicking on the icon . The report

includes a number of sections listed on the left side of its window. Figure 19 displays the

Compiler Flow Summary section, which indicates that only one logic element and three

pins are needed to implement this tiny circuit on the selected FPGA chip. Another

section is shown in Figure 23. It is reached by selecting Analysis & Synthesis > Equations

on the left side of the compilation report. Here we see the logic expressions produced by

the Compiler when synthesizing the designed circuit.

Figure 24 - Quartus II - Compilation report with the synthesised equations

Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


10 STATE MACHINES Aim

To Write the Verilog HDL programs for Moore and Mealy machine and verify the

functionality using Test bench.

Preparation

What is state machine?

Types of state machines?

State machine applications.

Example 1 Moore machine

module fsm_example(clk, reset, c, valid);

input clk, reset, c;

output valid;

parameter [2:0] //

idle = 3’d0,

one_str = 3’d1,

zero_str = 3’d2,

valid_str = 3’d4,

invalid_str = 3’d3;

reg [2:0] /* synopsys enum fsm_states */ state;


if (reset)

state <= idle;

else case(state)

idle: state <= c ? one_str : invalid_str;

one_str: state <= c ? one_str : zero_str;

zero_str: state <= c ? valid_str : zero_str;

valid_str: state <= c ? valid_str : invalid_str;

invalid_str: state <= invalid_str;

default: state <= 3’bx; // dont_care conditions

endcase

// note: valid becomes msb of state register

assign valid = state == valid_str;

endmodule

Example 2 Mealy machine

module fsm_example(clk, reset, c, valid);

input clk, reset, c;

output valid;

parameter [3:0] // synopsys enum fsm_states

idle = 3’d0,

Date:


one_str = 3’d1,

zero_str = 3’d2,

valid_str = 3’d4,

invalid_str = 3’d3;

reg valid, first_one; // a wire

reg [2:0] /* synopsys enum fsm_states */ state;

// synopsys state_vector state // next state assignments

in combinational block

always @(c or state or reset)

if (reset) begin

nxt_state = idle;

valid = 0;

first_one = 0;

end

else begin

valid = 0; // put defaults here

first_one = 0; // put defaults here

case(state)

idle:

if (c) begin

nxt_state = one_str;

first_one = 1;

end else

next_state = idle;

one_str:

if (c) nxt_state = one_str;

else nxt_state = zero_str;

zero_str:

if (c) nxt_state = valid_str;

else nxt_state = zero_str;

valid_str: begin

if (c) nxt_state = valid_str;

else nxt_state = invalid_str;

valid = 1;

end

invalid_str: begin

nxt_state = invalid_str;

valid = 0;

end

default: nxt_state = 3’bx; // dont_care condi-

tions

endcase

end

// an additional sequential block is needed



state <= next_state;

endmodule

Exercise 1 Design the state machines and write the test bench to simulate the design


Result

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


11 COMPLEX ADDERS AND MULTIPLIERS Aim

To Write the Verilog HDL programs for Complex Adder and Complex Multiplier and

verify the functionality using Test bench.

Theory

Complex representation

C = A + jB (“A” is real; “jB” is imaginary)

A and B are represented by 2’s complementary numbers

Normally, it is given by (2*width) bits by {A,B}

If A = 8’b00011111 and B=8’b0; Then C is represented as 16’h1f00

The real part and imaginary part are processed separately!

If C1 = A1 + jB1; C2 = A2 + jB2 then

Sum C1+C2 = (A1+A2) + j(B1+B2)

Complex numbers are useful in DSP algorithms

Excerise1 Write the program to Find the complex conjugate of a complex number

16’h1f00 (8bits real and 8bits imaginary)

Excerise2 Find the sum for the following inputs.

A= 16’h1133; B=16’hFFFF ( A and B are in 2’s Complement format)

(Note: Most significant byte is Real, Least significant byte is Imaginary and ignore

overflow.)

Result should be in 16 bit.

Exercises 1 and 2 solution:

Date:




Result:

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


x x f

0 0 0

0 1 1 1 0 1

1 1 0

12 STUDY OF TOOLS FOR FPGAS FOR SCHEMATIC ENTRY Aim

To study about design entry using Graphic Editor.

Theory

As a design example, we will use the two-way light controller circuit shown in Figure 25.

The circuit can be used to control a single light from either of the two switches, x1 and

x2, where a closed switch corresponds to the logic value 1. The truth table for the circuit

is also given in the figure. Note that this is just the Exclusive-OR function of the inputs x1

and x2, but we will implement it using the gates shown.

x1

f

x2

The Quartus II Graphic Editor can be used to specify a circuit in the form of a block

diagram. Select File> New to get the window in Figure 26, choose Block

Diagram/Schematic File, and click OK. This opens the Graphic Editor window. The first

step is to specify a name for the file that will be created.

Figure 26 - Choose to prepare a block diagram

Figure 27 - Graphic editor windows

Figure 25 - The light controller circuit

Date:


Importing Logic-Gate Symbols

Double-click on the blank space in the Graphic Editor window, or click on the icon in

the toolbar that looks like an AND gate. A pop-up box in Figure 28 will appear. Expand

the hierarchy in the Libraries box as shown in the figure. First expand libraries, and then

expand the library primitives, followed by expanding the library logic which comprises

the logic gates. Select and2, which is a two-input AND gate, and click OK. Now, the AND

gate symbol will appear in the Graphic Editor window. Using the mouse, move the

symbol to a desirable location and click to place it there. Import the second AND gate,

which can be done simply by positioning the mouse pointer over the existing AND-gate

symbol, right-clicking, and dragging to make a copy of the symbol. A symbol in the

Graphic Editor window can be moved by clicking on it and dragging it to a new location

with the mouse button pressed. Next, select or2 from the library and import the OR gate

into the diagram. Then, select not and import two instances of the NOT gate. Rotate the

NOT gates into proper position by using the “Rotate left 90" icon . Arrange the gates as

shown in Figure 29.

Figure 28 - Choose a symbol from the library

Figure 29 - Import the gate symbols

Importing Input and Output Symbols

Use the same procedure as for importing the gates, but choose the port symbols from

the library primitives/pin. Import two instances of the input port and one instance of

the output port, to obtain the image in Figure 30


Figure 30 - Import the input and output pins

Assign names to the input and output symbols as follows. Point to the word pin_name

on the top input symbol and double-click the mouse. The dialog box in Figure 31 will

appear. Type the pin name, x1, and click OK. Similarly, assign the name x2 to the other

input and f to the output.

Figure 31 - Naming of a pin

Connecting Nodes with Wires

The symbols in the diagram have to be connected by drawing lines (wires). Click on the

icon in the toolbar to activate the Orthogonal Node Tool. Position the mouse pointer

over the right edge of the x1 input pin. Click and hold the mouse button and drag the

mouse to the right until the drawn line reaches the pinstub on the top input of the AND

gate. Release the mouse button, which leaves the line connecting the two pinstubs.

Next, draw a wire from the input pinstub of the leftmost NOT gate to touch the wire that

was drawn above it. A dot will appear indicating a connection between the two wires.

Use the same procedure to draw the remaining wires in the circuit. If a mistake is made,

a wire can be selected by clicking on it, and removed by pressing the Delete key on the

keyboard. Upon completing the diagram, click on the icon , to activate the Selection

and Smart Drawing Tool. Now, changes in the appearance of the diagram can be made

by selecting a particular symbol or wire and either moving it to a different location or

deleting it. The final diagram is shown in Figure 32; save it


Figure 32 - The completed schematic diagram

Compile the Designed Circuit

Result:

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


13 STUDY OF PIN ASSIGNMENT AND CONFIGURING FPGA Aim

To study about pin assignment and configuring FPGA for the simple circuit designed in

previous experiment.

Theory

Physical Pin Assignment

During the compilation above, the Quartus II Compiler was free to choose any pins on

the selected FPGA to serve as inputs and outputs. However, the DE1 board has

hardwired connections between the FPGA pins and the other components on the board

such as the LEDs, switches, 7 segments displays etc. We will use two toggle switches,

labeled SW 0 and SW 1, to provide the external inputs, x 1 and x 2 in our example circuit.

These switches are connected to the FPGA x 1 = SW 0= PIN_L22 and x 2 = SW 1 =

PIN_L21, respectively. We will connect the output f to the green light-emitting diode

labeled LEDG 0 which is hardwired to the FPGA pin PIN_U22. To map the pins shown on

our circuit diagram to physical pins on the FPGA that are connected to the switches and

LEDs we require, right mouse click on a pin in the circuit diagram and when the pop-up

menu appears select “Locate‟ -> “Locate in Pin Planner‟ The Pin Planner is opened as

shown below listing all the inputs/outputs of our circuit.

Figure 33 - Pin planner

In the “Location‟ cell to the right of each signal, enter the FPGA pin that we want that

signal to connect to on the FPGA, to make an assignment of circuit pin to physical FPGA

pin, type the physical FPGA pin name into the cell next to the signal, e.g. for output “f‟

above, type in the name U22 (note you don‟t have to type in the full PIN_U22 although

Date:


you can if you want). Do the same for the other inputs x1 and x2 as shown in the Figure

below

Figure 34 - Pin assignment for the circuit

Now you have made the pin assignments, close the Pin Planner above and

IMPORTANTLY Recompile the circuit, so that it will be compiled with the correct pin

assignments.

Simulating the Designed Circuit

Before implementing the designed circuit in the FPGA chip on the DE1 board, it is

prudent to simulate it to ascertain its correctness. Quartus II software includes a

simulation tool that can be used to simulate the behaviour of a designed circuit. Before

the circuit can be simulated, it is necessary to create the desired waveforms, called test

vectors, to represent the input signals. It is also necessary to specify which outputs, as

well as possible internal points in the circuit, the designer wishes to observe. The

simulator applies the test vectors to a model of the implemented circuit and determines

the expected response. We will use the Quartus II Waveform Editor to draw the test

vectors, as follows:

1. Open the Waveform Editor window by selecting File > New. Click on the Other

Files tab. Choose Vector Waveform File and click OK.

2. Save the file under the name light.vwf; note that this changes the name in the

displayed window. Set the desired simulation to run from 0 to 200 ns by selecting

Edit > End Time and entering 200 ns in the dialog box that pops up. Selecting

View > Fit in Window displays the entire simulation range of 0 to 200 ns in the

window.


3. Next, we want to include the input and output nodes of the circuit to be

simulated. Click Edit > Insert Node or Bus. It is possible to type the name of a

signal (pin) into the Name box, but it is easier to click on the button labelled

Node Finder. The Node Finder utility has a filter used to indicate what type of

nodes are to be found. Since we are interested in input and output pins, set the

filter to Pins: all. Click the List button to find the input and output. Click on the x1

signal in the Nodes Found box, and then click the > sign to add it to the Selected

Nodes box on the right side of the figure. Do the same for x2 and f. Click OK to

close the Node Finder window, and then click OK. This leaves a fully displayed

Waveform Editor window, as shown in Figure 35.

Figure 35 - Waveform Editor

4. We will now specify the logic values to be used for the input signals x1 and x2

during simulation. The logic values at the output f will be generated

automatically by the simulator. The waveforms can be drawn using the Selection

Tool, which is activated by selecting the icon in the toolbar, or the Waveform

Editing Tool, which is activated by the icon . To simulate the behaviour of a

large circuit, it is necessary to apply a sufficient number of input valuations and

observe the expected values of the outputs. We will use four 50-ns time intervals

to apply the four test vectors. We can generate the desired input waveforms as

follows. Click on the waveform name for the x1 node. Once a waveform is

selected, the editing commands in the Waveform Editor can be used to draw the

desired waveforms. Commands are available for setting a selected signal to 0, 1,

unknown (X), high impedance (Z), don’t care (DC), inverting its existing value

(INV), or defining a clock waveform. Each command can be activated by using the

Edit > Value command, or via the toolbar for the Waveform Editor. The Edit

menu can also be opened by right-clicking on a waveform name Set x1 to 0 in the

time interval 0 to 100 ns, which is probably already set by default. Next, set x1 to

1 in the time interval 100 to 200 ns. Do this by pressing the mouse at the start of

the interval and dragging it to its end, which highlights the selected interval, and

choosing the logic value 1 in the toolbar. Make x2 = 1 from 50 to 100 ns and also

from 150 to 200 ns. This should produce the image in Figure 36. Save the file.


Figure 36 - Setting of test values

Performing the simulation

A designed circuit can be simulated in two ways. The simplest way is to assume that

logic elements and interconnection wires in the FPGA are perfect, thus causing no delay

in propagation of signals through the circuit. This is called functional simulation. A more

complex alternative is to take all propagation delays into account, which leads to timing

simulation. Typically, functional simulation is used to verify the functional correctness of

a circuit as it is being designed. This takes much less time, because the simulation can be

performed simply by using the logic expressions that define the circuit

Functional simulation

To perform the functional simulation, select Assignments > Settings to open the Settings

window. On the left side of this window click on Simulator to display the window in

Figure 37, choose Functional as the simulation mode, and click OK. The Quartus II

simulator takes the inputs and generates the outputs defined in the light.vwf file. Before

running the functional simulation it is necessary to create the required netlist, which is

done by selecting Processing > Generate Functional Simulation Netlist. A simulation run

is started by Processing > Start Simulation, or by using the icon . At the end of the

simulation, Quartus II software indicates its successful completion and displays a

Simulation Report illustrated in Figure 38. If your report window does not show the

entire simulation time range, click on the report window to select it and choose View >

Fit in Window.

Figure 37 - Specifying the simulation mode


Figure 38 - Functional simulation report

Timing simulation

To perform the functional simulation, select Assignments > Settings to open the Settings

window. On the left side of this window click on Simulator to display the window in

Figure 37, choose Timing as the simulation mode, and click OK. Run the simulator, which

should produce the waveforms in Figure 39. Observe that there is a delay of about 6 ns

in producing a change in the signal f from the time when the input signals, x1 and x2,

change their values. This delay is due to the propagation delays in the logic element and

the wires in the FPGA device. You may also notice that a momentary change in the value

of f, from 1 to 0 and back to 1, occurs at about 106-ns point in the simulation. This glitch

is also due to the propagation delays in the FPGA device, because changes in x1 and x2

may not arrive at exactly the same time at the logic element that generates f.

Figure 39 - Timing simulation report

Programming and Configuring the FPGA device

The FPGA device must be programmed and configured to implement the designed

circuit. The required configuration file is generated by the Quartus II Compiler‟s

Assembler module. Altera‟s DE1 board allows the configuration to be done in two

different ways, known as JTAG and AS modes. The configuration data is transferred from

the host computer (which runs the Quartus II software) to the board by means of a cable

that connects a USB port on the host computer to the leftmost USB connector on the

board. To use this connection, it is necessary to have the USB-Blaster driver installed.

Before using the board, make sure that the USB cable is properly connected and turn on

the power supply switch on the board.

In the JTAG mode, the configuration data is loaded directly into the FPGA device. The

acronym JTAG stands for Joint Test Action Group. If the FPGA is configured in this

manner, it will retain its configuration as long as the power remains turned on. The

configuration information is lost when the power is turned off

The second possibility is to use the Active Serial (AS) mode. In this case, a configuration

device that includes some flash memory is used to store the configuration data. Quartus

II software places the configuration data into the configuration device on the DE1 board.


Then, this data is loaded into the FPGA upon power-up or reconfiguration. Thus, the

FPGA need not be configured by the Quartus II software if the power is turned off and

on. The choice between the two modes is made by the RUN/PROG switch on the DE1

board. The RUN position selects the JTAG mode, while the PROG position selects the AS

mode.

JTAG mode Programming

The programming and configuration task is performed as follows. Flip the RUN/PROG

switch into the RUN position. Select Tools > Programmer to reach the window in Figure

40. Here it is necessary to specify the programming hardware and the mode that should

be used. If not already chosen by default, select JTAG in the Mode box. Also, if the USB-

Blaster is not chosen by default, press the Hardware Setup... button and select the USB-

Blaster in the window that pops up, as shown in Figure 41.

Figure 40 - The programmer window

Figure 41 - The Hardware setup window

Observe that the configuration file light.sof is listed in the window in Figure 40. If the file

is not already listed, then click Add File and select it. This is a binary file produced by the

Compiler’s Assembler module, which contains the data needed to configure the FPGA

device. The extension .sof stands for SRAM Object File. Note also that the device

selected is EP2C20F484C7, which is the FPGA device used on the DE1 board. Click on the

Program/Configure check box, as shown in Figure 42.

Figure 42 - The updated Programmer window


Now, press Start in the window in Figure 42. An LED on the board will light up when the

configuration data has been downloaded successfully. If an error is reported by Quartus

II software indicating that programming failed, check to ensure that the board is

properly powered on.

Active Serial mode Programming

In this case, the configuration data has to be loaded into the configuration device on the

DE1 board, which is identified by the name EPCS4. To specify the required configuration

device select Assignments > Device. Now, Click the Device & Pin. Then, click on the

Configuration tab. In the Configuration device box (which may be set to Auto) choose

EPCS4 and click OK. Click OK again. Recompile the designed circuit.

The rest of the procedure is similar to the one described above for the JTAG mode.

Select Tools > Programmer. In the Mode box select Active Serial Programming. If you are

changing the mode from the previously used JTAG mode, a pop-up box will appear,

asking if you want to clear all devices. Click Yes. Now, the Programmer window will

appear. Make sure that the Hardware Setup indicates the USB-Blaster. If the

configuration file is not already listed in the window, press Add File. Select the file

light.pof in the directory introtutorial and click Open. As a result, the configuration file

light.pof will be listed in the window. This is a binary file produced by the Compiler’s

Assembler module, which contains the data to be loaded into the EPCS4 configuration

device. The extension .pof stands for Programmer Object File. Upon returning to the

Programmer window, click on the Program/Configure check box, as shown in Figure 43.

Figure 43 - The programmer window (AS mode)

Flip the RUN/PROG switch on the DE2 board to the PROG position. Press Start in the

window in Figure43. An LED on the board will light up when the configuration data has

been downloaded successfully. Also, the Progress box in Figure 43 will indicate 100%,

when the configuration and programming process is completed

Testing the designed circuit

Having downloaded the configuration data into the FPGA device, you can now test the

implemented circuit. Flip the RUN/PROG switch to RUN position. Try all four valuations

of the input variables x1 and x2, by setting the corresponding states of the switches SW1

and SW0. Verify that the circuit implements the truth table of the circuit considered. If


you want to make changes in the designed circuit, first close the Programmer window.

Then make the desired changes in the Block Diagram/Schematic file or Verilog/VHDL file,

compile the circuit, and program the board as explained above.

Result:

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


14 STUDY OF FPGA BOARD AND TESTING ON BOARD LEDS AND

SWITCHES

Aim

The purpose of this exercise is to learn how to connect simple input and output devices

to an FPGA chip and implement a circuit that uses these devices. We will use the

switches SW9−0 on the DE1 board as inputs to the circuit. We will use light emitting

diodes (LEDs) and 7-segment displays as output devices.

Implementation

The DE1 board provides 10 toggle switches, called SW9−0 , that can be used as inputs to

a circuit, and 10 red lights, called LEDR9−0 , that can be used to display output values.

Since there are 10 switches and lights it is convenient to represent them as vectors in

the Verilog code, as shown. We have used a single assignment statement for all 10 LEDR

outputs, which is equivalent to the individual assignments

assign LEDR[9] = SW[9];


...


The DE1 board has hardwired connections between its FPGA chip and the switches and

lights. To use SW9−0 and LEDR9−0 it is necessary to include in your Quartus II project

the correct pin assignments, which are given in the DE1 User Manual. For example, the

manual specifies that SW0 is connected to the FPGA pin L22 and LEDR0 is connected to

pin R20. A good way to make the required pin assignments is to import into the Quartus

II software the file called DE1 pin assignments.csv, which is provided on the DE1 System

CD and in the University Program section of Altera’s web site. It is important to realize

that the pin assignments in the DE1 pin assignments.csv file are useful only if the pin

names given in the file are exactly the same as the port names used in your Verilog

module. The file uses the names SW[0] ... SW[9] and LEDR[0] ... LEDR[9] for the switches

and lights.

// Simple module that connects the SW switches to the

LEDR lights

module part1 (SW, LEDR);

input [9:0] SW; // toggle switches

output [9:0] LEDR; // red LEDs

assign LEDR = SW;

endmodule

Perform the following steps to implement a circuit corresponding to the code on the

DE1 board.

Date:


1. Create a new Quartus II project for your circuit. Select Cyclone II EP2C20F484C7

as the target chip, which is the FPGA chip on the Altera DE1 board.

2. Create a Verilog module for the code and include it in your project.

3. Include in your project the required pin assignments for the DE1 board, as

discussed above. Compile the project.

4. Download the compiled circuit into the FPGA chip.

5. Test the functionality of the circuit by toggling the switches and observing the

LEDs.

Exercise Figure shows a 7-segment decoder module that has the two-bit input c1 c0.

This decoder produces seven outputs that are used to display a character on a 7-

segment display. Table 1 lists the characters that should be displayed for each valuation

of c1 c0. To keep the design simple, only three characters are included in the table (plus

the ‘blank’ character, which is selected for codes 11). The seven segments in the display

are identified by the indices 0 to 6 shown in the figure. Each segment is illuminated by

driving it to the logic value 0. You are to write a Verilog module that implements logic

functions that represent circuits needed to activate each of the seven segments. Use

only simple Verilog assign statements in your code to specify each logic function using a

Boolean expression

c1, c0 Character

00 d

01 E

10 1

11

Test the functionality of the circuit on the FPGA.

Exercise 1 solution:

c1 7 segment

c2 decoder

Figure 44 - 7 Segment decoder



Result:

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


15 DESIGN OF LFSR AND PRBS GENERATOR Aim

Design Linear Feedback Shift Register (LFSR) and Pseudo Random Binary Sequence

(PRBS) Generator using Verilog.

Preparation

What is LFSR?

What is PRBS?

Statements to impeement PRBS, LFSR.

Theory

A PRBS sequence often come in handy in FPGA work. They're almost perfectly balanced

in other words the duty cycle or one to zero ratio, is very close to even. Although the

pattern is known and predictable, it makes a good substitute for a true random number.

In this discussion we will be talking about 'maximal LFSR' which produce a maximum

length sequence. A PRBS is sometimes also referred to as a Pseudo random number

sequence or PN. Usually the sequence is referred to by its length such as a PN7 has a

pattern length of 27-1. So let’s start with an example for a PN7. To generate an LFSR we

need a shift register and one or a few xor gates.

module prbs_generate (

// Outputs

prbs,

// Inputs

clk, reset

);

output prbs;

input clk, reset;

parameter PN = 7,

TAP1 = 6,

TAP2 = 5;

reg [PN-1:0] prbs_state;

wire prbs;

integer d;

assign prbs = prbs_state[PN-1];


if (reset)

prbs_state <= 1; //anything but the all 0s case is fine.

else

Date:


prbs_state<=

{prbs_state,prbs_state[TAP1]^prbs_state[TAP2]};

endmodule // prbs_generate

This code generates a PN7 by taking two 'taps' as they're called from the shift register,

exclusive oring them together and feeding them back into the shift register. Left to run

on its own, it will generate the a 127 bit long pattern, and then repeat. In that pattern

we have 64 1s and 63 0s. It is always one zero that is missing from the perfect balance.

The pattern also contains all of the 7 bit combinations, except the all 0s case. This gives

us a maximum run length of 1s as 7 bits, and the maximum run length of 0s as 6 bits.

Exercise 1 Design and simulate a 4 bit LFSR with test bench in Verilog.

Result:

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):


16 MINI PROJECT – DESIGN OF A REAL TIME CLOCK Aim

Design a Real time Clock (2 digits, 7 segments LED displays each for HRS, MTS, and SECS.)

and demonstrate its working on the FPGA board.

Program

Main module

module rtc(clock,a,b,c,d,e,f,rst);

input clock,rst;

output[0:6]a,b,c,d,e,f;

wire [3:0]u,v,w,x;

wire [4:0]y;

bcdcascade(clock,u,v,w,x,y,rst);

bcdtoseven sec1(u,a);

bcdtoseven sec2(v,b);

bcdtoseven min1(w,c);

bcdtoseven min2(x,d);

fi_bi_seven(y,f,e);

endmodule

//bcdtoseven coding

module bcdtoseven(x,a);

input [3:0]x;

output [0:6]a;

reg [0:6]a;

always@(x)

case(x[3:0])

4′b0000:a=7′b0000001;

4′b0001:a=7′b1001111;

4′b0010:a=7′b0010010;

4′b0011:a=7′b0000110;

4′b0100:a=7′b1001100;

4′b0101:a=7′b0100000;

4′b0111:a=7′b0001111;

4′b1000:a=7′b0000000;

4′b1001:a=7′b0000100;

endcase

endmodule

Module bcdcascaded coding

module bcdcascade(clock,u,v,w,x,y,rst);

input clock,rst;

output [3:0]u,v,w,x;

output [4:0]y;

wire ck;

fiftyone(clock,ck);

clktobcdmod10(ck,u,rst);


clktobcdmod6(u[3],v,rst);

clktobcdmod10(v[2],w,rst);

clktobcdmod6(w[3],x,rst);

hrcounter(x[2],y,rst);

endmodule

Time converter module

module fiftyone(ck,q);

input ck;

output q;

wire x,y;

modthous(ck,x);

modthous(x,y);

modfif(y,q);

endmodule

Module modulous thousand

module modthous(ck,x);

input ck;

output x;

reg [9:0]sig;

reg x;

initial sig=10′d0;

always@(posedge ck)

begin

sig=(sig+1)%1000;

x=sig[9];

end

endmodule

Modulous fifty counter module

module modfif(ck,x);

input ck;

output x;

reg [5:0]sig;

reg x;

initial sig=6′d0;

always@(posedge ck)

begin

sig=(sig+1)%50;

x=sig[5];

end

endmodule

Module clock to bcdmod6

module clktobcdmod6(clock,x,rst);

input clock,rst;

output [3:0]x;


reg [3:0]x;

initial x=4′b0000;

always@(negedge clock or negedge rst)

if(rst==0)

x=4′b0000;

else

x=(x+1)%6;

endmodule

Module clock to bcdmod10

module clktobcdmod10(clock,x,rst);

input clock,rst;

output [3:0]x;

reg [3:0]x;



if(rst==0)

x=4′b0000;

else

x=(x+1)%10;

endmodule

Hours counter module

module hrcounter(clock,x,rst);

input clock,rst;

output reg [4:0]x;



if(rst==0)

x=5′b00000;

else

x=(x+1)%24;

endmodule

Coding for segment decoder

module fi_bi_seven(x,y,z);

input [4:0]x;

output reg [6:0]y,z;

always@(x)

case(x)

5′d0:begin

y=7′b0000001;

z=7′b0000001;

end

5′d1:begin

y=7′b0000001;

z=7′b1001111;


end

5′d2:begin

y=7′b0000001;

z=7′b0010010;

end

5′d3:begin

y=7′b0000001;

z=7′b0000110;

end

5′d4:begin

y=7′b0000001;

z=7′b1001100;

end

5′d5:begin

y=7′b0000001;

z=7′b0100100;

end

5′d6:begin

y=7′b0000001;

z=7′b0100000;

end

5′d7:begin

y=7′b0000001;

z=7′b0001111;

end

5′d8:begin

y=7′b0000001;

z=7′b0000000;

end

5′d9:begin

y=7′b0000001;

z=7′b0000100;

end

5′d10:begin

y=7′b1001111;

z=7′b0000001;

end

5′d11:begin

y=7′b1001111;

z=7′b1001111;

end

5′d12:begin

y=7′b1001111;

z=7′b0010010;


end

5′d13:begin

y=7′b1001111;

z=7′b0000110;

end

5′d14:begin

y=7′b1001111;

z=7′b1001100;

end

5′d15:begin

y=7′b1001111;

z=7′b0100100;

end

5′d16:begin

y=7′b1001111;

z=7′b0100000;

end

5′d17:begin

y=7′b1001111;

z=7′b0001111;

end

5′d18:begin

y=7′b1001111;

z=7′b0000000;

end

5′d19:begin

y=7′b1001111;

z=7′b0000100;

end

5′d20:begin

y=7′b0010010;

z=7′b0000001;

end

5′d21:begin

y=7′b0010010;

z=7′b1001111;

end

5′d22:begin

y=7′b0010010;

z=7′b0010010;

end

5′d24:begin

y=7′b0010010;

z=7′b1001100;


end

endcase

endmodule

Result:

MARKS

Preparation (30):

Execution (30):

Result (20):

Viva (20):

Total (100):

Documents

ECE482 VLSI Lab Manual